diff options
Diffstat (limited to 'fpga/usrp3/top/x300/sim')
| -rw-r--r-- | fpga/usrp3/top/x300/sim/aurora_loopback/Makefile | 27 | ||||
| -rw-r--r-- | fpga/usrp3/top/x300/sim/dram_fifo/Makefile | 35 | ||||
| -rw-r--r-- | fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile | 24 |
3 files changed, 79 insertions, 7 deletions
diff --git a/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile b/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile index eb135ef4e..b7621c4a3 100644 --- a/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile +++ b/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile @@ -51,6 +51,30 @@ $(AURORA_PHY_SRCS) \ ) #------------------------------------------------- +# ModelSim Specific +#------------------------------------------------- + +MODELSIM_IP_SRCS = $(wildcard $(abspath \ +$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \ +$(IP_BUILD_DIR)/axi64_4k_2clk_fifo/sim/axi64_4k_2clk_fifo.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma_core.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/src/*.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/*.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/gt/*.v \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ +)) + +MODELSIM_LIBS += \ +unisims_ver \ +unimacro_ver \ +secureip \ +fifo_generator_v13_2_4 \ + + +MODELSIM_ARGS += glbl -t 1fs + +#------------------------------------------------- # Testbench Specific #------------------------------------------------- include $(BASE_DIR)/../sim/general/Makefile.srcs @@ -66,7 +90,8 @@ SIM_SRCS = \ $(abspath aurora_loopback_tb.sv) \ $(SIM_GENERAL_SRCS) \ $(SIM_CONTROL_SRCS) \ -$(SIM_AXI_SRCS) +$(SIM_AXI_SRCS) \ +$(MODELSIM_IP_SRCS) \ #------------------------------------------------- # Bottom-of-Makefile diff --git a/fpga/usrp3/top/x300/sim/dram_fifo/Makefile b/fpga/usrp3/top/x300/sim/dram_fifo/Makefile index 8cc56331c..6273c604c 100644 --- a/fpga/usrp3/top/x300/sim/dram_fifo/Makefile +++ b/fpga/usrp3/top/x300/sim/dram_fifo/Makefile @@ -53,15 +53,44 @@ $(IP_AXI4_BRAM_SRCS) \ ) #------------------------------------------------- +# ModelSim Specific +#------------------------------------------------- + +MODELSIM_IP_SRCS = $(wildcard $(abspath \ +$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \ +$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/sim/axi_intercon_2x64_128_bd.v \ +$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/ip/*/sim/*.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ +)) + +MODELSIM_LIBS += \ +secureip \ +fifo_generator_v13_2_4 \ +axi_register_slice_v2_1_19 \ +axi_infrastructure_v1_1_0 \ +axi_dwidth_converter_v2_1_19 \ +axi_crossbar_v2_1_20 \ +blk_mem_gen_v8_4_3 \ +axi_data_fifo_v2_1_18 \ +generic_baseblocks_v2_1_0 \ + +modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS) + +MODELSIM_ARGS = glbl -t 1fs + +#------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module +# Define only one top-level module SIM_TOP = dram_fifo_tb -SIM_SRCS = \ +SIM_SRCS += \ $(abspath dram_fifo_tb.sv) \ $(abspath axis_dram_fifo_single.sv) \ -$(IP_DDR3_32BIT_SIM_OUTS) +$(IP_DDR3_32BIT_SIM_OUTS) \ #------------------------------------------------- # Bottom-of-Makefile diff --git a/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile b/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile index 8e75817b1..6a57a5510 100644 --- a/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile +++ b/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile @@ -53,15 +53,33 @@ $(IP_AXI4_BRAM_SRCS) \ ) #------------------------------------------------- +# ModelSim Specific +#------------------------------------------------- + +MODELSIM_IP_SRCS = $(wildcard $(abspath \ +$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \ +$(IP_BUILD_DIR)/axi4_dualport_sram/sim/axi4_dualport_sram.v \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ +)) + +MODELSIM_LIBS += \ +fifo_generator_v13_2_4 \ +blk_mem_gen_v8_4_3 \ + +modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS) + +MODELSIM_ARGS += glbl -t 1fs + +#------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module +# Define only one top-level module SIM_TOP = dram_fifo_bist_tb -SIM_SRCS = \ +SIM_SRCS += \ $(abspath dram_fifo_bist_tb.sv) \ $(abspath ../dram_fifo/axis_dram_fifo_single.sv) \ -$(IP_DDR3_32BIT_SIM_OUTS) +$(IP_DDR3_32BIT_SIM_OUTS) \ #------------------------------------------------- # Bottom-of-Makefile |