aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/top/x300/bus_int_tb.v
diff options
context:
space:
mode:
Diffstat (limited to 'fpga/usrp3/top/x300/bus_int_tb.v')
-rw-r--r--fpga/usrp3/top/x300/bus_int_tb.v32
1 files changed, 32 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x300/bus_int_tb.v b/fpga/usrp3/top/x300/bus_int_tb.v
new file mode 100644
index 000000000..70103c3bf
--- /dev/null
+++ b/fpga/usrp3/top/x300/bus_int_tb.v
@@ -0,0 +1,32 @@
+`timescale 1ns/1ps
+
+module bus_int_tb();
+
+ wire GSR, GTS;
+ xlnx_glbl glbl( );
+
+ reg clk = 0;
+ reg reset = 1;
+
+ always #10 clk = ~clk;
+
+ initial $dumpfile("bus_int_tb.vcd");
+ initial $dumpvars(0,bus_int_tb);
+
+ initial
+ begin
+ #1000 reset = 0;
+ #2000000;
+ $finish;
+ end
+
+ wire sen, sclk, mosi, miso;
+ wire scl, sda;
+
+ bus_int bus_int
+ (.clk(clk), .reset(reset),
+ .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
+ .scl(scl), .sda(sda)
+ );
+
+endmodule // bus_int_tb