diff options
Diffstat (limited to 'fpga/usrp3/top/n3xx')
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_bist_image_core.yml | 90 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml | 88 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_bist_image_core.yml | 131 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml | 141 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_bist_image_core.yml | 109 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml | 103 |
6 files changed, 367 insertions, 295 deletions
diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml index d4abd6089..34325daeb 100644 --- a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml @@ -1,8 +1,10 @@ # General parameters # ----------------------------------------- schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers -license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +copyright: >- # Copyright information used in file headers + Ettus Research, A National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version rfnoc_version: '1.0' # RFNoC protocol version chdr_width: 64 # Bit width of the CHDR bus for this image @@ -12,37 +14,40 @@ default_target: 'N300_AA' # A list of all stream endpoints in design # ---------------------------------------- stream_endpoints: - ep0: # Stream endpoint name - ctrl: True # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data - ep1: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size: 16384 # We call the next endpoints 4 and 5 to keep them consistent with the # N310 version of this file - ep4: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data - ep5: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data + ep4: + ctrl: False + data: True + buff_size: 16384 + ep5: + ctrl: False + data: True + buff_size: 16384 # A list of all NoC blocks in design # ---------------------------------- noc_blocks: radio0: - block_desc: 'radio_2x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 2 fifo0: - block_desc: 'axi_ram_fifo_4x64.yml' + block_desc: 'axi_ram_fifo.yml' parameters: # These parameters match the memory interface on the N3XX NUM_PORTS: 4 MEM_DATA_W: 64 MEM_ADDR_W: 31 + # Create two non-overlapping 32 MB buffers by default FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}" FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}" MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz @@ -50,38 +55,39 @@ noc_blocks: # A list of all static connections in design # ------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect -# - srcport = Port on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Port on the destination block to connect +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect connections: - # ep0 to radio0(0) - RF0 TX - - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } - # radio0(0) to ep0 - RF0 RX - - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } - # ep1 to radio0(1) - RF1 TX - - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } - # radio0(1) to ep1 - RF1 RX - - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } - # ep4 to fifo0(0) + # RF 0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # RF 0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF 1 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # RF 1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # + # DRAM FIFO Connections - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } - # ep5 to fifo0(1) - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # # BSP Connections - - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } - - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } - - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) -# - srcport = Clock domain on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Clock domain on the destination block to connect +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect clk_domains: - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml index 1574204f2..71ac5a403 100644 --- a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml @@ -1,8 +1,10 @@ # General parameters # ----------------------------------------- schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers -license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +copyright: >- # Copyright information used in file headers + Ettus Research, A National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version rfnoc_version: '1.0' # RFNoC protocol version chdr_width: 64 # Bit width of the CHDR bus for this image @@ -12,36 +14,38 @@ default_target: 'N300_HG' # A list of all stream endpoints in design # ---------------------------------------- stream_endpoints: - ep0: # Stream endpoint name - ctrl: True # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep1: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep2: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data - ep3: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size: 32768 + ep2: + ctrl: False + data: True + buff_size: 4096 + ep3: + ctrl: False + data: True + buff_size: 4096 # A list of all NoC blocks in design # ---------------------------------- noc_blocks: - duc0: # NoC block name - block_desc: 'duc.yml' # Block device descriptor file - parameters: # Block HDL parameters + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: # Block HDL parameters NUM_PORTS: 2 ddc0: block_desc: 'ddc.yml' parameters: NUM_PORTS: 2 radio0: - block_desc: 'radio_2x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 2 replay0: block_desc: 'replay.yml' parameters: @@ -51,37 +55,45 @@ noc_blocks: # A list of all static connections in design # ------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect -# - srcport = Port on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Port on the destination block to connect +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect connections: + # RF 0 TX - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # RF 0 RX - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF 1 TX - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + # RF 1 RX - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + # + # Replay Connections - { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 } - { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 } - { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 } - { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 } - - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } - - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } - - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) -# - srcport = Clock domain on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Clock domain on the destination block to connect +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect clk_domains: - - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } - - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } - - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml index fa6710724..fe9ed9169 100644 --- a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml @@ -1,56 +1,63 @@ # General parameters # ----------------------------------------- schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers -license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +copyright: >- # Copyright information used in file headers + Ettus Research, A National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version rfnoc_version: '1.0' # RFNoC protocol version -chdr_width: 64 # Bitwidth of the CHDR bus for this block +chdr_width: 64 # Bit width of the CHDR bus for this block device: 'n310' default_target: 'N310_AA' # A list of all stream endpoints in design # ---------------------------------------- stream_endpoints: - ep0: # Stream endpoint name - ctrl: True # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data - ep1: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data - ep2: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data - ep3: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data - ep4: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data - ep5: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 16384 # Ingress buffer size for data + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size: 16384 + ep2: + ctrl: False + data: True + buff_size: 16384 + ep3: + ctrl: False + data: True + buff_size: 16384 + ep4: + ctrl: False + data: True + buff_size: 16384 + ep5: + ctrl: False + data: True + buff_size: 16384 # A list of all NoC blocks in design # ---------------------------------- noc_blocks: - radio0: - block_desc: 'radio_2x64.yml' + radio0: # NoC block name + block_desc: 'radio.yml' # Block device descriptor file + parameters: + NUM_PORTS: 2 radio1: - block_desc: 'radio_2x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 2 fifo0: - block_desc: 'axi_ram_fifo_4x64.yml' + block_desc: 'axi_ram_fifo.yml' parameters: # These parameters match the memory interface on the N3XX NUM_PORTS: 4 MEM_DATA_W: 64 MEM_ADDR_W: 31 + # Create two non-overlapping 32 MB buffers by default FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}" FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}" MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz @@ -58,49 +65,51 @@ noc_blocks: # A list of all static connections in design # ------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect -# - srcport = Port on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Port on the destination block to connect +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect connections: - # ep0 to radio0(0) - RF0 TX + # RF 0 TX - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } - # radio0(0) to ep0 - RF0 RX + # RF 0 RX - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } - # ep1 to radio0(1) - RF0 TX + # RF 1 TX - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } - # radio0(1) to ep1 - RF0 RX + # RF 1 RX - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } - # ep2 to radio1(0) - RF1 TX + # + # RF 2 TX - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 } - # radio1(0) to ep2 - RF1 RX + # RF 2 RX - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 } - # ep3 to radio1(1) - RF1 TX + # RF 3 TX - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 } - # radio1(1) to ep3 - RF1 RX + # RF 3 RX - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 } - # ep4 to fifo0(0) - - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } - - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } - # ep5 to fifo0(1) - - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } - - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # + # DRAM FIFO Connections + - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } + - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } + - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } + - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # # BSP Connections - - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } - - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } - - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } - - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } - - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } # A list of all clock domain connections in design -# ------------------------------------------ +# ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) -# - srcport = Clock domain on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Clock domain on the destination block to connect +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect clk_domains: - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml index 4826d28b6..13fd8cfc0 100644 --- a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml @@ -1,8 +1,10 @@ # General parameters # ----------------------------------------- schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers -license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +copyright: >- # Copyright information used in file headers + Ettus Research, A National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version rfnoc_version: '1.0' # RFNoC protocol version chdr_width: 64 # Bit width of the CHDR bus for this image @@ -12,44 +14,44 @@ default_target: 'N310_HG' # A list of all stream endpoints in design # ---------------------------------------- stream_endpoints: - ep0: # Stream endpoint name - ctrl: True # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep1: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep2: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep3: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep4: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data - ep5: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data - ep6: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data - ep7: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size: 32768 + ep2: + ctrl: False + data: True + buff_size: 32768 + ep3: + ctrl: False + data: True + buff_size: 32768 + ep4: + ctrl: False + data: True + buff_size: 4096 + ep5: + ctrl: False + data: True + buff_size: 4096 + ep6: + ctrl: False + data: True + buff_size: 4096 + ep7: + ctrl: False + data: True + buff_size: 4096 # A list of all NoC blocks in design # ---------------------------------- noc_blocks: - duc0: # NoC block name - block_desc: 'duc.yml' # Block device descriptor file + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file parameters: NUM_PORTS: 2 ddc0: @@ -57,7 +59,9 @@ noc_blocks: parameters: NUM_PORTS: 2 radio0: - block_desc: 'radio_2x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 2 duc1: block_desc: 'duc.yml' parameters: @@ -67,37 +71,52 @@ noc_blocks: parameters: NUM_PORTS: 2 radio1: - block_desc: 'radio_2x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 2 replay0: block_desc: 'replay.yml' parameters: NUM_PORTS: 4 + MEM_DATA_W: 64 MEM_ADDR_W: 31 # A list of all static connections in design # ------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect -# - srcport = Port on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Port on the destination block to connect +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect connections: + # Radio Connections + # RF 0 TX - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # RF 0 RX - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF 1 TX - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + # RF 1 RX - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + # + # RF 2 TX - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 } - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + # RF 2 RX - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 } + # RF 3 TX - { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 } - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 } + # RF 3 RX - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 } - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 } + # + # Replay Block Connections - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 } - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 } - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 } @@ -106,26 +125,28 @@ connections: - { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 } - { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 } - { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 } - - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } - - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } - - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } - - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } - - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time } # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) -# - srcport = Clock domain on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Clock domain on the destination block to connect +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect clk_domains: - - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } - - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } - - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } - - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc1, dstport: ce } - - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc1, dstport: ce } - - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc1, dstport: ce } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.yml b/fpga/usrp3/top/n3xx/n320_bist_image_core.yml index 95a1b5e68..478440219 100644 --- a/fpga/usrp3/top/n3xx/n320_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n320_bist_image_core.yml @@ -1,50 +1,57 @@ # General parameters # ----------------------------------------- schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers -license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +copyright: >- # Copyright information used in file headers + Ettus Research, A National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version rfnoc_version: '1.0' # RFNoC protocol version -chdr_width: 64 # Bitwidth of the CHDR bus for this block +chdr_width: 64 # Bit width of the CHDR bus for this block device: 'n320' default_target: 'N320_AA' # A list of all stream endpoints in design # ---------------------------------------- stream_endpoints: - ep0: # Stream endpoint name - ctrl: True # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep1: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - # We call the next endpoints 4 and 5 to keep them consistent with the - # N310 version of this file - ep4: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data - ep5: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 32768 # Ingress buffer size for data + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size: 32768 + # We call the next endpoints 4 and 5 to keep them consistent with the N310 + # version of this file. + ep4: + ctrl: False + data: True + buff_size: 32768 + ep5: + ctrl: False + data: True + buff_size: 32768 # A list of all NoC blocks in design # ---------------------------------- noc_blocks: radio0: - block_desc: 'radio_1x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 radio1: - block_desc: 'radio_1x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 fifo0: - block_desc: 'axi_ram_fifo_4x64.yml' + block_desc: 'axi_ram_fifo.yml' parameters: # These parameters match the memory interface on the N3XX NUM_PORTS: 4 MEM_DATA_W: 64 MEM_ADDR_W: 31 + # Create four non-overlapping 32 MB buffers by default FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}" FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}" MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz @@ -52,41 +59,43 @@ noc_blocks: # A list of all static connections in design # ------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect -# - srcport = Port on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Port on the destination block to connect +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect connections: - # ep0 to radio0(0) - RF0 TX - - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } - # radio0(0) to ep0 - RF0 RX - - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } - # ep1 to radio1(0) - RF1 TX - - { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 } - # radio1(0) to ep1 - RF1 RX - - { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 } - # ep4 to fifo0(0) + # RF 0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # RF 0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # + # RF 1 TX + - { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 } + # RF 1 RX + - { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 } + # + # DRAM FIFO Connections - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } - # ep5 to fifo0(1) - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # # BSP Connections - - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } - - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } - - { srcblk: _device_, srcport: radio_ch0, dstblk: radio0, dstport: radio_iface } - - { srcblk: _device_, srcport: radio_ch1, dstblk: radio1, dstport: radio_iface } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } - - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time } # A list of all clock domain connections in design -# ------------------------------------------ +# ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) -# - srcport = Clock domain on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Clock domain on the destination block to connect +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect clk_domains: - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml index ce0e9389a..32af29600 100644 --- a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml @@ -1,8 +1,10 @@ # General parameters # ----------------------------------------- schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers -license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +copyright: >- # Copyright information used in file headers + Ettus Research, A National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version rfnoc_version: '1.0' # RFNoC protocol version chdr_width: 64 # Bit width of the CHDR bus for this image @@ -12,28 +14,28 @@ default_target: 'N320_HG' # A list of all stream endpoints in design # ---------------------------------------- stream_endpoints: - ep0: # Stream endpoint name - ctrl: True # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 65536 # Ingress buffer size for data - ep1: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 65536 # Ingress buffer size for data - ep2: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data - ep3: # Stream endpoint name - ctrl: False # Endpoint passes control traffic - data: True # Endpoint passes data traffic - buff_size: 4096 # Ingress buffer size for data + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 65536 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size: 65536 + ep2: + ctrl: False + data: True + buff_size: 4096 + ep3: + ctrl: False + data: True + buff_size: 4096 # A list of all NoC blocks in design # ---------------------------------- noc_blocks: - duc0: # NoC block name - block_desc: 'duc.yml' # Block device descriptor file + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file parameters: NUM_PORTS: 1 ddc0: @@ -41,7 +43,9 @@ noc_blocks: parameters: NUM_PORTS: 1 radio0: - block_desc: 'radio_1x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 duc1: block_desc: 'duc.yml' parameters: @@ -51,7 +55,9 @@ noc_blocks: parameters: NUM_PORTS: 1 radio1: - block_desc: 'radio_1x64.yml' + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 replay0: block_desc: 'replay.yml' parameters: @@ -61,43 +67,52 @@ noc_blocks: # A list of all static connections in design # ------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect -# - srcport = Port on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Port on the destination block to connect +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect connections: + # RF 0 TX - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # RF 0 RX - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + # + # RF 1 TX - { srcblk: ep1, srcport: out0, dstblk: duc1, dstport: in_0 } - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + # RF 1 RX - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } - { srcblk: ddc1, srcport: out_0, dstblk: ep1, dstport: in0 } + # + # Replay Connections - { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 } - { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 } - { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 } - { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 } - - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } - - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } - - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } - - { srcblk: _device_, srcport: radio_ch0, dstblk: radio0, dstport: radio_iface } - - { srcblk: _device_, srcport: radio_ch1, dstblk: radio1, dstport: radio_iface } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } - - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time } # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) -# - srcport = Clock domain on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Clock domain on the destination block to connect +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect clk_domains: - - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - - { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce } - - { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce } - - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } - - { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce } - - { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce } - - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } |