diff options
Diffstat (limited to 'fpga/usrp3/top/n3xx')
| -rw-r--r-- | fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile | 35 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile | 35 |
2 files changed, 64 insertions, 6 deletions
diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile b/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile index 738cb12dc..1ca7ef708 100644 --- a/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile @@ -51,15 +51,44 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \ ) #------------------------------------------------- +# ModelSim Specific +#------------------------------------------------- + +MODELSIM_IP_SRCS = $(wildcard $(abspath \ +$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ +)) + +MODELSIM_LIBS += \ +secureip \ +fifo_generator_v13_2_4 \ +axi_register_slice_v2_1_19 \ +axi_infrastructure_v1_1_0 \ +axi_dwidth_converter_v2_1_19 \ +axi_crossbar_v2_1_20 \ +blk_mem_gen_v8_4_3 \ +axi_data_fifo_v2_1_18 \ +generic_baseblocks_v2_1_0 \ + +modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS) + +MODELSIM_ARGS += glbl -t 1fs + +#------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module +# Define only one top-level module SIM_TOP = dram_fifo_tb -SIM_SRCS = \ +SIM_SRCS += \ $(abspath dram_fifo_tb.sv) \ $(abspath axis_dram_fifo_single.sv) \ -$(IP_DDR3_32BIT_SIM_OUTS) +$(IP_DDR3_32BIT_SIM_OUTS) \ #------------------------------------------------- # Bottom-of-Makefile diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile index 49e673dc4..122dfff8b 100644 --- a/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile @@ -51,15 +51,44 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \ ) #------------------------------------------------- +# ModelSim Specific +#------------------------------------------------- + +MODELSIM_IP_SRCS = $(wildcard $(abspath \ +$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ +)) + +MODELSIM_LIBS += \ +secureip \ +fifo_generator_v13_2_4 \ +axi_register_slice_v2_1_19 \ +axi_infrastructure_v1_1_0 \ +axi_dwidth_converter_v2_1_19 \ +axi_crossbar_v2_1_20 \ +blk_mem_gen_v8_4_3 \ +axi_data_fifo_v2_1_18 \ +generic_baseblocks_v2_1_0 \ + +modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS) + +MODELSIM_ARGS += glbl -t 1fs + +#------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module +# Define only one top-level module SIM_TOP = dram_fifo_bist_tb -SIM_SRCS = \ +SIM_SRCS += \ $(abspath dram_fifo_bist_tb.sv) \ $(abspath ../dram_fifo/axis_dram_fifo_single.sv) \ -$(IP_DDR3_32BIT_SIM_OUTS) +$(IP_DDR3_32BIT_SIM_OUTS) \ #------------------------------------------------- # Bottom-of-Makefile |