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Diffstat (limited to 'fpga/usrp3/top/n3xx/dboards')
58 files changed, 43759 insertions, 0 deletions
diff --git a/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs new file mode 100644 index 000000000..2439e8b40 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs @@ -0,0 +1,18 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# DB COMMON Sources +################################################## +DB_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/common/, \ +PkgRegs.vhd \ +sync/CrossTrigger.vhd \ +sync/Pulser.vhd \ +sync/TdcTop.vhd \ +sync/TdcWrapper.vhd \ +sync/TdcCore.edf \ +sync/SyncRegsIfc.edf \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd b/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd new file mode 100644 index 000000000..783e86e9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd @@ -0,0 +1,314 @@ +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- This package contains functions for reading and writing N310 registers. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + + +package PkgRegs is + + + -- RegPort Type Definitions : --------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + constant kAddressWidth : integer := 16; + + subtype InterfaceData_t is std_logic_vector(31 downto 0); + type RegDataAry_t is array (natural range <>) of InterfaceData_t; + constant kRegPortDataZero : InterfaceData_t := (others => '0'); + + -- The type of the signal used to communicate from the Interface + -- component to the frameworks + type RegPortIn_t is record + Address : unsigned(kAddressWidth - 1 downto 0); + Data : InterfaceData_t; + Rd : boolean; -- Must be a one clock cycle pulse + Wt : boolean; -- Must be a one clock cycle pulse + end record; + + -- The type of the signal used to communicate to the Interface + -- component from the frameworks + -- Ready is just the Ready signal from the Handshake component. + -- Address in RegPortIn_t should be valid in the cycle where Data, DataValid, + -- or Ready are being sampled by the bus communication interface. + type RegPortOut_t is record + Data : InterfaceData_t; + DataValid : boolean; -- Must be a one clock cycle pulse + Ready : boolean; -- Must be valid one clock after Wt assertion + end record; + + -- Constants for the RegPort + constant kRegPortInZero : RegPortIn_t := ( + Address => to_unsigned(0,kAddressWidth), + Data => (others => '0'), + Rd => false, + Wt => false); + + constant kRegPortOutZero : RegPortOut_t := ( + Data => (others=>'0'), + DataValid => false, + Ready => true); + + + + -- Register Offset Types : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + -- Custom type for defining register spaces. Is it assumed that all defined register + -- addresses for each space are kOffset <= Address < kOffset+kWidth. Therefore when + -- Address equals kOffset+kWidth, we are not talking to this space but the space + -- above it. + type RegOffset_t is record + kOffset : integer; + kWidth : integer; + end record; + + constant kRegOffsetZero : RegOffset_t := (kOffset => 16#0#, kWidth => 16#04#); + + + + -- Access Functions : ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + -- Helper function to combine register ports on their way back upstream. + function "+" (L, R : RegPortOut_t) return RegPortOut_t; + + function Mask(RegPortIn : in RegPortIn_t; + kRegisterOffset : in RegOffset_t) return RegPortIn_t; + + -- Helper functions to determine when a register is targeted by the RegPort. There + -- are three groups: RegSelected, RegWrite, and RegRead. The latter two call + -- RegSelected to determine if a register is targeted and being read or written. + -- RegSelected is also overloaded to accommodate the RegOffset_t type. + -- function RegSelected (RegPortIn : RegPortIn_t; + -- RegisterOffset : RegOffset_t) return boolean; + function RegSelected (RegOffset : integer; + RegPortIn : RegPortIn_t) return boolean; + function RegWrite (Address : integer; + RegPortIn : RegPortIn_t) return boolean; + function RegRead (Address : integer; + RegPortIn : RegPortIn_t) return boolean; + + function OrArray(ArrayIn : RegDataAry_t) return std_logic_vector; + + + + + -- Flattening Functions : ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + constant kFlatRegPortInSize : natural := kAddressWidth + + InterfaceData_t'length + + 2; + + subtype FlatRegPortIn_t is std_logic_vector(kFlatRegPortInSize-1 downto 0); + + constant kFlatRegPortOutSize : natural := InterfaceData_t'length + + 2; + + subtype FlatRegPortOut_t is std_logic_vector(kFlatRegPortOutSize-1 downto 0); + + function Flatten(Var : RegPortIn_t) return FlatRegPortIn_t; + function Unflatten(Var : FlatRegPortIn_t) return RegPortIn_t; + + function Flatten(Var : RegPortOut_t) return FlatRegPortOut_t; + function Unflatten(Var : FlatRegPortOut_t) return RegPortOut_t; + + + + +end PkgRegs; + + +package body PkgRegs is + + -- Combines RegPortOut_t types together + function "+" (L, R : RegPortOut_t) return RegPortOut_t + is + variable ReturnVal : RegPortOut_t; + begin + ReturnVal := kRegPortOutZero; + ReturnVal.Data := L.Data or R.Data; + ReturnVal.DataValid := L.DataValid or R.DataValid; + ReturnVal.Ready := L.Ready and R.Ready; + return ReturnVal; + end function; + + + -- This function lops off the portion of the register bus that is + -- decoded in the InAddrSpace function in order to reduce the number of bits + -- decoded by the register read logic. Also, the Rd and Wt strobes are gated + -- as well. + function Mask(RegPortIn : in RegPortIn_t; + kRegisterOffset : in RegOffset_t) return RegPortIn_t + is + variable RegPortInVar : RegPortIn_t; + variable InSpace : boolean := false; + begin + + InSpace := (RegPortIn.Address >= kRegisterOffset.kOffset) and + (RegPortIn.Address < kRegisterOffset.kOffset + kRegisterOffset.kWidth); + + -- Compare the most significant bits of the address bus downto the LSb + -- that we just calculated. + if InSpace then + -- If in address space then allow Rd and Wt to assert + RegPortInVar.Rd := RegPortIn.Rd; + RegPortInVar.Wt := RegPortIn.Wt; + else + RegPortInVar.Rd := kRegPortInZero.Rd; + RegPortInVar.Wt := kRegPortInZero.Wt; + end if; + + RegPortInVar.Data := RegPortIn.Data; + RegPortInVar.Address := RegPortIn.Address - kRegisterOffset.kOffset; + return RegPortInVar; + end function Mask; + + + -- Returns true when this chip is selected and the address matches the register. + -- Note that RegOffset is divided by 4 before being compared against the register + -- port Address value. + function RegSelected (RegOffset : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegPortIn.Address = to_unsigned(RegOffset, RegPortIn.Address'length); + end function RegSelected; + + -- Returns true when the register is being written. + function RegWrite (Address : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegSelected(Address, RegPortIn) and RegPortIn.Wt; + end function RegWrite; + + -- Returns true when the register is being read. + function RegRead (Address : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegSelected(Address, RegPortIn) and RegPortIn.Rd; + end function RegRead; + + -- Overloaded version of RegSelected for the RegOffset_t + -- NOTE!!! Offset <= Address < Offset+Width + -- Therefore, this function assumes that when Address = Offset+Width we are talking to + -- a different register group than the one given in RegisterOffset. + -- function RegSelected (RegPortIn : RegPortIn_t; + -- RegisterOffset : RegOffset_t) return boolean is + -- begin + -- return (RegPortIn.Address >= to_unsigned(RegisterOffset.kOffset, RegPortIn.Address'length)) and + -- (RegPortIn.Address < to_unsigned(RegisterOffset.kOffset + RegisterOffset.kWidth, RegPortIn.Address'length)); + -- end function RegSelected; + + function OrArray(ArrayIn : RegDataAry_t) return std_logic_vector + is + variable ReturnVar : std_logic_vector(ArrayIn(ArrayIn'right)'range); + begin + ReturnVar := (others => '0'); + for i in ArrayIn'range loop + ReturnVar := ReturnVar or ArrayIn(i); + end loop; + return ReturnVar; + end function OrArray; + + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + + + ----------------------------------------------------- + -- REG PORTS (FROM PkgCommunicationInterface) + -- + -- subtype InterfaceData_t is std_logic_vector(31 downto 0); + -- + -- constant kAddressWidth : positive := kAddressWidth - 2; + -- + -- type RegPortIn_t is record + -- Address : unsigned(kAddressWidth - 1 downto 0); + -- Data : InterfaceData_t; + -- Rd : boolean; -- Must be a one clock cycle pulse + -- Wt : boolean; -- Must be a one clock cycle pulse + -- end record; + + function Flatten(Var : RegPortIn_t) return FlatRegPortIn_t is + variable Index : natural; + variable RetVar : FlatRegPortIn_t; + begin + Index := 0; + RetVar(Index) := to_StdLogic(Var.Wt); Index := Index + 1; + RetVar(Index) := to_StdLogic(Var.Rd); Index := Index + 1; + RetVar(Index + Var.Data'length - 1 downto Index) := std_logic_vector(Var.Data); + Index := Index + Var.Data'length; + RetVar(Index + Var.Address'length - 1 downto Index) := std_logic_vector(Var.Address); + Index := Index + Var.Address'length; + + return RetVar; + end function Flatten; + + function Unflatten(Var : FlatRegPortIn_t) return RegPortIn_t is + variable Index : natural; + variable RetVal : RegPortIn_t; + begin + Index := 0; + RetVal.Wt := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Rd := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Data := InterfaceData_t(Var(Index + RetVal.Data'length - 1 downto Index)); + Index := Index + RetVal.Data'length; + RetVal.Address := unsigned(Var(Index + RetVal.Address'length - 1 downto Index)); + Index := Index + RetVal.Address'length; + + return RetVal; + end function Unflatten; + + -- type RegPortOut_t is record + -- Data : InterfaceData_t; + -- DataValid : boolean; -- Must be a one clock cycle pulse + -- Ready : boolean; -- Must be valid one clock after Wt assertion + -- end record; + + function Flatten(Var : RegPortOut_t) return FlatRegPortOut_t is + variable Index : natural; + variable RetVar : FlatRegPortOut_t; + begin + Index := 0; + RetVar(Index) := to_StdLogic(Var.Ready); Index := Index + 1; + RetVar(Index) := to_StdLogic(Var.DataValid); Index := Index + 1; + RetVar(Index + Var.Data'length - 1 downto Index) := std_logic_vector(Var.Data); + Index := Index + Var.Data'length; + + return RetVar; + end function Flatten; + + function Unflatten(Var : FlatRegPortOut_t) return RegPortOut_t is + variable Index : natural; + variable RetVal : RegPortOut_t; + begin + Index := 0; + RetVal.Ready := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.DataValid := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Data := InterfaceData_t(Var(Index + RetVal.Data'length - 1 downto Index)); + Index := Index + RetVal.Data'length; + + return RetVal; + end function Unflatten; + + + +end PkgRegs; diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd new file mode 100644 index 000000000..70a873501 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd @@ -0,0 +1,414 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- Uses the RP and SP edges to cross a trigger from the RefClk domain to +-- the SampleClk domain. The RP FE captures the input trigger and sends it to +-- the SampleClk domain. There, it is double-synchronized but only allowed to pass +-- when the SP RE occurs. The trigger (now in the SampleClk domain) is then passed +-- through an elastic buffer before being sent on it's merry way. +-- +-- Below is the latency through this module. If you assert rTriggerIn before or after +-- the rRP RE, then you need to add/subtract the distance to the rRP RE. +-- +-- Deterministic latency through this module is (starting at the rRP RE): +-- Measured difference between rRP and sSP rising edges (using a TDC, positive value +-- if rRP rises before sSP). +-- + One period of sSP +-- + Two periods of SampleClk (Double Sync) +-- + (sElasticBufferPtr value + 1) * SampleClk Period +-- + One period of SampleClk +-- +-- How much skew between RP and SP can we allow and still safely pass triggers? +-- Our "launch" edge is essentially the RP FE, and our "latch" edge is the SP RE. +-- Consider the no skew (RP and SP edges align) case first. Our setup and hold budget +-- is balanced at T/2. Based on this, it seems we can tolerate almost T/2 skew in either +-- direction (ignoring a few Reference and Sample Clock cycles here and there). +-- My recommendation is to keep the skew to a minimum, like less than T/4. +-- In the context of the FTDC project for N310, this should be a no-brainer since +-- the SP pulses are started only a few RefClk cycles after RP. The skew is +-- easily verified by taking a FTDC measurement. If the skew is less than T/4, you can +-- sleep easy. If not, then I recommend doing a comprehensive analysis of how much +-- settling time you have between the trigger being launched from the RefClk domain +-- and latched in the SampleClk domain. +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + + +entity CrossTrigger is + port ( + aReset : in boolean; + + RefClk : in std_logic; + -- For convenience while writing this, I have only considered the N3x0 case where + -- rRP is slightly ahead of sSP in phase. + rRP : in boolean; + -- De-asserts the clock cycle after rTriggerIn asserts. Re-asserts after the + -- second falling edge of rRP, indicating new triggers can be accepted. + rReadyForInput : out boolean; + -- Only one pulse will be output for each rising edge of rTriggerIn. rTriggerIn is + -- ignored when rReadyForInput is de-asserted. All levels are ignored when Enable + -- is de-asserted. + rEnableTrigger : in boolean; + rTriggerIn : in boolean; + + SampleClk : in std_logic; + sSP : in boolean; + -- An elastic buffer just before the output is used to compensate for skew + -- in sSP pulses across boards. Default should be in the middle of the 4 bit + -- range at 7. + sElasticBufferPtr : in unsigned(3 downto 0); + -- Single-cycle pulse output. + sTriggerOut : out boolean + ); +end CrossTrigger; + + +architecture rtl of CrossTrigger is + + --vhook_sigstart + --vhook_sigend + + signal rRpFE, + rRpDly, + rTriggerToSClk, + rTriggerCaptured, + sSpRE, + sSpDly : boolean; + + signal sTriggerBuffer : unsigned(2**sElasticBufferPtr'length-1 downto 0); + signal sTriggerInSClk, sTriggerInSClk_ms : boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + attribute async_reg : string; + attribute async_reg of sTriggerInSClk : signal is "TRUE"; + attribute async_reg of sTriggerInSClk_ms : signal is "TRUE"; + +begin + + -- Reference Clock Domain Trigger Capture : ------------------------------------------- + -- The trigger input is captured whenever it is high. The captured value is reset + -- by the falling edge of rRP. + -- ------------------------------------------------------------------------------------ + + rRpFE <= rRpDly and not rRP; + + CaptureTrigger : process(aReset, RefClk) + begin + if aReset then + rTriggerCaptured <= false; + rRpDly <= false; + elsif rising_edge(RefClk) then + rRpDly <= rRP; + if not rEnableTrigger then + rTriggerCaptured <= false; + elsif rTriggerIn then + -- Capture trigger whenever the input is asserted (so this will work with single + -- cycle and multi-cycle pulses). + rTriggerCaptured <= true; + elsif rRpFE then + -- Reset the captured trigger one cycle after the rRP FE. + rTriggerCaptured <= false; + end if; + end if; + end process; + + + -- Send Trigger To Sample Clock Domain : ---------------------------------------------- + -- Send the captured trigger on the falling edge of rRP. + -- ------------------------------------------------------------------------------------ + SendTrigger : process(aReset, RefClk) + begin + if aReset then + rTriggerToSClk <= false; + elsif rising_edge(RefClk) then + if not rEnableTrigger then + rTriggerToSClk <= false; + elsif rRpFE then + rTriggerToSClk <= rTriggerCaptured; + end if; + end if; + end process; + + rReadyForInput <= not (rTriggerToSClk or rTriggerCaptured); + + -- Capture Trigger in Sample Clock Domain : ------------------------------------------- + -- On the rising edge of sSP, capture the trigger. To keep things free of + -- metastability, we double-sync the trigger into the SampleClk domain first. + -- ------------------------------------------------------------------------------------ + + ReceiveAndProcessTrigger : process(aReset, SampleClk) + begin + if aReset then + sSpDly <= false; + sTriggerBuffer <= (others => '0'); + sTriggerOut <= false; + sTriggerInSClk_ms <= false; + sTriggerInSClk <= false; + elsif rising_edge(SampleClk) then + -- Edge detector delays. + sSpDly <= sSP; + + -- Double-synchronizer for trigger. + sTriggerInSClk_ms <= rTriggerToSClk; + sTriggerInSClk <= sTriggerInSClk_ms; + + -- Delay chain for the elastic buffer. Move to the left people! Note that this + -- operation incurs at least one cycle of delay. Also note the trigger input is + -- gated with the SP RE. + sTriggerBuffer <= sTriggerBuffer(sTriggerBuffer'high-1 downto 0) & + to_stdlogic(sTriggerInSClk and sSpRE); + + -- Based on the buffer pointer value select and flop the output one more time. + sTriggerOut <= to_boolean(sTriggerBuffer(to_integer(sElasticBufferPtr))); + end if; + end process; + + -- Rising edge detectors. + sSpRE <= sSP and not sSpDly; + + +end rtl; + + + + + +-------------------------------------------------------------------------------- +-- Testbench for CrossTrigger +-- +-- Meh coverage on the triggers so far... but this tests general operation +-- and latency. +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity tb_CrossTrigger is end tb_CrossTrigger; + +architecture test of tb_CrossTrigger is + + -- Sets up a 1.25 MHz period. + constant kClksPerPulseMaxBits: integer := 10; + constant kRpPeriodInRClks : integer := 8; + constant kRpHighTimeInRClks : integer := 4; + constant kSpPeriodInRClks : integer := 100; + constant kSpHighTimeInRClks : integer := 50; + + --vhook_sigstart + signal aReset: boolean; + signal RefClk: std_logic := '0'; + signal rEnablePulser: boolean; + signal rEnableTrigger: boolean; + signal rReadyForInput: boolean; + signal rRP: boolean; + signal rTriggerIn: boolean; + signal SampleClk: std_logic := '0'; + signal sElasticBufferPtr: unsigned(3 downto 0); + signal sEnablePulser: boolean; + signal sSP: boolean; + signal sTriggerOut: boolean; + --vhook_sigend + + signal StopSim : boolean; + -- shared variable Rand : Random_t; + constant kSPer : time := 8.000 ns; -- 125.00 MHz + constant kRPer : time := 100.000 ns; -- 10.00 MHz + + signal rRfiExpected: boolean:= true; + signal sTriggerOutExpected: boolean:= false; + + procedure ClkWait( + signal Clk : in std_logic; + X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + +begin + + SampleClk <= not SampleClk after kSPer/2 when not StopSim else '0'; + RefClk <= not RefClk after kRPer/2 when not StopSim else '0'; + + --vhook_e Pulser RpPulser + --vhook_a Clk RefClk + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits) + --vhook_a cEnablePulse rEnablePulser + --vhook_a cPulse rRP + RpPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rEnablePulser, --in boolean + cPulse => rRP); --out boolean + + --vhook_e Pulser SpPulser + --vhook_a Clk SampleClk + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits) + --vhook_a cEnablePulse sEnablePulser + --vhook_a cPulse sSP + SpPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => SampleClk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => sEnablePulser, --in boolean + cPulse => sSP); --out boolean + + + main: process + procedure SendTrigger is + begin + assert rReadyForInput + report "RFI isn't high, so we can't issue a trigger" severity error; + + -- Give it some action. We need to ideally test this for every phase offset of + -- rTriggerIn with respect to the rising edge of rRP, but let's get to that later. + -- For now, wait until a rising edge on rRP and then wait for most of the period + -- to issue the trigger. + wait until rRP and not rRP'delayed; + wait for (kRpPeriodInRClks-3)*kRPer; + rTriggerIn <= true; + ClkWait(RefClk); + rTriggerIn <= false; + rRfiExpected <= false; + + -- At this point, we wait until a sSP RE, plus two SampleClks, plus sElasticBufferPtr + -- plus 1 worth of SampleClks, plus one more SampleClk, and then the trigger + -- should appear. + wait until not rRP and rRP'delayed; + wait until sSP and not sSP'delayed; + ClkWait(SampleClk,1); + ClkWait(SampleClk, to_integer(sElasticBufferPtr)+1); + sTriggerOutExpected <= true; + ClkWait(SampleClk,1); + sTriggerOutExpected <= false; + wait until not rRP and rRP'delayed; + ClkWait(RefClk,1); + rRfiExpected <= true; + end procedure SendTrigger; + + begin + rEnablePulser <= false; + sEnablePulser <= false; + rEnableTrigger <= true; + sElasticBufferPtr <= to_unsigned(7, sElasticBufferPtr'length); + + aReset <= true, false after 10 ns; + ClkWait(RefClk,5); + + -- Start up the pulsers and ensure nothing comes out of the trigger for a while. + rEnablePulser <= true; + ClkWait(RefClk, 3); + ClkWait(SampleClk, 2); + sEnablePulser <= true; + + ClkWait(RefClk, kRpPeriodInRClks*5); + assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer) + report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error; + assert (rReadyForInput) and rReadyForInput'stable(kRpPeriodInRClks*5*kRPer) + report "Ready for Input was not high before trigger!" severity error; + + + SendTrigger; + + ClkWait(RefClk, kRpPeriodInRClks*5); + + SendTrigger; + + ClkWait(RefClk, kRpPeriodInRClks*5); + + -- Turn off the trigger enable and send a trigger. + rEnableTrigger <= false; + ClkWait(RefClk); + rTriggerIn <= true; + ClkWait(RefClk); + rTriggerIn <= false; + + -- And nothing should happen. + ClkWait(RefClk, kRpPeriodInRClks*5); + assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer) + report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error; + + + ClkWait(RefClk, kRpPeriodInRClks*5); + StopSim <= true; + wait; + end process; + + + CheckRfi : process(RefClk) + begin + if falling_edge(RefClk) then + assert rReadyForInput = rRfiExpected + report "RFI didn't match expected" severity error; + end if; + end process; + + CheckTrigOut : process(SampleClk) + begin + if falling_edge(SampleClk) then + assert sTriggerOut = sTriggerOutExpected + report "Trigger Out didn't match expected" severity error; + end if; + end process; + + + --vhook_e CrossTrigger dutx + dutx: entity work.CrossTrigger (rtl) + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + rRP => rRP, --in boolean + rReadyForInput => rReadyForInput, --out boolean + rEnableTrigger => rEnableTrigger, --in boolean + rTriggerIn => rTriggerIn, --in boolean + SampleClk => SampleClk, --in std_logic + sSP => sSP, --in boolean + sElasticBufferPtr => sElasticBufferPtr, --in unsigned(3:0) + sTriggerOut => sTriggerOut); --out boolean + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd new file mode 100644 index 000000000..c6cb30f24 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd @@ -0,0 +1,362 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- The purpose of this module is to create a psuedo-clock "pulse" on the output +-- cPulse whenever cEnablePulse is asserted. +-- +-- The output period and high time are determined by the inputs cPeriod and +-- cHighTime, where cPeriod must be greater than cHighTime+2. When these values +-- are valid at the inputs, pulse cLoadLimits to load them into the pulser routine. +-- It is not recommended to leave cEnablePulse asserted when loading new limits. +-- +-- Dynamic period and duty cycle setup: +-- 1) Disable the pulser by de-asserting cEnablePulse. +-- 2) Load new period and duty cycle by modifying cPeriod and cHighTime. Pulse +-- cLoadLimits for at least one Clk cycle. +-- 3) Enable the pulser by asserting cEnablePulse. +-- 4) Repeat 1-3 as necessary. +-- +-- Static period and duty cycle setup: +-- 1) Tie cLoadLimits to asserted. +-- 2) Tie cPeriod and cHighTime to static values. +-- 3) Enable and disable the pulser by asserting and de-asserting cEnablePulser at will. +-- This input can also be tied asserted in this case. +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity Pulser is + generic ( + -- The pulse counter is kClksPerPulseMaxBits wide. + -- Why 16? Then both cPeriod and cHighTime fit nicely into one 32 bit register! + -- Minimum of 3 to make our default values for cHighTime work out. + kClksPerPulseMaxBits : integer range 3 to 32 := 16 + ); + port ( + aReset : in boolean; + Clk : in std_logic; + + -- Pulse cLoadLimits when cPeriod and cHighTime are valid. Is it not recommended to + -- load new limits when the output is enabled. + -- Alternatively, cLoadLimits can be tied high if cPeriod and cHighTime are also + -- tied to static values. + cLoadLimits : in boolean; + cPeriod : in unsigned(kClksPerPulseMaxBits - 1 downto 0); + cHighTime : in unsigned(kClksPerPulseMaxBits - 1 downto 0); + + -- When cEnablePulse is de-asserted, cPulse idles low on the following cycle. + -- When asserted, cPulse will then assert within a few cycles. + -- This input can be tied high, if desired, and the pulses will start several + -- clock cycles after aReset de-assertion. + cEnablePulse : in boolean; + + -- When cEnablePulse is asserted, cPulse will produce a rising edge every + -- cPeriod of the Clk input and a falling edge cHighTime cycles after + -- the rising edge. + cPulse : out boolean + ); +end Pulser; + + +architecture rtl of Pulser is + + signal cCounter, + cPeriodStored, + cHighTimeStored : unsigned(cPeriod'range); + + signal cSafeToStart_ms, cSafeToStart, cSafeToStartDly : boolean; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of cSafeToStart_ms : signal is "true"; + attribute ASYNC_REG of cSafeToStart : signal is "true"; + +begin + + --synthesis translate_off + CheckInputRanges : process(Clk) + begin + if falling_edge(Clk) then + -- +2 since we have the output high offset from the zero of the counter + assert (cPeriodStored > cHighTimeStored + 2) + report "cPeriod is not greater than cHighTime + 2" severity error; + -- Ensure the high time is greater than 1... + assert (cHighTimeStored > 1) + report "cHighTime is not greater than 1" severity error; + end if; + end process; + --synthesis translate_on + + + -- ------------------------------------------------------------------------------------ + -- !!! SAFE COUNTER STARTUP !!! + -- This counter starts safely, meaning it cannot start counting immediately after + -- aReset de-assertion, because the counter cannot start until cSafeToStart asserts, + -- which cannot happen until 1-2 clock cycles after aReset de-assertion. + -- ------------------------------------------------------------------------------------ + CountFreqRefPeriod: process(aReset, Clk) + begin + if aReset then + cCounter <= (others => '0'); + cSafeToStart_ms <= false; + cSafeToStart <= false; + cSafeToStartDly <= false; + cPulse <= false; + cPeriodStored <= (others => '1'); + -- This is a rather arbitrary start value, but we are guaranteed that it is + -- less than the reset value of cPeriodStored as well as greater than 2, + -- so it works well enough in case the module isn't set up correctly. + cHighTimeStored <= to_unsigned(kClksPerPulseMaxBits+2,cHighTimeStored'length); + elsif rising_edge(Clk) then + -- Create a safe counter startup signal that asserts shortly after + -- aReset de-assertion. + cSafeToStart_ms <= true; + cSafeToStart <= cSafeToStart_ms; + -- In the case where cLoadLimits and cEnablePulse are tied high, we need to give + -- them one cycle to load before starting the counter, so we delay cSafeToStart + -- by one for the counter. + cSafeToStartDly <= cSafeToStart; + + if cEnablePulse and cSafeToStartDly then + -- Simple counter increment until ceiling reached, then roll over. + if cCounter >= cPeriodStored - 1 then + cCounter <= (others => '0'); + else + cCounter <= cCounter + 1; + end if; + + -- Pulse the output when counter is between 1 and cHighTimeStored. + if cCounter = 1 then + cPulse <= true; + elsif cCounter >= cHighTimeStored+1 then + cPulse <= false; + end if; + + else + cPulse <= false; + cCounter <= (others => '0'); + end if; + + if cLoadLimits and cSafeToStart then + cPeriodStored <= cPeriod; + cHighTimeStored <= cHighTime; + end if; + end if; + end process; + +end rtl; + + +-------------------------------------------------------------------------------- +-- Testbench for Pulser +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity tb_Pulser is end tb_Pulser; + +architecture test of tb_Pulser is + + constant kClksPerPulseMaxBits : integer := 16; + + --vhook_sigstart + signal aReset: boolean; + signal cEnablePulse: boolean; + signal cHighTime: unsigned(kClksPerPulseMaxBits-1 downto 0); + signal Clk: std_logic := '0'; + signal cLoadLimits: boolean; + signal cPeriod: unsigned(kClksPerPulseMaxBits-1 downto 0); + signal cPulse: boolean; + signal cPulseDut2: boolean; + --vhook_sigend + + signal StopSim : boolean; + constant kPer : time := 10 ns; + + signal CheckPulse : boolean := false; + signal cPulseSl : std_logic := '0'; + signal cPulseDut2Sl : std_logic := '0'; + + procedure ClkWait(X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + +begin + + Clk <= not Clk after kPer/2 when not StopSim else '0'; + + main: process + begin + cEnablePulse <= false; + aReset <= true, false after 10 ns; + ClkWait(5); + + -- Ensure the pulse is quiet for a while. + ClkWait(100); + assert cPulse'stable(kPer*100) and not cPulse + report "pulse not stable at false at startup" + severity error; + + + -- Set up, then enable the pulse; expect it to go high after a few cycles. + cPeriod <= to_unsigned(250,cPeriod'length); + cHighTime <= to_unsigned(100,cPeriod'length); + cLoadLimits <= true; + ClkWait; + cLoadLimits <= false; + cEnablePulse <= true; + ClkWait(2); -- pulse rises here + wait until falling_edge(Clk); + assert cPulse report "cPulse not high two cycles after enabling" severity error; + -- After another clock cycle the checker below should be primed, so we can enable it. + ClkWait; + CheckPulse <= true; + ClkWait(to_integer(cHighTime)-1); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + + -- Check the pulse high and low for a few cycles (duplicated below, but this also + -- checks that it actually is toggling). + for i in 0 to 100 loop + ClkWait(to_integer(cPeriod) - to_integer(cHighTime)); + wait until falling_edge(Clk); + assert cPulse report "Pulse not high when expected" severity error; + ClkWait(to_integer(cHighTime)); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + end loop; + + -- Disable pulse, and check that it goes away for a long time + cEnablePulse <= false; + CheckPulse <= false; + -- 2 is about the max time for it to go away. + ClkWait(2); + ClkWait(2**kClksPerPulseMaxBits); + assert (not cPulse) and cPulse'stable(2**kClksPerPulseMaxBits*kPer) + report "disable didn't work" severity error; + + + -- Re-do all the initial tests with different periods and such. + + -- Enable the pulse, expect it to go high after a few cycles + cPeriod <= to_unsigned(10,cPeriod'length); + cHighTime <= to_unsigned(5,cPeriod'length); + cLoadLimits <= true; + ClkWait; + cLoadLimits <= false; + cEnablePulse <= true; + ClkWait(2); -- pulse rises here + wait until falling_edge(Clk); + assert cPulse report "cPulse not high two cycles after enabling" severity error; + -- After another clock cycle the checker below should be primed, so we can enable it. + ClkWait; + CheckPulse <= true; + ClkWait(to_integer(cHighTime)-1); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + + -- Check the pulse high and low for a few cycles (duplicated below, but this also + -- checks that it actually is toggling). + for i in 0 to 100 loop + ClkWait(to_integer(cPeriod) - to_integer(cHighTime)); + wait until falling_edge(Clk); + assert cPulse report "Pulse not high when expected" severity error; + ClkWait(to_integer(cHighTime)); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + end loop; + + ClkWait(100); + + + StopSim <= true; + wait; + end process; + + cPulseSl <= '1' when cPulse else '0'; + + -- Test the period and duty cycle of the pulse. + CheckPulseSpecs : process(cPulseSl) + variable LastRise : time := 0 ns; + begin + if falling_edge(cPulseSl) then + assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cHighTime)) + report "High cycles requirement not met" severity error; + elsif rising_edge(cPulseSl) then + assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cPeriod)) + report "Period requirement not met" & LF & + "Act: " & time'image(now-LastRise) & LF & + "Req: " & time'image(kPer*to_integer(cPeriod)) + severity error; + LastRise := now; + end if; + end process; + + --vhook_e Pulser dutx + dutx: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => Clk, --in std_logic + cLoadLimits => cLoadLimits, --in boolean + cPeriod => cPeriod, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => cHighTime, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => cEnablePulse, --in boolean + cPulse => cPulse); --out boolean + + + --vhook_e Pulser dut2 + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(5,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(2,kClksPerPulseMaxBits) + --vhook_a cEnablePulse true + --vhook_a cPulse cPulseDut2 + dut2: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => Clk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(5,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(2,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => true, --in boolean + cPulse => cPulseDut2); --out boolean + + cPulseDut2Sl <= '1' when cPulseDut2 else '0'; + + CheckDut2 : process (cPulseDut2Sl) + variable LastRise : time := 0 ns; + begin + if falling_edge(cPulseDut2Sl) then + assert (not CheckPulse) or (now - LastRise = kPer*2) + report "DUT 2 High cycles requirement not met" severity error; + elsif rising_edge(cPulseDut2Sl) then + assert (not CheckPulse) or (now - LastRise = kPer*5) + report "DUT 2 Period requirement not met" & LF & + "Act: " & time'image(now-LastRise) & LF & + "Req: " & time'image(kPer*5) + severity error; + LastRise := now; + end if; + end process; + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf b/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf new file mode 100644 index 000000000..a3886f6d4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf @@ -0,0 +1,23420 @@ +(edif SyncRegsIfc + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2018 03 16 14 23 36) + (program "Vivado" (version "2017.4")) + (comment "Built on 'Fri Dec 15 20:55:39 MST 2017'") + (comment "Built by 'xbuild'") + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell FDCE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port CLR (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell LUT1 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell LUT6 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + (port I5 (direction INPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell FDPE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port PRE (direction INPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library work + (edifLevel 0) + (technology (numberDefinition )) + (cell SyncRegsIfc (celltype GENERIC) + (view SyncRegsIfc (viewtype NETLIST) + (interface + (port BusClk (direction INPUT)) + (port MeasClk (direction INPUT)) + (port RefClk (direction INPUT)) + (port SampleClk (direction INPUT)) + (port aBusReset (direction INPUT)) + (port aTdcReset (direction OUTPUT)) + (port bBusReset (direction INPUT)) + (port mOffsetsDone (direction INPUT)) + (port mOffsetsValid (direction INPUT)) + (port rEnablePpsCrossing (direction OUTPUT)) + (port rEnableTdc (direction OUTPUT)) + (port rLoadRePulseCounts (direction OUTPUT)) + (port rLoadRpCounts (direction OUTPUT)) + (port rLoadRptCounts (direction OUTPUT)) + (port rPpsPulseCaptured (direction INPUT)) + (port rReRunEnable (direction OUTPUT)) + (port rResetTdc (direction OUTPUT)) + (port rResetTdcDone (direction INPUT)) + (port sLoadSpCounts (direction OUTPUT)) + (port sLoadSptCounts (direction OUTPUT)) + (port (array (rename bRegPortInFlat "bRegPortInFlat[49:0]") 50) (direction INPUT)) + (port (array (rename bRegPortOutFlat "bRegPortOutFlat[33:0]") 34) (direction OUTPUT)) + (port (array (rename mRpOffset "mRpOffset[39:0]") 40) (direction INPUT)) + (port (array (rename mSpOffset "mSpOffset[39:0]") 40) (direction INPUT)) + (port (array (rename rPulserEnableDelayVal "rPulserEnableDelayVal[3:0]") 4) (direction OUTPUT)) + (port (array (rename rRePulseHighTimeInRClks "rRePulseHighTimeInRClks[23:0]") 24) (direction OUTPUT)) + (port (array (rename rRePulsePeriodInRClks "rRePulsePeriodInRClks[23:0]") 24) (direction OUTPUT)) + (port (array (rename rRpHighTimeInRClks "rRpHighTimeInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRpPeriodInRClks "rRpPeriodInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRptHighTimeInRClks "rRptHighTimeInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRptPeriodInRClks "rRptPeriodInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sPpsClkCrossDelayVal "sPpsClkCrossDelayVal[3:0]") 4) (direction OUTPUT)) + (port (array (rename sSpHighTimeInSClks "sSpHighTimeInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSpPeriodInSClks "sSpPeriodInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSptHighTimeInSClks "sSptHighTimeInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSptPeriodInSClks "sSptPeriodInSClks[15:0]") 16) (direction OUTPUT)) + ) + (contents + (instance (rename BlkIn_iDlyPush_i_1 "BlkIn.iDlyPush_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance (rename BlkIn_iDlyPush_i_1__0 "BlkIn.iDlyPush_i_1__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename BlkIn_iDlyPush_i_1__1 "BlkIn.iDlyPush_i_1__1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename BlkIn_iDlyPush_i_1__2 "BlkIn.iDlyPush_i_1__2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename BlkIn_iDlyPush_i_1__3 "BlkIn.iDlyPush_i_1__3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance (rename BlkIn_iDlyPush_i_1__4 "BlkIn.iDlyPush_i_1__4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename BlkOut_oDataValid_i_1 "BlkOut.oDataValid_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__0 "BlkOut.oDataValid_i_1__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__1 "BlkOut.oDataValid_i_1__1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__2 "BlkOut.oDataValid_i_1__2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__3 "BlkOut.oDataValid_i_1__3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename Gen0_FDCEx_i_1 "Gen0.FDCEx_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename Gen0_FDCEx_i_1__0 "Gen0.FDCEx_i_1__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__1 "Gen0.FDCEx_i_1__1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__10 "Gen0.FDCEx_i_1__10") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_1__11 "Gen0.FDCEx_i_1__11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_1__2 "Gen0.FDCEx_i_1__2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0100")) + ) + (instance (rename Gen0_FDCEx_i_1__3 "Gen0.FDCEx_i_1__3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename Gen0_FDCEx_i_1__4 "Gen0.FDCEx_i_1__4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__5 "Gen0.FDCEx_i_1__5") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__6 "Gen0.FDCEx_i_1__6") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__7 "Gen0.FDCEx_i_1__7") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__8 "Gen0.FDCEx_i_1__8") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__9 "Gen0.FDCEx_i_1__9") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_2 "Gen0.FDCEx_i_2") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__0 "Gen0.FDCEx_i_2__0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__1 "Gen0.FDCEx_i_2__1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__2 "Gen0.FDCEx_i_2__2") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__3 "Gen0.FDCEx_i_2__3") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__4 "Gen0.FDCEx_i_2__4") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__5 "Gen0.FDCEx_i_2__5") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__6 "Gen0.FDCEx_i_2__6") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__7 "Gen0.FDCEx_i_2__7") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_3 "Gen0.FDCEx_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename Gen0_FDCEx_i_3__0 "Gen0.FDCEx_i_3__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename Gen0_FDCEx_i_3__1 "Gen0.FDCEx_i_3__1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0002")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg "IncomingOffsetHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[36]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[39]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[40]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[41]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[42]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[43]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[44]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[45]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[46]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[47]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[48]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[49]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[50]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[51]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[52]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[53]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[54]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[55]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[56]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[57]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[58]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[59]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[60]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[61]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[62]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[63]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[64]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[65]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[66]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[67]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[68]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[69]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[70]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[71]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[72]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[73]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[74]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[75]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[76]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[77]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[78]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[79]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[33].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[34].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[35].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[36].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[37].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[38].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[39].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[40].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[41].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property 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(property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[67].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[68].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename 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(property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[75].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[76].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[77].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[78].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[79].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oDataValid_reg "IncomingOffsetHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg "IncomingOffsetHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[20].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[20].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[21].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[21].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[22].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[22].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[23].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[23].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[24].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[24].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[25].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[25].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[26].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[26].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[27].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[27].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[28].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[28].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[29].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[29].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[2].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[2].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[30].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[30].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[31].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[31].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[32].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[32].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[33].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[33].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[34].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[34].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[35].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[35].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[36].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[36].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[37].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[37].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[38].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[38].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[39].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[39].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[3].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[3].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[40].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[40].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[41].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[41].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[42].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[42].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[43].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[43].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[44].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[44].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[45].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[45].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[46].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[46].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[47].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[47].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[48].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[48].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[49].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[49].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[4].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[4].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[50].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[50].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[51].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[51].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[52].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[52].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[53].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[53].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[54].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[54].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[55].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[55].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[56].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[56].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[57].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[57].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[58].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[58].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[59].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[59].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[5].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[5].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[60].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[60].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[61].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[61].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[62].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[62].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[63].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[63].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[64].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[64].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[65].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[65].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[66].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[66].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[67].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[67].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[68].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[68].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg "PpsDelayValCrossingHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg "PpsDelayValCrossingHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg "PulserEnableDelayValCrossingHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg "PulserEnableDelayValCrossingHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkIn_iDlyPush_reg "RePulse1CntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_0_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_10_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_11_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_12_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_13_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_14_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_15_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_16_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_17_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_18_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_19_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_1_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_20_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_21_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_22_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_23_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_24_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_25_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_26_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_27_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_28_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_29_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_2_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_30_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_31_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_3_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_4_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_5_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_6_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_7_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_8_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_9_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RePulse1CntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RePulse1CntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle2_reg "RePulse1CntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RePulse1CntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkIn_iDlyPush_reg "RePulse2CntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_0_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_10_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_11_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_12_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_13_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_14_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_15_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_16_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_17_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_18_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_19_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_1_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_20_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_21_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_22_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_23_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_24_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_25_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_26_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_27_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_28_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_29_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_2_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_30_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_31_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_3_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_4_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_5_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_6_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_7_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_8_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_9_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RePulse2CntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_oDataValid_reg "RePulse2CntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RePulse2CntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle2_reg "RePulse2CntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RePulse2CntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkIn_iDlyPush_reg "RpCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_0_ "RpCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_10_ "RpCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_11_ "RpCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_12_ "RpCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_13_ "RpCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_14_ "RpCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_15_ "RpCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_16_ "RpCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_17_ "RpCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_18_ "RpCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_19_ "RpCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_1_ "RpCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_20_ "RpCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_21_ "RpCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_22_ "RpCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_23_ "RpCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_24_ "RpCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_25_ "RpCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_26_ "RpCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_27_ "RpCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_28_ "RpCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_29_ "RpCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_2_ "RpCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_30_ "RpCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_31_ "RpCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_3_ "RpCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_4_ "RpCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_5_ "RpCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_6_ "RpCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_7_ "RpCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_8_ "RpCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_9_ "RpCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RpCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_oDataValid_reg "RpCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RpCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle2_reg "RpCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RpCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkIn_iDlyPush_reg "RptCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_0_ "RptCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_10_ "RptCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_11_ "RptCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_12_ "RptCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_13_ "RptCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_14_ "RptCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_15_ "RptCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_16_ "RptCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_17_ "RptCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_18_ "RptCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_19_ "RptCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_1_ "RptCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_20_ "RptCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_21_ "RptCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_22_ "RptCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_23_ "RptCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_24_ "RptCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_25_ "RptCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_26_ "RptCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_27_ "RptCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_28_ "RptCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_29_ "RptCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_2_ "RptCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_30_ "RptCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_31_ "RptCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_3_ "RptCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_4_ "RptCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_5_ "RptCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_6_ "RptCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_7_ "RptCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_8_ "RptCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_9_ "RptCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RptCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_oDataValid_reg "RptCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RptCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle2_reg "RptCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RptCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkIn_iDlyPush_reg "SpCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_0_ "SpCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_10_ "SpCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_11_ "SpCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_12_ "SpCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_13_ "SpCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_14_ "SpCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_15_ "SpCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_16_ "SpCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_17_ "SpCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_18_ "SpCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_19_ "SpCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_1_ "SpCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_20_ "SpCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_21_ "SpCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_22_ "SpCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_23_ "SpCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_24_ "SpCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_25_ "SpCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_26_ "SpCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_27_ "SpCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_28_ "SpCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_29_ "SpCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_2_ "SpCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_30_ "SpCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_31_ "SpCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_3_ "SpCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_4_ "SpCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_5_ "SpCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_6_ "SpCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_7_ "SpCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_8_ "SpCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_9_ "SpCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "SpCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_oDataValid_reg "SpCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "SpCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle2_reg "SpCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "SpCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkIn_iDlyPush_reg "SptCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_0_ "SptCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_10_ "SptCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_11_ "SptCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_12_ "SptCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_13_ "SptCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_14_ "SptCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_15_ "SptCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_16_ "SptCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_17_ "SptCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_18_ "SptCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_19_ "SptCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_1_ "SptCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_20_ "SptCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_21_ "SptCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_22_ "SptCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_23_ "SptCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_24_ "SptCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_25_ "SptCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_26_ "SptCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_27_ "SptCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_28_ "SptCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_29_ "SptCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_2_ "SptCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_30_ "SptCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_31_ "SptCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_3_ "SptCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_4_ "SptCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_5_ "SptCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_6_ "SptCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_7_ "SptCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_8_ "SptCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_9_ "SptCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "SptCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_oDataValid_reg "SptCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "SptCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle2_reg "SptCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "SptCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance aTdcResetLcl_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0200000000000000")) + ) + (instance aTdcResetLcl_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00001000")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance aTdcResetLcl_i_4 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance aTdcResetLcl_i_5 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance aTdcResetLcl_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__0 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__1 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__2 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__3 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_rep_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__0 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__3 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance bClearTdcRegs_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00000080")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance bClearTdcRegs_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000080")) + ) + (instance bClearTdcRegs_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance bClearTdcRegs_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bEnableTdc_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bEnableTdc_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bOffsetUpdated_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h05030500")) + ) + (instance bOffsetUpdated_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_0__i_1 "bPpsClkCrossDelayVal[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename bPpsClkCrossDelayVal_1__i_1 "bPpsClkCrossDelayVal[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename bPpsClkCrossDelayVal_2__i_1 "bPpsClkCrossDelayVal[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_1 "bPpsClkCrossDelayVal[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFF8")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_2 "bPpsClkCrossDelayVal[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_3 "bPpsClkCrossDelayVal[3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000100")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_0_ "bPpsClkCrossDelayVal_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_1_ "bPpsClkCrossDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_2_ "bPpsClkCrossDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_3_ "bPpsClkCrossDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPpsClkCrossEn_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bPpsClkCrossEn_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_0__i_1 "bPulserEnableDelayVal[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename bPulserEnableDelayVal_1__i_1 "bPulserEnableDelayVal[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bPulserEnableDelayVal_2__i_1 "bPulserEnableDelayVal[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bPulserEnableDelayVal_3__i_1 "bPulserEnableDelayVal[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFF8")) + ) + (instance (rename bPulserEnableDelayVal_3__i_2 "bPulserEnableDelayVal[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename bPulserEnableDelayVal_reg_0_ "bPulserEnableDelayVal_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename bPulserEnableDelayVal_reg_1_ "bPulserEnableDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_reg_2_ "bPulserEnableDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_reg_3_ "bPulserEnableDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPushPpsDelayVal_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0080000000000000")) + ) + (instance bPushPpsDelayVal_i_2 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance bPushPpsDelayVal_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance bPushPpsDelayVal_i_4 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance bPushPpsDelayVal_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPushPulserEnableDelayVal_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0080000000000000")) + ) + (instance bPushPulserEnableDelayVal_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bReRunEnable_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bReRunEnable_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_1 "bRegPortOutLcl[Data][0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_2 "bRegPortOutLcl[Data][0]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_3 "bRegPortOutLcl[Data][0]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_4 "bRegPortOutLcl[Data][0]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_5 "bRegPortOutLcl[Data][0]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAAAAFAAAAAAAEEAA")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_6 "bRegPortOutLcl[Data][0]_i_6") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_7 "bRegPortOutLcl[Data][0]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000002000")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_1 "bRegPortOutLcl[Data][10]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_2 "bRegPortOutLcl[Data][10]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_3 "bRegPortOutLcl[Data][10]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_4 "bRegPortOutLcl[Data][10]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_1 "bRegPortOutLcl[Data][11]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_2 "bRegPortOutLcl[Data][11]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_3 "bRegPortOutLcl[Data][11]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_4 "bRegPortOutLcl[Data][11]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_1 "bRegPortOutLcl[Data][12]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_2 "bRegPortOutLcl[Data][12]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_3 "bRegPortOutLcl[Data][12]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_4 "bRegPortOutLcl[Data][12]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_1 "bRegPortOutLcl[Data][13]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFBAA")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_2 "bRegPortOutLcl[Data][13]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_3 "bRegPortOutLcl[Data][13]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_4 "bRegPortOutLcl[Data][13]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_1 "bRegPortOutLcl[Data][14]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_2 "bRegPortOutLcl[Data][14]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_3 "bRegPortOutLcl[Data][14]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_4 "bRegPortOutLcl[Data][14]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_1 "bRegPortOutLcl[Data][15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_2 "bRegPortOutLcl[Data][15]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_3 "bRegPortOutLcl[Data][15]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_4 "bRegPortOutLcl[Data][15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_1 "bRegPortOutLcl[Data][16]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEEE")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_2 "bRegPortOutLcl[Data][16]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_3 "bRegPortOutLcl[Data][16]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF002000200020")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_4 "bRegPortOutLcl[Data][16]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF080008000000000")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_5 "bRegPortOutLcl[Data][16]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_1 "bRegPortOutLcl[Data][17]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_2 "bRegPortOutLcl[Data][17]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_3 "bRegPortOutLcl[Data][17]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_4 "bRegPortOutLcl[Data][17]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_1 "bRegPortOutLcl[Data][18]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_2 "bRegPortOutLcl[Data][18]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_3 "bRegPortOutLcl[Data][18]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_4 "bRegPortOutLcl[Data][18]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_1 "bRegPortOutLcl[Data][19]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_2 "bRegPortOutLcl[Data][19]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_3 "bRegPortOutLcl[Data][19]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_4 "bRegPortOutLcl[Data][19]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_1 "bRegPortOutLcl[Data][1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_2 "bRegPortOutLcl[Data][1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF88F888F888F8")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_3 "bRegPortOutLcl[Data][1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_4 "bRegPortOutLcl[Data][1]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_5 "bRegPortOutLcl[Data][1]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_1 "bRegPortOutLcl[Data][20]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_2 "bRegPortOutLcl[Data][20]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_3 "bRegPortOutLcl[Data][20]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_4 "bRegPortOutLcl[Data][20]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_1 "bRegPortOutLcl[Data][21]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_2 "bRegPortOutLcl[Data][21]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_3 "bRegPortOutLcl[Data][21]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_4 "bRegPortOutLcl[Data][21]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_1 "bRegPortOutLcl[Data][22]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_2 "bRegPortOutLcl[Data][22]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_3 "bRegPortOutLcl[Data][22]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_4 "bRegPortOutLcl[Data][22]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_1 "bRegPortOutLcl[Data][23]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_2 "bRegPortOutLcl[Data][23]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_3 "bRegPortOutLcl[Data][23]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_4 "bRegPortOutLcl[Data][23]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_1 "bRegPortOutLcl[Data][24]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_2 "bRegPortOutLcl[Data][24]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_3 "bRegPortOutLcl[Data][24]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_4 "bRegPortOutLcl[Data][24]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_1 "bRegPortOutLcl[Data][25]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_2 "bRegPortOutLcl[Data][25]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_3 "bRegPortOutLcl[Data][25]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000100000000000")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_4 "bRegPortOutLcl[Data][25]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_5 "bRegPortOutLcl[Data][25]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_1 "bRegPortOutLcl[Data][26]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_2 "bRegPortOutLcl[Data][26]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_3 "bRegPortOutLcl[Data][26]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0020000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_4 "bRegPortOutLcl[Data][26]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_5 "bRegPortOutLcl[Data][26]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_1 "bRegPortOutLcl[Data][27]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_2 "bRegPortOutLcl[Data][27]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_3 "bRegPortOutLcl[Data][27]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000200000")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_4 "bRegPortOutLcl[Data][27]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000120000000000")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_5 "bRegPortOutLcl[Data][27]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_6 "bRegPortOutLcl[Data][27]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_7 "bRegPortOutLcl[Data][27]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0040000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_1 "bRegPortOutLcl[Data][28]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_10 "bRegPortOutLcl[Data][28]_i_10") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_2 "bRegPortOutLcl[Data][28]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_3 "bRegPortOutLcl[Data][28]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_4 "bRegPortOutLcl[Data][28]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0004000C00000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_5 "bRegPortOutLcl[Data][28]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0800000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_6 "bRegPortOutLcl[Data][28]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_7 "bRegPortOutLcl[Data][28]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0040")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_8 "bRegPortOutLcl[Data][28]_i_8") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000008000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_9 "bRegPortOutLcl[Data][28]_i_9") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_1 "bRegPortOutLcl[Data][29]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_2 "bRegPortOutLcl[Data][29]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_3 "bRegPortOutLcl[Data][29]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_4 "bRegPortOutLcl[Data][29]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_1 "bRegPortOutLcl[Data][2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_2 "bRegPortOutLcl[Data][2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_3 "bRegPortOutLcl[Data][2]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_4 "bRegPortOutLcl[Data][2]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF8")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_5 "bRegPortOutLcl[Data][2]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_1 "bRegPortOutLcl[Data][30]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_2 "bRegPortOutLcl[Data][30]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_3 "bRegPortOutLcl[Data][30]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_4 "bRegPortOutLcl[Data][30]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000002000000000")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_5 "bRegPortOutLcl[Data][30]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_6 "bRegPortOutLcl[Data][30]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000004000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_1 "bRegPortOutLcl[Data][31]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_10 "bRegPortOutLcl[Data][31]_i_10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000020000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_11 "bRegPortOutLcl[Data][31]_i_11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0800000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_12 "bRegPortOutLcl[Data][31]_i_12") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_2 "bRegPortOutLcl[Data][31]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_3 "bRegPortOutLcl[Data][31]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_4 "bRegPortOutLcl[Data][31]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_5 "bRegPortOutLcl[Data][31]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0010000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_6 "bRegPortOutLcl[Data][31]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000800000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_7 "bRegPortOutLcl[Data][31]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000200000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_8 "bRegPortOutLcl[Data][31]_i_8") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000200000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_9 "bRegPortOutLcl[Data][31]_i_9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000020000000000")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_1 "bRegPortOutLcl[Data][3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_2 "bRegPortOutLcl[Data][3]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_3 "bRegPortOutLcl[Data][3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_4 "bRegPortOutLcl[Data][3]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_5 "bRegPortOutLcl[Data][3]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_1 "bRegPortOutLcl[Data][4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_2 "bRegPortOutLcl[Data][4]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_3 "bRegPortOutLcl[Data][4]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_4 "bRegPortOutLcl[Data][4]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_5 "bRegPortOutLcl[Data][4]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0001000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_6 "bRegPortOutLcl[Data][4]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000000C00000E000")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_7 "bRegPortOutLcl[Data][4]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_1 "bRegPortOutLcl[Data][5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_2 "bRegPortOutLcl[Data][5]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF88F888F888F8")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_3 "bRegPortOutLcl[Data][5]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_4 "bRegPortOutLcl[Data][5]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_5 "bRegPortOutLcl[Data][5]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_1 "bRegPortOutLcl[Data][6]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_2 "bRegPortOutLcl[Data][6]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_3 "bRegPortOutLcl[Data][6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_4 "bRegPortOutLcl[Data][6]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF8")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_5 "bRegPortOutLcl[Data][6]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_1 "bRegPortOutLcl[Data][7]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_2 "bRegPortOutLcl[Data][7]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_3 "bRegPortOutLcl[Data][7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_4 "bRegPortOutLcl[Data][7]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_5 "bRegPortOutLcl[Data][7]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_6 "bRegPortOutLcl[Data][7]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000008000")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_1 "bRegPortOutLcl[Data][8]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_2 "bRegPortOutLcl[Data][8]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_3 "bRegPortOutLcl[Data][8]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_4 "bRegPortOutLcl[Data][8]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_5 "bRegPortOutLcl[Data][8]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_6 "bRegPortOutLcl[Data][8]_i_6") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h8000")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_1 "bRegPortOutLcl[Data][9]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_2 "bRegPortOutLcl[Data][9]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_3 "bRegPortOutLcl[Data][9]_i_3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF88F8")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_4 "bRegPortOutLcl[Data][9]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_5 "bRegPortOutLcl[Data][9]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_reg_Data__0_ "bRegPortOutLcl_reg[Data][0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__10_ "bRegPortOutLcl_reg[Data][10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__11_ "bRegPortOutLcl_reg[Data][11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__12_ "bRegPortOutLcl_reg[Data][12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__13_ "bRegPortOutLcl_reg[Data][13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__14_ "bRegPortOutLcl_reg[Data][14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__15_ "bRegPortOutLcl_reg[Data][15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__16_ "bRegPortOutLcl_reg[Data][16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__17_ "bRegPortOutLcl_reg[Data][17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__18_ "bRegPortOutLcl_reg[Data][18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__19_ "bRegPortOutLcl_reg[Data][19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__1_ "bRegPortOutLcl_reg[Data][1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__20_ "bRegPortOutLcl_reg[Data][20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__21_ "bRegPortOutLcl_reg[Data][21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__22_ "bRegPortOutLcl_reg[Data][22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__23_ "bRegPortOutLcl_reg[Data][23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__24_ "bRegPortOutLcl_reg[Data][24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__25_ "bRegPortOutLcl_reg[Data][25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__26_ "bRegPortOutLcl_reg[Data][26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__27_ "bRegPortOutLcl_reg[Data][27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__28_ "bRegPortOutLcl_reg[Data][28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__29_ "bRegPortOutLcl_reg[Data][29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__2_ "bRegPortOutLcl_reg[Data][2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__30_ "bRegPortOutLcl_reg[Data][30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__31_ "bRegPortOutLcl_reg[Data][31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__3_ "bRegPortOutLcl_reg[Data][3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__4_ "bRegPortOutLcl_reg[Data][4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__5_ "bRegPortOutLcl_reg[Data][5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__6_ "bRegPortOutLcl_reg[Data][6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__7_ "bRegPortOutLcl_reg[Data][7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__8_ "bRegPortOutLcl_reg[Data][8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__9_ "bRegPortOutLcl_reg[Data][9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bResetTdc_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFEFFFFFFFEEEEEE")) + ) + (instance bResetTdc_reg (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename bRpOffsetStored_0__i_1 "bRpOffsetStored[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename bRpOffsetStored_10__i_1 "bRpOffsetStored[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename bRpOffsetStored_11__i_1 "bRpOffsetStored[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename bRpOffsetStored_12__i_1 "bRpOffsetStored[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename bRpOffsetStored_13__i_1 "bRpOffsetStored[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename bRpOffsetStored_14__i_1 "bRpOffsetStored[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename bRpOffsetStored_15__i_1 "bRpOffsetStored[15]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bRpOffsetStored_16__i_1 "bRpOffsetStored[16]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bRpOffsetStored_17__i_1 "bRpOffsetStored[17]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bRpOffsetStored_18__i_1 "bRpOffsetStored[18]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bRpOffsetStored_19__i_1 "bRpOffsetStored[19]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bRpOffsetStored_1__i_1 "bRpOffsetStored[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename bRpOffsetStored_20__i_1 "bRpOffsetStored[20]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bRpOffsetStored_21__i_1 "bRpOffsetStored[21]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bRpOffsetStored_22__i_1 "bRpOffsetStored[22]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bRpOffsetStored_23__i_1 "bRpOffsetStored[23]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bRpOffsetStored_24__i_1 "bRpOffsetStored[24]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bRpOffsetStored_25__i_1 "bRpOffsetStored[25]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bRpOffsetStored_26__i_1 "bRpOffsetStored[26]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bRpOffsetStored_27__i_1 "bRpOffsetStored[27]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bRpOffsetStored_28__i_1 "bRpOffsetStored[28]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bRpOffsetStored_29__i_1 "bRpOffsetStored[29]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bRpOffsetStored_2__i_1 "bRpOffsetStored[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename bRpOffsetStored_30__i_1 "bRpOffsetStored[30]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bRpOffsetStored_31__i_1 "bRpOffsetStored[31]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bRpOffsetStored_32__i_1 "bRpOffsetStored[32]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bRpOffsetStored_33__i_1 "bRpOffsetStored[33]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bRpOffsetStored_34__i_1 "bRpOffsetStored[34]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bRpOffsetStored_35__i_1 "bRpOffsetStored[35]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bRpOffsetStored_36__i_1 "bRpOffsetStored[36]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bRpOffsetStored_37__i_1 "bRpOffsetStored[37]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bRpOffsetStored_38__i_1 "bRpOffsetStored[38]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bRpOffsetStored_39__i_1 "bRpOffsetStored[39]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF8000")) + ) + (instance (rename bRpOffsetStored_39__i_2 "bRpOffsetStored[39]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bRpOffsetStored_39__i_3 "bRpOffsetStored[39]_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename bRpOffsetStored_39__i_4 "bRpOffsetStored[39]_i_4") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00000004")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename bRpOffsetStored_3__i_1 "bRpOffsetStored[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename bRpOffsetStored_4__i_1 "bRpOffsetStored[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename bRpOffsetStored_5__i_1 "bRpOffsetStored[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename bRpOffsetStored_6__i_1 "bRpOffsetStored[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename bRpOffsetStored_7__i_1 "bRpOffsetStored[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename bRpOffsetStored_8__i_1 "bRpOffsetStored[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename bRpOffsetStored_9__i_1 "bRpOffsetStored[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename bRpOffsetStored_reg_0_ "bRpOffsetStored_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_10_ "bRpOffsetStored_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_11_ "bRpOffsetStored_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_12_ "bRpOffsetStored_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_13_ "bRpOffsetStored_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_14_ "bRpOffsetStored_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_15_ "bRpOffsetStored_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_16_ "bRpOffsetStored_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_17_ "bRpOffsetStored_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_18_ "bRpOffsetStored_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_19_ "bRpOffsetStored_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_1_ "bRpOffsetStored_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_20_ "bRpOffsetStored_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_21_ "bRpOffsetStored_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_22_ "bRpOffsetStored_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_23_ "bRpOffsetStored_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_24_ "bRpOffsetStored_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_25_ "bRpOffsetStored_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_26_ "bRpOffsetStored_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_27_ "bRpOffsetStored_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_28_ "bRpOffsetStored_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_29_ "bRpOffsetStored_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_2_ "bRpOffsetStored_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_30_ "bRpOffsetStored_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_31_ "bRpOffsetStored_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_32_ "bRpOffsetStored_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_33_ "bRpOffsetStored_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_34_ "bRpOffsetStored_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_35_ "bRpOffsetStored_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_36_ "bRpOffsetStored_reg[36]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_37_ "bRpOffsetStored_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_38_ "bRpOffsetStored_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_39_ "bRpOffsetStored_reg[39]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_3_ "bRpOffsetStored_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_4_ "bRpOffsetStored_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_5_ "bRpOffsetStored_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_6_ "bRpOffsetStored_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_7_ "bRpOffsetStored_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_8_ "bRpOffsetStored_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_9_ "bRpOffsetStored_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_0__i_1 "bScratch[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bScratch_10__i_1 "bScratch[10]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename bScratch_11__i_1 "bScratch[11]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename bScratch_12__i_1 "bScratch[12]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bScratch_13__i_1 "bScratch[13]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bScratch_14__i_1 "bScratch[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bScratch_15__i_1 "bScratch[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename bScratch_1__i_1 "bScratch[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename bScratch_20__i_1 "bScratch[20]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bScratch_21__i_1 "bScratch[21]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bScratch_22__i_1 "bScratch[22]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename bScratch_23__i_1 "bScratch[23]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bScratch_24__i_1 "bScratch[24]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bScratch_28__i_1 "bScratch[28]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename bScratch_29__i_1 "bScratch[29]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename bScratch_2__i_1 "bScratch[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename bScratch_30__i_1 "bScratch[30]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename bScratch_31__i_1 "bScratch[31]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFF00800000")) + ) + (instance (rename bScratch_31__i_2 "bScratch[31]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename bScratch_31__i_3 "bScratch[31]_i_3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h40")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance (rename bScratch_31__i_4 "bScratch[31]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename bScratch_31__i_5 "bScratch[31]_i_5") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance (rename bScratch_3__i_1 "bScratch[3]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bScratch_4__i_1 "bScratch[4]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename bScratch_5__i_1 "bScratch[5]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename bScratch_6__i_1 "bScratch[6]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename bScratch_7__i_1 "bScratch[7]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename bScratch_8__i_1 "bScratch[8]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename bScratch_9__i_1 "bScratch[9]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename bScratch_reg_0_ "bScratch_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_10_ "bScratch_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_11_ "bScratch_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_12_ "bScratch_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_13_ "bScratch_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_14_ "bScratch_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_15_ "bScratch_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_16_ "bScratch_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_17_ "bScratch_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_18_ "bScratch_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_19_ "bScratch_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_1_ "bScratch_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_20_ "bScratch_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_21_ "bScratch_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_22_ "bScratch_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_23_ "bScratch_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_24_ "bScratch_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_25_ "bScratch_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_26_ "bScratch_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_27_ "bScratch_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_28_ "bScratch_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_29_ "bScratch_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_2_ "bScratch_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_30_ "bScratch_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_31_ "bScratch_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_3_ "bScratch_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_4_ "bScratch_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_5_ "bScratch_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_6_ "bScratch_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_7_ "bScratch_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_8_ "bScratch_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_9_ "bScratch_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_0__i_1 "bSpOffsetStored[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename bSpOffsetStored_10__i_1 "bSpOffsetStored[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair60")) + ) + (instance (rename bSpOffsetStored_11__i_1 "bSpOffsetStored[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair59")) + ) + (instance (rename bSpOffsetStored_12__i_1 "bSpOffsetStored[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair59")) + ) + (instance (rename bSpOffsetStored_13__i_1 "bSpOffsetStored[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair58")) + ) + (instance (rename bSpOffsetStored_14__i_1 "bSpOffsetStored[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair58")) + ) + (instance (rename bSpOffsetStored_15__i_1 "bSpOffsetStored[15]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair57")) + ) + (instance (rename bSpOffsetStored_16__i_1 "bSpOffsetStored[16]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair57")) + ) + (instance (rename bSpOffsetStored_17__i_1 "bSpOffsetStored[17]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename bSpOffsetStored_18__i_1 "bSpOffsetStored[18]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename bSpOffsetStored_19__i_1 "bSpOffsetStored[19]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename bSpOffsetStored_1__i_1 "bSpOffsetStored[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair64")) + ) + (instance (rename bSpOffsetStored_20__i_1 "bSpOffsetStored[20]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename bSpOffsetStored_21__i_1 "bSpOffsetStored[21]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename bSpOffsetStored_22__i_1 "bSpOffsetStored[22]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename bSpOffsetStored_23__i_1 "bSpOffsetStored[23]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename bSpOffsetStored_24__i_1 "bSpOffsetStored[24]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename bSpOffsetStored_25__i_1 "bSpOffsetStored[25]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename bSpOffsetStored_26__i_1 "bSpOffsetStored[26]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename bSpOffsetStored_27__i_1 "bSpOffsetStored[27]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename bSpOffsetStored_28__i_1 "bSpOffsetStored[28]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename bSpOffsetStored_29__i_1 "bSpOffsetStored[29]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename bSpOffsetStored_2__i_1 "bSpOffsetStored[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair64")) + ) + (instance (rename bSpOffsetStored_30__i_1 "bSpOffsetStored[30]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename bSpOffsetStored_31__i_1 "bSpOffsetStored[31]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename bSpOffsetStored_3__i_1 "bSpOffsetStored[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair63")) + ) + (instance (rename bSpOffsetStored_4__i_1 "bSpOffsetStored[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair63")) + ) + (instance (rename bSpOffsetStored_5__i_1 "bSpOffsetStored[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair62")) + ) + (instance (rename bSpOffsetStored_6__i_1 "bSpOffsetStored[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair62")) + ) + (instance (rename bSpOffsetStored_7__i_1 "bSpOffsetStored[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair61")) + ) + (instance (rename bSpOffsetStored_8__i_1 "bSpOffsetStored[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair61")) + ) + (instance (rename bSpOffsetStored_9__i_1 "bSpOffsetStored[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair60")) + ) + (instance (rename bSpOffsetStored_reg_0_ "bSpOffsetStored_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_10_ "bSpOffsetStored_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_11_ "bSpOffsetStored_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_12_ "bSpOffsetStored_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_13_ "bSpOffsetStored_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_14_ "bSpOffsetStored_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_15_ "bSpOffsetStored_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_16_ "bSpOffsetStored_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_17_ "bSpOffsetStored_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_18_ "bSpOffsetStored_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_19_ "bSpOffsetStored_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_1_ "bSpOffsetStored_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_20_ "bSpOffsetStored_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_21_ "bSpOffsetStored_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_22_ "bSpOffsetStored_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_23_ "bSpOffsetStored_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_24_ "bSpOffsetStored_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_25_ "bSpOffsetStored_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_26_ "bSpOffsetStored_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_27_ "bSpOffsetStored_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_28_ "bSpOffsetStored_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_29_ "bSpOffsetStored_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_2_ "bSpOffsetStored_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_30_ "bSpOffsetStored_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_31_ "bSpOffsetStored_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_3_ "bSpOffsetStored_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_4_ "bSpOffsetStored_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_5_ "bSpOffsetStored_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_6_ "bSpOffsetStored_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_7_ "bSpOffsetStored_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_8_ "bSpOffsetStored_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_9_ "bSpOffsetStored_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_0_ "rPulserEnableDelayVal_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename rPulserEnableDelayVal_reg_1_ "rPulserEnableDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_2_ "rPulserEnableDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_3_ "rPulserEnableDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_0_ "sPpsClkCrossDelayVal_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_1_ "sPpsClkCrossDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_2_ "sPpsClkCrossDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_3_ "sPpsClkCrossDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "<const0>") (joined + (portref CLR (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref G (instanceref GND)) + (portref (member bRegPortOutFlat 32)) + (portref (member rRePulseHighTimeInRClks 0)) + (portref (member rRpHighTimeInRClks 0)) + (portref (member rRptHighTimeInRClks 0)) + (portref (member sSpHighTimeInSClks 0)) + (portref (member sSptHighTimeInSClks 0)) + ) + ) + (net (rename &_const1_ "<const1>") (joined + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref 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OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref 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OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CE (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref CE (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref CE (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + (portref CE (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref CE (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref CE (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref 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(instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref C (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref C 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RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref 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RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref 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RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref 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SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref 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(portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref 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bPpsClkCrossDelayVal_reg_2_)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref C (instanceref bPpsClkCrossEn_reg)) + (portref C (instanceref bPulserEnableDelayVal_reg_0_)) + (portref C (instanceref bPulserEnableDelayVal_reg_1_)) + (portref C (instanceref bPulserEnableDelayVal_reg_2_)) + (portref C (instanceref bPulserEnableDelayVal_reg_3_)) + (portref C (instanceref bPushPpsDelayVal_reg)) + (portref C (instanceref bPushPulserEnableDelayVal_reg)) + (portref C (instanceref bReRunEnable_reg)) + (portref C (instanceref bRegPortOutLcl_reg_Data__0_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__10_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__11_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__12_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__13_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__14_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__15_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__16_)) + (portref C (instanceref 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(portref C (instanceref bRegPortOutLcl_reg_Data__4_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__5_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__6_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__7_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__8_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__9_)) + (portref C (instanceref bResetTdc_reg)) + (portref C (instanceref bRpOffsetStored_reg_0_)) + (portref C (instanceref bRpOffsetStored_reg_10_)) + (portref C (instanceref bRpOffsetStored_reg_11_)) + (portref C (instanceref bRpOffsetStored_reg_12_)) + (portref C (instanceref bRpOffsetStored_reg_13_)) + (portref C (instanceref bRpOffsetStored_reg_14_)) + (portref C (instanceref bRpOffsetStored_reg_15_)) + (portref C (instanceref bRpOffsetStored_reg_16_)) + (portref C (instanceref bRpOffsetStored_reg_17_)) + (portref C (instanceref bRpOffsetStored_reg_18_)) + (portref C (instanceref bRpOffsetStored_reg_19_)) + (portref C (instanceref bRpOffsetStored_reg_1_)) + (portref C (instanceref bRpOffsetStored_reg_20_)) + (portref C (instanceref bRpOffsetStored_reg_21_)) + (portref C (instanceref bRpOffsetStored_reg_22_)) + (portref C (instanceref bRpOffsetStored_reg_23_)) + (portref C (instanceref bRpOffsetStored_reg_24_)) + (portref C (instanceref bRpOffsetStored_reg_25_)) + (portref C (instanceref bRpOffsetStored_reg_26_)) + (portref C (instanceref bRpOffsetStored_reg_27_)) + (portref C (instanceref bRpOffsetStored_reg_28_)) + (portref C (instanceref bRpOffsetStored_reg_29_)) + (portref C (instanceref bRpOffsetStored_reg_2_)) + (portref C (instanceref bRpOffsetStored_reg_30_)) + (portref C (instanceref bRpOffsetStored_reg_31_)) + (portref C (instanceref bRpOffsetStored_reg_32_)) + (portref C (instanceref bRpOffsetStored_reg_33_)) + (portref C (instanceref bRpOffsetStored_reg_34_)) + (portref C (instanceref bRpOffsetStored_reg_35_)) + (portref C (instanceref bRpOffsetStored_reg_36_)) + (portref C (instanceref bRpOffsetStored_reg_37_)) + (portref C (instanceref bRpOffsetStored_reg_38_)) + (portref C (instanceref bRpOffsetStored_reg_39_)) + (portref C (instanceref bRpOffsetStored_reg_3_)) + (portref C (instanceref bRpOffsetStored_reg_4_)) + (portref C (instanceref bRpOffsetStored_reg_5_)) + (portref C (instanceref bRpOffsetStored_reg_6_)) + (portref C (instanceref bRpOffsetStored_reg_7_)) + (portref C (instanceref bRpOffsetStored_reg_8_)) + (portref C (instanceref bRpOffsetStored_reg_9_)) + (portref C (instanceref bScratch_reg_0_)) + (portref C (instanceref bScratch_reg_10_)) + (portref C (instanceref bScratch_reg_11_)) + (portref C (instanceref bScratch_reg_12_)) + (portref C (instanceref bScratch_reg_13_)) + (portref C (instanceref bScratch_reg_14_)) + (portref C (instanceref bScratch_reg_15_)) + (portref C (instanceref bScratch_reg_16_)) + (portref C (instanceref bScratch_reg_17_)) + (portref C (instanceref bScratch_reg_18_)) + (portref C (instanceref bScratch_reg_19_)) + (portref C (instanceref bScratch_reg_1_)) + (portref C (instanceref bScratch_reg_20_)) + (portref C (instanceref bScratch_reg_21_)) + (portref C (instanceref bScratch_reg_22_)) + (portref C (instanceref bScratch_reg_23_)) + (portref C (instanceref bScratch_reg_24_)) + (portref C (instanceref bScratch_reg_25_)) + (portref C (instanceref bScratch_reg_26_)) + (portref C (instanceref bScratch_reg_27_)) + (portref C (instanceref bScratch_reg_28_)) + (portref C (instanceref bScratch_reg_29_)) + (portref C (instanceref bScratch_reg_2_)) + (portref C (instanceref bScratch_reg_30_)) + (portref C (instanceref bScratch_reg_31_)) + (portref C (instanceref bScratch_reg_3_)) + (portref C (instanceref bScratch_reg_4_)) + (portref C (instanceref bScratch_reg_5_)) + (portref C (instanceref bScratch_reg_6_)) + (portref C (instanceref bScratch_reg_7_)) + (portref C (instanceref bScratch_reg_8_)) + (portref C (instanceref bScratch_reg_9_)) + (portref C (instanceref bSpOffsetStored_reg_0_)) + (portref C (instanceref bSpOffsetStored_reg_10_)) + (portref C (instanceref bSpOffsetStored_reg_11_)) + (portref C (instanceref bSpOffsetStored_reg_12_)) + (portref C (instanceref bSpOffsetStored_reg_13_)) + (portref C (instanceref bSpOffsetStored_reg_14_)) + (portref C (instanceref bSpOffsetStored_reg_15_)) + (portref C (instanceref bSpOffsetStored_reg_16_)) + (portref C (instanceref bSpOffsetStored_reg_17_)) + (portref C (instanceref bSpOffsetStored_reg_18_)) + (portref C (instanceref bSpOffsetStored_reg_19_)) + (portref C (instanceref bSpOffsetStored_reg_1_)) + (portref C (instanceref bSpOffsetStored_reg_20_)) + (portref C (instanceref bSpOffsetStored_reg_21_)) + (portref C (instanceref bSpOffsetStored_reg_22_)) + (portref C (instanceref bSpOffsetStored_reg_23_)) + (portref C (instanceref bSpOffsetStored_reg_24_)) + (portref C (instanceref bSpOffsetStored_reg_25_)) + (portref C (instanceref bSpOffsetStored_reg_26_)) + (portref C (instanceref bSpOffsetStored_reg_27_)) + (portref C (instanceref bSpOffsetStored_reg_28_)) + (portref C (instanceref bSpOffsetStored_reg_29_)) + (portref C (instanceref bSpOffsetStored_reg_2_)) + (portref C (instanceref bSpOffsetStored_reg_30_)) + (portref C (instanceref bSpOffsetStored_reg_31_)) + (portref C (instanceref bSpOffsetStored_reg_3_)) + (portref C (instanceref bSpOffsetStored_reg_4_)) + (portref C (instanceref bSpOffsetStored_reg_5_)) + (portref C (instanceref bSpOffsetStored_reg_6_)) + (portref C (instanceref bSpOffsetStored_reg_7_)) + (portref C (instanceref bSpOffsetStored_reg_8_)) + (portref C (instanceref bSpOffsetStored_reg_9_)) + (portref BusClk) + ) + ) + (net (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename EnableTdcDs_DoubleSyncBasex_iDlySig "EnableTdcDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename Gen0_FDCEx_i_1__10_n_0 "Gen0.FDCEx_i_1__10_n_0") (joined + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__10)) + ) + ) + (net (rename Gen0_FDCEx_i_1__11_n_0 "Gen0.FDCEx_i_1__11_n_0") (joined + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__11)) + ) + ) + (net (rename Gen0_FDCEx_i_1__9_n_0 "Gen0.FDCEx_i_1__9_n_0") (joined + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__9)) + ) + ) + (net (rename Gen0_FDCEx_i_3__0_n_0 "Gen0.FDCEx_i_3__0_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1__1)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__2)) + (portref I3 (instanceref Gen0_FDCEx_i_1__1)) + (portref I3 (instanceref Gen0_FDCEx_i_1__2)) + (portref O (instanceref Gen0_FDCEx_i_3__0)) + ) + ) + (net (rename Gen0_FDCEx_i_3__1_n_0 "Gen0.FDCEx_i_3__1_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1__3)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__4)) + (portref I3 (instanceref Gen0_FDCEx_i_1__3)) + (portref I3 (instanceref Gen0_FDCEx_i_1__4)) + (portref O (instanceref Gen0_FDCEx_i_3__1)) + ) + ) + (net (rename Gen0_FDCEx_i_3_n_0 "Gen0.FDCEx_i_3_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__0)) + (portref I3 (instanceref Gen0_FDCEx_i_1)) + (portref I3 (instanceref Gen0_FDCEx_i_1__0)) + (portref O (instanceref Gen0_FDCEx_i_3)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__10_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__11_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__12_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__13_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__14_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__15_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__16_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__17_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__18_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__19_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__20_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[20]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__21_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[21]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__22_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[22]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__23_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[23]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__24_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[24]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__25_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[25]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__26_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[26]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__27_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[27]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__28_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[28]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__29_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[29]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__30_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[30]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__31_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[31]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__32_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[32]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__33_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[33]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__34_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[34]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__35_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[35]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__36_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[36]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__37_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[37]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__38_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[38]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__39_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[39]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__40_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[40]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__41_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[41]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__42_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[42]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__43_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[43]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__44_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[44]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__45_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[45]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__46_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[46]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__47_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[47]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__48_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[48]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__49_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[49]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__4_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[4]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__50_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[50]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__51_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[51]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__52_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[52]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__53_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[53]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__54_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[54]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__55_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[55]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__56_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[56]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__57_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[57]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__58_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[58]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__59_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[59]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__5_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[5]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__60_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[60]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__61_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[61]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__62_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[62]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__63_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[63]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__64_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[64]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__65_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[65]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__66_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[66]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__67_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[67]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__68_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[68]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__69_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[69]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__6_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[6]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__70_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[70]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__71_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[71]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__72_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[72]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__73_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[73]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__74_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[74]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__75_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[75]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__76_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[76]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__77_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[77]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__78_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[78]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__79_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[79]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__7_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[7]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__8_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[8]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__9_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[9]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg_n_0 "IncomingOffsetHs/HBx/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__7)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iDlyPush "IncomingOffsetHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__11)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iPushToggle "IncomingOffsetHs/HBx/iPushToggle") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__1)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iPushToggleNx "IncomingOffsetHs/HBx/iPushToggleNx") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__1)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggle0_ms "IncomingOffsetHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggle1 "IncomingOffsetHs/HBx/oPushToggle1") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__7)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggleChanged "IncomingOffsetHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__7)) + ) + ) + (net MeasClk (joined + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref C (instanceref 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OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[46].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[47].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[48].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[49].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[4].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[50].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[51].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[52].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[53].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[54].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[55].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[56].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[57].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[58].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[59].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[5].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[60].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[61].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[62].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[63].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[64].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[65].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[66].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[67].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[68].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_ms "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCapturedDs_DoubleSyncBasex_iDlySig "PpsCapturedDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCrossEnDs_DoubleSyncBasex_iDlySig "PpsCrossEnDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iDlyPush "PpsDelayValCrossingHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__9)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iPushToggle "PpsDelayValCrossingHs/HBx/iPushToggle") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iPushToggleNx "PpsDelayValCrossingHs/HBx/iPushToggleNx") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggle0_ms "PpsDelayValCrossingHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggle1 "PpsDelayValCrossingHs/HBx/oPushToggle1") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__5)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggleChanged "PpsDelayValCrossingHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__5)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg_n_0 "PulserEnableDelayValCrossingHs/HBx/BlkOut.oDataValid_reg_n_0") (joined + (portref CE (instanceref rPulserEnableDelayVal_reg_0_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_1_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_2_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_3_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg_n_0 "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__6)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iDlyPush "PulserEnableDelayValCrossingHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__10)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iPushToggle "PulserEnableDelayValCrossingHs/HBx/iPushToggle") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__0)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iPushToggleNx "PulserEnableDelayValCrossingHs/HBx/iPushToggleNx") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__0)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggle0_ms "PulserEnableDelayValCrossingHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggle1 "PulserEnableDelayValCrossingHs/HBx/oPushToggle1") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__6)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggleChanged "PulserEnableDelayValCrossingHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__6)) + ) + ) + (net (rename RePulse1CntHs_BlkIn_iDlyPush_reg_n_0 "RePulse1CntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__2)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RePulse1CntHs_BlkOut_oPushToggle2_reg_n_0 "RePulse1CntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__8)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RePulse1CntHs_iPushPulse "RePulse1CntHs/iPushPulse") (joined + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__2)) + ) + ) + (net (rename RePulse1CntHs_iPushToggle "RePulse1CntHs/iPushToggle") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__4)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_iPushToggleNx "RePulse1CntHs/iPushToggleNx") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__4)) + ) + ) + (net (rename RePulse1CntHs_oPushToggle0_ms "RePulse1CntHs/oPushToggle0_ms") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_oPushToggle1 "RePulse1CntHs/oPushToggle1") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__8)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_oPushToggleChanged "RePulse1CntHs/oPushToggleChanged") (joined + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__8)) + ) + ) + (net (rename RePulse2CntHs_BlkIn_iDlyPush_reg_n_0 "RePulse2CntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RePulse2CntHs_BlkOut_oPushToggle2_reg_n_0 "RePulse2CntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RePulse2CntHs_iPushPulse "RePulse2CntHs/iPushPulse") (joined + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__1)) + ) + ) + (net (rename RePulse2CntHs_iPushToggle "RePulse2CntHs/iPushToggle") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__5)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_iPushToggleNx "RePulse2CntHs/iPushToggleNx") (joined + (portref D (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__5)) + ) + ) + (net (rename RePulse2CntHs_oPushToggle0_ms "RePulse2CntHs/oPushToggle0_ms") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_oPushToggle1 "RePulse2CntHs/oPushToggle1") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_oPushToggleChanged "RePulse2CntHs/oPushToggleChanged") (joined + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__1)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ReRunEnableDs_DoubleSyncBasex_iDlySig "ReRunEnableDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net RefClk (joined + (portref C (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref C (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref C (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref rPulserEnableDelayVal_reg_0_)) + (portref C (instanceref rPulserEnableDelayVal_reg_1_)) + (portref C (instanceref rPulserEnableDelayVal_reg_2_)) + (portref C (instanceref rPulserEnableDelayVal_reg_3_)) + (portref RefClk) + ) + ) + (net RegWrite53_out (joined + (portref D (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1)) + ) + ) + (net RegWrite54_out (joined + (portref D (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__0)) + ) + ) + (net RegWrite55_out (joined + (portref D (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__1)) + ) + ) + (net RegWrite56_out (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__2)) + ) + ) + (net RegWrite57_out (joined + (portref D (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__3)) + ) + ) + (net RegWrite58_out (joined + (portref D (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__4)) + ) + ) + (net (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ResetDoneDs_DoubleSyncBasex_iDlySig "ResetDoneDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ResetTdcDs_DoubleSyncBasex_iDlySig "ResetTdcDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename RpCntHs_BlkOut_oPushToggle2_reg_n_0 "RpCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RpCntHs_iPushPulse "RpCntHs/iPushPulse") (joined + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__4)) + ) + ) + (net (rename RpCntHs_iPushToggle "RpCntHs/iPushToggle") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__2)) + (portref Q (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_iPushToggleNx "RpCntHs/iPushToggleNx") (joined + (portref D (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__2)) + ) + ) + (net (rename RpCntHs_oPushToggle0_ms "RpCntHs/oPushToggle0_ms") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_oPushToggle1 "RpCntHs/oPushToggle1") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_oPushToggleChanged "RpCntHs/oPushToggleChanged") (joined + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1)) + ) + ) + (net (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_BlkIn_iDlyPush_reg_n_0 "RptCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__0)) + (portref Q (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RptCntHs_BlkOut_oPushToggle2_reg_n_0 "RptCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__2)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RptCntHs_iPushPulse "RptCntHs/iPushPulse") (joined + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__0)) + ) + ) + (net (rename RptCntHs_iPushToggle "RptCntHs/iPushToggle") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__6)) + (portref Q (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_iPushToggleNx "RptCntHs/iPushToggleNx") (joined + (portref D (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__6)) + ) + ) + (net (rename RptCntHs_oPushToggle0_ms "RptCntHs/oPushToggle0_ms") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_oPushToggle1 "RptCntHs/oPushToggle1") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__2)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_oPushToggleChanged "RptCntHs/oPushToggleChanged") (joined + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__2)) + ) + ) + (net (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net SampleClk (joined + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_0_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_1_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref SampleClk) + ) + ) + (net (rename SpCntHs_BlkIn_iDlyPush_reg_n_0 "SpCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__3)) + (portref Q (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename SpCntHs_BlkOut_oPushToggle2_reg_n_0 "SpCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__0)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename SpCntHs_iPushPulse "SpCntHs/iPushPulse") (joined + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__3)) + ) + ) + (net (rename SpCntHs_iPushToggle "SpCntHs/iPushToggle") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__3)) + (portref Q (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_iPushToggleNx "SpCntHs/iPushToggleNx") (joined + (portref D (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__3)) + ) + ) + (net (rename SpCntHs_oPushToggle0_ms "SpCntHs/oPushToggle0_ms") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_oPushToggle1 "SpCntHs/oPushToggle1") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__0)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_oPushToggleChanged "SpCntHs/oPushToggleChanged") (joined + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__0)) + ) + ) + (net (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_BlkIn_iDlyPush_reg_n_0 "SptCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1)) + (portref Q (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename SptCntHs_BlkOut_oPushToggle2_reg_n_0 "SptCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__3)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename SptCntHs_iPushPulse "SptCntHs/iPushPulse") (joined + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1)) + ) + ) + (net (rename SptCntHs_iPushToggle "SptCntHs/iPushToggle") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__7)) + (portref Q (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_iPushToggleNx "SptCntHs/iPushToggleNx") (joined + (portref D (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__7)) + ) + ) + (net (rename SptCntHs_oPushToggle0_ms "SptCntHs/oPushToggle0_ms") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_oPushToggle1 "SptCntHs/oPushToggle1") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__3)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_oPushToggleChanged "SptCntHs/oPushToggleChanged") (joined + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__3)) + ) + ) + (net (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net aBusReset (joined + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref aTdcResetLcl_reg)) + (portref CLR (instanceref aTdcResetLcl_reg_rep)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__0)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__1)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__2)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__3)) + (portref CLR (instanceref bClearTdcRegs_reg)) + (portref CLR (instanceref bEnableTdc_reg)) + (portref CLR (instanceref bOffsetUpdated_reg)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref CLR (instanceref bPpsClkCrossEn_reg)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_1_)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_2_)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_3_)) + (portref CLR (instanceref bPushPpsDelayVal_reg)) + (portref CLR (instanceref bPushPulserEnableDelayVal_reg)) + (portref CLR (instanceref bReRunEnable_reg)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__0_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__10_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__11_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__12_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__13_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__14_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__15_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__16_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__17_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__18_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__19_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__1_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__20_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__21_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__22_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__23_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__24_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__25_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__26_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__27_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__28_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__30_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__31_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__3_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__4_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__5_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__6_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__7_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__8_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__9_)) + (portref CLR (instanceref bRpOffsetStored_reg_0_)) + (portref CLR (instanceref bRpOffsetStored_reg_10_)) + (portref CLR (instanceref bRpOffsetStored_reg_11_)) + (portref CLR (instanceref bRpOffsetStored_reg_12_)) + (portref CLR (instanceref bRpOffsetStored_reg_13_)) + (portref CLR (instanceref bRpOffsetStored_reg_14_)) + (portref CLR (instanceref bRpOffsetStored_reg_15_)) + (portref CLR (instanceref bRpOffsetStored_reg_16_)) + (portref CLR (instanceref bRpOffsetStored_reg_17_)) + (portref CLR (instanceref bRpOffsetStored_reg_18_)) + (portref CLR (instanceref bRpOffsetStored_reg_19_)) + (portref CLR (instanceref bRpOffsetStored_reg_1_)) + (portref CLR (instanceref bRpOffsetStored_reg_20_)) + (portref CLR (instanceref bRpOffsetStored_reg_21_)) + (portref CLR (instanceref bRpOffsetStored_reg_22_)) + (portref CLR (instanceref bRpOffsetStored_reg_23_)) + (portref CLR (instanceref bRpOffsetStored_reg_24_)) + (portref CLR (instanceref bRpOffsetStored_reg_25_)) + (portref CLR (instanceref bRpOffsetStored_reg_26_)) + (portref CLR (instanceref bRpOffsetStored_reg_27_)) + (portref CLR (instanceref bRpOffsetStored_reg_28_)) + (portref CLR (instanceref bRpOffsetStored_reg_29_)) + (portref CLR (instanceref bRpOffsetStored_reg_2_)) + (portref CLR (instanceref bRpOffsetStored_reg_30_)) + (portref CLR (instanceref bRpOffsetStored_reg_31_)) + (portref CLR (instanceref bRpOffsetStored_reg_32_)) + (portref CLR (instanceref bRpOffsetStored_reg_33_)) + (portref CLR (instanceref bRpOffsetStored_reg_34_)) + (portref CLR (instanceref bRpOffsetStored_reg_35_)) + (portref CLR (instanceref bRpOffsetStored_reg_36_)) + (portref CLR (instanceref bRpOffsetStored_reg_37_)) + (portref CLR (instanceref bRpOffsetStored_reg_38_)) + (portref CLR (instanceref bRpOffsetStored_reg_39_)) + (portref CLR (instanceref bRpOffsetStored_reg_3_)) + (portref CLR (instanceref bRpOffsetStored_reg_4_)) + (portref CLR (instanceref bRpOffsetStored_reg_5_)) + (portref CLR (instanceref bRpOffsetStored_reg_6_)) + (portref CLR (instanceref bRpOffsetStored_reg_7_)) + (portref CLR (instanceref bRpOffsetStored_reg_8_)) + (portref CLR (instanceref bRpOffsetStored_reg_9_)) + (portref CLR (instanceref bScratch_reg_0_)) + (portref CLR (instanceref bScratch_reg_10_)) + (portref CLR (instanceref bScratch_reg_11_)) + (portref CLR (instanceref bScratch_reg_12_)) + (portref CLR (instanceref bScratch_reg_13_)) + (portref CLR (instanceref bScratch_reg_14_)) + (portref CLR (instanceref bScratch_reg_15_)) + (portref CLR (instanceref bScratch_reg_16_)) + (portref CLR (instanceref bScratch_reg_17_)) + (portref CLR (instanceref bScratch_reg_18_)) + (portref CLR (instanceref bScratch_reg_19_)) + (portref CLR (instanceref bScratch_reg_1_)) + (portref CLR (instanceref bScratch_reg_20_)) + (portref CLR (instanceref bScratch_reg_21_)) + (portref CLR (instanceref bScratch_reg_22_)) + (portref CLR (instanceref bScratch_reg_23_)) + (portref CLR (instanceref bScratch_reg_24_)) + (portref CLR (instanceref bScratch_reg_25_)) + (portref CLR (instanceref bScratch_reg_26_)) + (portref CLR (instanceref bScratch_reg_27_)) + (portref CLR (instanceref bScratch_reg_28_)) + (portref CLR (instanceref bScratch_reg_29_)) + (portref CLR (instanceref bScratch_reg_2_)) + (portref CLR (instanceref bScratch_reg_30_)) + (portref CLR (instanceref bScratch_reg_31_)) + (portref CLR (instanceref bScratch_reg_3_)) + (portref CLR (instanceref bScratch_reg_4_)) + (portref CLR (instanceref bScratch_reg_5_)) + (portref CLR (instanceref bScratch_reg_6_)) + (portref CLR (instanceref bScratch_reg_7_)) + (portref CLR (instanceref bScratch_reg_8_)) + (portref CLR (instanceref bScratch_reg_9_)) + (portref CLR (instanceref bSpOffsetStored_reg_0_)) + (portref CLR (instanceref bSpOffsetStored_reg_10_)) + (portref CLR (instanceref bSpOffsetStored_reg_11_)) + (portref CLR (instanceref bSpOffsetStored_reg_12_)) + (portref CLR (instanceref bSpOffsetStored_reg_13_)) + (portref CLR (instanceref bSpOffsetStored_reg_14_)) + (portref CLR (instanceref bSpOffsetStored_reg_15_)) + (portref CLR (instanceref bSpOffsetStored_reg_16_)) + (portref CLR (instanceref bSpOffsetStored_reg_17_)) + (portref CLR (instanceref bSpOffsetStored_reg_18_)) + (portref CLR (instanceref bSpOffsetStored_reg_19_)) + (portref CLR (instanceref bSpOffsetStored_reg_1_)) + (portref CLR (instanceref bSpOffsetStored_reg_20_)) + (portref CLR (instanceref bSpOffsetStored_reg_21_)) + (portref CLR (instanceref bSpOffsetStored_reg_22_)) + (portref CLR (instanceref bSpOffsetStored_reg_23_)) + (portref CLR (instanceref bSpOffsetStored_reg_24_)) + (portref CLR (instanceref bSpOffsetStored_reg_25_)) + (portref CLR (instanceref bSpOffsetStored_reg_26_)) + (portref CLR (instanceref bSpOffsetStored_reg_27_)) + (portref CLR (instanceref bSpOffsetStored_reg_28_)) + (portref CLR (instanceref bSpOffsetStored_reg_29_)) + (portref CLR (instanceref bSpOffsetStored_reg_2_)) + (portref CLR (instanceref bSpOffsetStored_reg_30_)) + (portref CLR (instanceref bSpOffsetStored_reg_31_)) + (portref CLR (instanceref bSpOffsetStored_reg_3_)) + (portref CLR (instanceref bSpOffsetStored_reg_4_)) + (portref CLR (instanceref bSpOffsetStored_reg_5_)) + (portref CLR (instanceref bSpOffsetStored_reg_6_)) + (portref CLR (instanceref bSpOffsetStored_reg_7_)) + (portref CLR (instanceref bSpOffsetStored_reg_8_)) + (portref CLR (instanceref bSpOffsetStored_reg_9_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_1_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_2_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_3_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_0_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_1_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref PRE (instanceref bPulserEnableDelayVal_reg_0_)) + (portref PRE (instanceref bResetTdc_reg)) + (portref PRE (instanceref rPulserEnableDelayVal_reg_0_)) + (portref aBusReset) + ) + ) + (net aTdcReset (joined + (portref CLR (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I3 (instanceref aTdcResetLcl_i_1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref Q (instanceref aTdcResetLcl_reg)) + (portref aTdcReset) + ) + ) + (net aTdcResetLcl_i_1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg)) + (portref O (instanceref aTdcResetLcl_i_1)) + ) + ) + (net aTdcResetLcl_i_2_n_0 (joined + (portref I1 (instanceref aTdcResetLcl_i_1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref O (instanceref aTdcResetLcl_i_2)) + ) + ) + (net aTdcResetLcl_i_3_n_0 (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref I2 (instanceref aTdcResetLcl_i_1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_7)) + (portref I2 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_8)) + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I5 (instanceref bPushPpsDelayVal_i_1)) + (portref I5 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref O (instanceref aTdcResetLcl_i_3)) + ) + ) + (net aTdcResetLcl_i_4_n_0 (joined + (portref I1 (instanceref bRpOffsetStored_39__i_3)) + (portref I2 (instanceref aTdcResetLcl_i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref I2 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref O (instanceref aTdcResetLcl_i_4)) + ) + ) + (net aTdcResetLcl_i_5_n_0 (joined + (portref I0 (instanceref bRpOffsetStored_39__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref I3 (instanceref aTdcResetLcl_i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref O (instanceref aTdcResetLcl_i_5)) + ) + ) + (net aTdcResetLcl_reg_rep__0_n_0 (joined + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__0)) + ) + ) + (net aTdcResetLcl_reg_rep__1_n_0 (joined + (portref CLR (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__1)) + ) + ) + (net aTdcResetLcl_reg_rep__2_n_0 (joined + (portref CLR (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__2)) + ) + ) + (net aTdcResetLcl_reg_rep__3_n_0 (joined + (portref CLR (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__3)) + ) + ) + (net aTdcResetLcl_reg_rep_n_0 (joined + (portref CLR (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep)) + ) + ) + (net aTdcResetLcl_rep_i_1__0_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__0)) + (portref O (instanceref aTdcResetLcl_rep_i_1__0)) + ) + ) + (net aTdcResetLcl_rep_i_1__1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__1)) + (portref O (instanceref aTdcResetLcl_rep_i_1__1)) + ) + ) + (net aTdcResetLcl_rep_i_1__2_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__2)) + (portref O (instanceref aTdcResetLcl_rep_i_1__2)) + ) + ) + (net aTdcResetLcl_rep_i_1__3_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__3)) + (portref O (instanceref aTdcResetLcl_rep_i_1__3)) + ) + ) + (net aTdcResetLcl_rep_i_1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep)) + (portref O (instanceref aTdcResetLcl_rep_i_1)) + ) + ) + (net bBusReset (joined + (portref I0 (instanceref bOffsetUpdated_i_1)) + (portref I0 (instanceref bPulserEnableDelayVal_0__i_1)) + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref I1 (instanceref bEnableTdc_i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_0__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_1__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_2__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_3__i_2)) + (portref I1 (instanceref bPpsClkCrossEn_i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_1__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_2__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_3__i_2)) + (portref I1 (instanceref bReRunEnable_i_1)) + (portref I1 (instanceref bResetTdc_i_1)) + (portref I1 (instanceref bRpOffsetStored_0__i_1)) + (portref I1 (instanceref bRpOffsetStored_10__i_1)) + (portref I1 (instanceref bRpOffsetStored_11__i_1)) + (portref I1 (instanceref bRpOffsetStored_12__i_1)) + (portref I1 (instanceref bRpOffsetStored_13__i_1)) + (portref I1 (instanceref bRpOffsetStored_14__i_1)) + (portref I1 (instanceref bRpOffsetStored_15__i_1)) + (portref I1 (instanceref bRpOffsetStored_16__i_1)) + (portref I1 (instanceref bRpOffsetStored_17__i_1)) + (portref I1 (instanceref bRpOffsetStored_18__i_1)) + (portref I1 (instanceref bRpOffsetStored_19__i_1)) + (portref I1 (instanceref bRpOffsetStored_1__i_1)) + (portref I1 (instanceref bRpOffsetStored_20__i_1)) + (portref I1 (instanceref bRpOffsetStored_21__i_1)) + (portref I1 (instanceref bRpOffsetStored_22__i_1)) + (portref I1 (instanceref bRpOffsetStored_23__i_1)) + (portref I1 (instanceref bRpOffsetStored_24__i_1)) + (portref I1 (instanceref bRpOffsetStored_25__i_1)) + (portref I1 (instanceref bRpOffsetStored_26__i_1)) + (portref I1 (instanceref bRpOffsetStored_27__i_1)) + (portref I1 (instanceref bRpOffsetStored_28__i_1)) + (portref I1 (instanceref bRpOffsetStored_29__i_1)) + (portref I1 (instanceref bRpOffsetStored_2__i_1)) + (portref I1 (instanceref bRpOffsetStored_30__i_1)) + (portref I1 (instanceref bRpOffsetStored_31__i_1)) + (portref I1 (instanceref bRpOffsetStored_32__i_1)) + (portref I1 (instanceref bRpOffsetStored_33__i_1)) + (portref I1 (instanceref bRpOffsetStored_34__i_1)) + (portref I1 (instanceref bRpOffsetStored_35__i_1)) + (portref I1 (instanceref bRpOffsetStored_36__i_1)) + (portref I1 (instanceref bRpOffsetStored_37__i_1)) + (portref I1 (instanceref bRpOffsetStored_38__i_1)) + (portref I1 (instanceref bRpOffsetStored_39__i_2)) + (portref I1 (instanceref bRpOffsetStored_3__i_1)) + (portref I1 (instanceref bRpOffsetStored_4__i_1)) + (portref I1 (instanceref bRpOffsetStored_5__i_1)) + (portref I1 (instanceref bRpOffsetStored_6__i_1)) + (portref I1 (instanceref bRpOffsetStored_7__i_1)) + (portref I1 (instanceref bRpOffsetStored_8__i_1)) + (portref I1 (instanceref bRpOffsetStored_9__i_1)) + (portref I1 (instanceref bScratch_0__i_1)) + (portref I1 (instanceref bScratch_10__i_1)) + (portref I1 (instanceref bScratch_11__i_1)) + (portref I1 (instanceref bScratch_12__i_1)) + (portref I1 (instanceref bScratch_13__i_1)) + (portref I1 (instanceref bScratch_14__i_1)) + (portref I1 (instanceref bScratch_15__i_1)) + (portref I1 (instanceref bScratch_1__i_1)) + (portref I1 (instanceref bScratch_20__i_1)) + (portref I1 (instanceref bScratch_21__i_1)) + (portref I1 (instanceref bScratch_22__i_1)) + (portref I1 (instanceref bScratch_23__i_1)) + (portref I1 (instanceref bScratch_24__i_1)) + (portref I1 (instanceref bScratch_28__i_1)) + (portref I1 (instanceref bScratch_29__i_1)) + (portref I1 (instanceref bScratch_2__i_1)) + (portref I1 (instanceref bScratch_30__i_1)) + (portref I1 (instanceref bScratch_31__i_2)) + (portref I1 (instanceref bScratch_31__i_5)) + (portref I1 (instanceref bScratch_3__i_1)) + (portref I1 (instanceref bScratch_4__i_1)) + (portref I1 (instanceref bScratch_5__i_1)) + (portref I1 (instanceref bScratch_6__i_1)) + (portref I1 (instanceref bScratch_7__i_1)) + (portref I1 (instanceref bScratch_8__i_1)) + (portref I1 (instanceref bScratch_9__i_1)) + (portref I1 (instanceref bSpOffsetStored_0__i_1)) + (portref I1 (instanceref bSpOffsetStored_10__i_1)) + (portref I1 (instanceref bSpOffsetStored_11__i_1)) + (portref I1 (instanceref bSpOffsetStored_12__i_1)) + (portref I1 (instanceref bSpOffsetStored_13__i_1)) + (portref I1 (instanceref bSpOffsetStored_14__i_1)) + (portref I1 (instanceref bSpOffsetStored_15__i_1)) + (portref I1 (instanceref bSpOffsetStored_16__i_1)) + (portref I1 (instanceref bSpOffsetStored_17__i_1)) + (portref I1 (instanceref bSpOffsetStored_18__i_1)) + (portref I1 (instanceref bSpOffsetStored_19__i_1)) + (portref I1 (instanceref bSpOffsetStored_1__i_1)) + (portref I1 (instanceref bSpOffsetStored_20__i_1)) + (portref I1 (instanceref bSpOffsetStored_21__i_1)) + (portref I1 (instanceref bSpOffsetStored_22__i_1)) + (portref I1 (instanceref bSpOffsetStored_23__i_1)) + (portref I1 (instanceref bSpOffsetStored_24__i_1)) + (portref I1 (instanceref bSpOffsetStored_25__i_1)) + (portref I1 (instanceref bSpOffsetStored_26__i_1)) + (portref I1 (instanceref bSpOffsetStored_27__i_1)) + (portref I1 (instanceref bSpOffsetStored_28__i_1)) + (portref I1 (instanceref bSpOffsetStored_29__i_1)) + (portref I1 (instanceref bSpOffsetStored_2__i_1)) + (portref I1 (instanceref bSpOffsetStored_30__i_1)) + (portref I1 (instanceref bSpOffsetStored_31__i_1)) + (portref I1 (instanceref bSpOffsetStored_3__i_1)) + (portref I1 (instanceref bSpOffsetStored_4__i_1)) + (portref I1 (instanceref bSpOffsetStored_5__i_1)) + (portref I1 (instanceref bSpOffsetStored_6__i_1)) + (portref I1 (instanceref bSpOffsetStored_7__i_1)) + (portref I1 (instanceref bSpOffsetStored_8__i_1)) + (portref I1 (instanceref bSpOffsetStored_9__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I3 (instanceref bClearTdcRegs_i_1)) + (portref I4 (instanceref aTdcResetLcl_i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref I4 (instanceref bRpOffsetStored_39__i_1)) + (portref bBusReset) + ) + ) + (net bClearTdcRegs (joined + (portref D (instanceref bScratch_reg_0_)) + (portref O (instanceref bScratch_0__i_1)) + ) + ) + (net bClearTdcRegs_i_1_n_0 (joined + (portref D (instanceref bClearTdcRegs_reg)) + (portref O (instanceref bClearTdcRegs_i_1)) + ) + ) + (net bClearTdcRegs_i_2_n_0 (joined + (portref I2 (instanceref bClearTdcRegs_i_1)) + (portref O (instanceref bClearTdcRegs_i_2)) + ) + ) + (net bClearTdcRegs_i_3_n_0 (joined + (portref I0 (instanceref bClearTdcRegs_i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_9)) + (portref O (instanceref bClearTdcRegs_i_3)) + ) + ) + (net bClearTdcRegs_reg_n_0 (joined + (portref I0 (instanceref bEnableTdc_i_1)) + (portref I0 (instanceref bPpsClkCrossEn_i_1)) + (portref I0 (instanceref bReRunEnable_i_1)) + (portref I0 (instanceref bResetTdc_i_1)) + (portref I0 (instanceref bScratch_31__i_5)) + (portref I1 (instanceref bPulserEnableDelayVal_0__i_1)) + (portref I2 (instanceref aTdcResetLcl_i_2)) + (portref I2 (instanceref bPpsClkCrossDelayVal_0__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_1__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_2__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_3__i_2)) + (portref I2 (instanceref bPulserEnableDelayVal_1__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_2__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_3__i_2)) + (portref I2 (instanceref bScratch_0__i_1)) + (portref I2 (instanceref bScratch_10__i_1)) + (portref I2 (instanceref bScratch_11__i_1)) + (portref I2 (instanceref bScratch_12__i_1)) + (portref I2 (instanceref bScratch_13__i_1)) + (portref I2 (instanceref bScratch_14__i_1)) + (portref I2 (instanceref bScratch_15__i_1)) + (portref I2 (instanceref bScratch_1__i_1)) + (portref I2 (instanceref bScratch_20__i_1)) + (portref I2 (instanceref bScratch_21__i_1)) + (portref I2 (instanceref bScratch_22__i_1)) + (portref I2 (instanceref bScratch_23__i_1)) + (portref I2 (instanceref bScratch_24__i_1)) + (portref I2 (instanceref bScratch_28__i_1)) + (portref I2 (instanceref bScratch_29__i_1)) + (portref I2 (instanceref bScratch_2__i_1)) + (portref I2 (instanceref bScratch_30__i_1)) + (portref I2 (instanceref bScratch_31__i_2)) + (portref I2 (instanceref bScratch_3__i_1)) + (portref I2 (instanceref bScratch_4__i_1)) + (portref I2 (instanceref bScratch_5__i_1)) + (portref I2 (instanceref bScratch_6__i_1)) + (portref I2 (instanceref bScratch_7__i_1)) + (portref I2 (instanceref bScratch_8__i_1)) + (portref I2 (instanceref bScratch_9__i_1)) + (portref I3 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I3 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I3 (instanceref bPushPpsDelayVal_i_1)) + (portref I3 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I4 (instanceref bClearTdcRegs_i_1)) + (portref Q (instanceref bClearTdcRegs_reg)) + ) + ) + (net bEnableTdc (joined + (portref D (instanceref bScratch_reg_4_)) + (portref O (instanceref bScratch_4__i_1)) + ) + ) + (net bEnableTdc_i_1_n_0 (joined + (portref D (instanceref bEnableTdc_reg)) + (portref O (instanceref bEnableTdc_i_1)) + ) + ) + (net bEnableTdc_reg_n_0 (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref I5 (instanceref bEnableTdc_i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_5)) + (portref Q (instanceref bEnableTdc_reg)) + ) + ) + (net bOffsetUpdated_i_1_n_0 (joined + (portref D (instanceref bOffsetUpdated_reg)) + (portref O (instanceref bOffsetUpdated_i_1)) + ) + ) + (net bOffsetUpdated_reg_n_0 (joined + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref I4 (instanceref bOffsetUpdated_i_1)) + (portref Q (instanceref bOffsetUpdated_reg)) + ) + ) + (net bOffsetsValid (joined + (portref D (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + ) + ) + (net bOffsetsValidSyncReset (joined + (portref I3 (instanceref bOffsetUpdated_i_1)) + (portref Q (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_0_ "bOffsets[0]") (joined + (portref D (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_10_ "bOffsets[10]") (joined + (portref D (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_11_ "bOffsets[11]") (joined + (portref D (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_12_ "bOffsets[12]") (joined + (portref D (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_13_ "bOffsets[13]") (joined + (portref D (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_14_ "bOffsets[14]") (joined + (portref D (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_15_ "bOffsets[15]") (joined + (portref D (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_16_ "bOffsets[16]") (joined + (portref D (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_17_ "bOffsets[17]") (joined + (portref D (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_18_ "bOffsets[18]") (joined + (portref D (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_19_ "bOffsets[19]") (joined + (portref D (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_1_ "bOffsets[1]") (joined + (portref D (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_20_ "bOffsets[20]") (joined + (portref D (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_21_ "bOffsets[21]") (joined + (portref D (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_22_ "bOffsets[22]") (joined + (portref D (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_23_ "bOffsets[23]") (joined + (portref D (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_24_ "bOffsets[24]") (joined + (portref D (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_25_ "bOffsets[25]") (joined + (portref D (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_26_ "bOffsets[26]") (joined + (portref D (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_27_ "bOffsets[27]") (joined + (portref D (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_28_ "bOffsets[28]") (joined + (portref D (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_29_ "bOffsets[29]") (joined + (portref D (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_2_ "bOffsets[2]") (joined + (portref D (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_30_ "bOffsets[30]") (joined + (portref D (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_31_ "bOffsets[31]") (joined + (portref D (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_32_ "bOffsets[32]") (joined + (portref D (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_33_ "bOffsets[33]") (joined + (portref D (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_34_ "bOffsets[34]") (joined + (portref D (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_35_ "bOffsets[35]") (joined + (portref D (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_36_ "bOffsets[36]") (joined + (portref D (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_37_ "bOffsets[37]") (joined + (portref D (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_38_ "bOffsets[38]") (joined + (portref D (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_39_ "bOffsets[39]") (joined + (portref D (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_3_ "bOffsets[3]") (joined + (portref D (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_40_ "bOffsets[40]") (joined + (portref D (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_41_ "bOffsets[41]") (joined + (portref D (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_42_ "bOffsets[42]") (joined + (portref D (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_43_ "bOffsets[43]") (joined + (portref D (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_44_ "bOffsets[44]") (joined + (portref D (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_45_ "bOffsets[45]") (joined + (portref D (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_46_ "bOffsets[46]") (joined + (portref D (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_47_ "bOffsets[47]") (joined + (portref D (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_48_ "bOffsets[48]") (joined + (portref D (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_49_ "bOffsets[49]") (joined + (portref D (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_4_ "bOffsets[4]") (joined + (portref D (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_50_ "bOffsets[50]") (joined + (portref D (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_51_ "bOffsets[51]") (joined + (portref D (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_52_ "bOffsets[52]") (joined + (portref D (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_53_ "bOffsets[53]") (joined + (portref D (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_54_ "bOffsets[54]") (joined + (portref D (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_55_ "bOffsets[55]") (joined + (portref D (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_56_ "bOffsets[56]") (joined + (portref D (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_57_ "bOffsets[57]") (joined + (portref D (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_58_ "bOffsets[58]") (joined + (portref D (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_59_ "bOffsets[59]") (joined + (portref D (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_5_ "bOffsets[5]") (joined + (portref D (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_60_ "bOffsets[60]") (joined + (portref D (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_61_ "bOffsets[61]") (joined + (portref D (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_62_ "bOffsets[62]") (joined + (portref D (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_63_ "bOffsets[63]") (joined + (portref D (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_64_ "bOffsets[64]") (joined + (portref D (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_65_ "bOffsets[65]") (joined + (portref D (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_66_ "bOffsets[66]") (joined + (portref D (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_67_ "bOffsets[67]") (joined + (portref D (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_68_ "bOffsets[68]") (joined + (portref D (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_69_ "bOffsets[69]") (joined + (portref D (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_6_ "bOffsets[6]") (joined + (portref D (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_70_ "bOffsets[70]") (joined + (portref D (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_71_ "bOffsets[71]") (joined + (portref D (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_72_ "bOffsets[72]") (joined + (portref D (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_73_ "bOffsets[73]") (joined + (portref D (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_74_ "bOffsets[74]") (joined + (portref D (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_75_ "bOffsets[75]") (joined + (portref D (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_76_ "bOffsets[76]") (joined + (portref D (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_77_ "bOffsets[77]") (joined + (portref D (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_78_ "bOffsets[78]") (joined + (portref D (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_79_ "bOffsets[79]") (joined + (portref D (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_7_ "bOffsets[7]") (joined + (portref D (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_8_ "bOffsets[8]") (joined + (portref D (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_9_ "bOffsets[9]") (joined + (portref D (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bPpsClkCrossDelayVal_1__i_1_n_0 "bPpsClkCrossDelayVal[1]_i_1_n_0") (joined + (portref D (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref D (instanceref bScratch_reg_17_)) + (portref O (instanceref bPpsClkCrossDelayVal_1__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_2__i_1_n_0 "bPpsClkCrossDelayVal[2]_i_1_n_0") (joined + (portref D (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref D (instanceref bScratch_reg_18_)) + (portref O (instanceref bPpsClkCrossDelayVal_2__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_3__i_1_n_0 "bPpsClkCrossDelayVal[3]_i_1_n_0") (joined + (portref CE (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref O (instanceref bPpsClkCrossDelayVal_3__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_3__i_3_n_0 "bPpsClkCrossDelayVal[3]_i_3_n_0") (joined + (portref I1 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I4 (instanceref bEnableTdc_i_1)) + (portref I4 (instanceref bPpsClkCrossEn_i_1)) + (portref I4 (instanceref bReRunEnable_i_1)) + (portref I4 (instanceref bResetTdc_i_1)) + (portref O (instanceref bPpsClkCrossDelayVal_3__i_3)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__0_ "bPpsClkCrossDelayVal_reg_n_0_[0]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_1)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_0_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__1_ "bPpsClkCrossDelayVal_reg_n_0_[1]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_1_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__2_ "bPpsClkCrossDelayVal_reg_n_0_[2]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_2_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__3_ "bPpsClkCrossDelayVal_reg_n_0_[3]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_1)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_3_)) + ) + ) + (net bPpsClkCrossEn (joined + (portref D (instanceref bScratch_reg_12_)) + (portref O (instanceref bScratch_12__i_1)) + ) + ) + (net bPpsClkCrossEn_i_1_n_0 (joined + (portref D (instanceref bPpsClkCrossEn_reg)) + (portref O (instanceref bPpsClkCrossEn_i_1)) + ) + ) + (net bPpsClkCrossEn_reg_n_0 (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_1)) + (portref I5 (instanceref bPpsClkCrossEn_i_1)) + (portref Q (instanceref bPpsClkCrossEn_reg)) + ) + ) + (net bPpsPulseCaptured (joined + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_6)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bPulserEnableDelayVal_0__i_1_n_0 "bPulserEnableDelayVal[0]_i_1_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_0_)) + (portref O (instanceref bPulserEnableDelayVal_0__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_2__i_1_n_0 "bPulserEnableDelayVal[2]_i_1_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_2_)) + (portref D (instanceref bScratch_reg_26_)) + (portref O (instanceref bPulserEnableDelayVal_2__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_3__i_1_n_0 "bPulserEnableDelayVal[3]_i_1_n_0") (joined + (portref CE (instanceref bPulserEnableDelayVal_reg_0_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_1_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_2_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_3_)) + (portref O (instanceref bPulserEnableDelayVal_3__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_3__i_2_n_0 "bPulserEnableDelayVal[3]_i_2_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_3_)) + (portref D (instanceref bScratch_reg_27_)) + (portref O (instanceref bPulserEnableDelayVal_3__i_2)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__0_ "bPulserEnableDelayVal_reg_n_0_[0]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_1)) + (portref Q (instanceref bPulserEnableDelayVal_reg_0_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__1_ "bPulserEnableDelayVal_reg_n_0_[1]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_1)) + (portref Q (instanceref bPulserEnableDelayVal_reg_1_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__2_ "bPulserEnableDelayVal_reg_n_0_[2]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref Q (instanceref bPulserEnableDelayVal_reg_2_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__3_ "bPulserEnableDelayVal_reg_n_0_[3]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref Q (instanceref bPulserEnableDelayVal_reg_3_)) + ) + ) + (net bPushPpsDelayVal (joined + (portref D (instanceref bPushPpsDelayVal_reg)) + (portref O (instanceref bPushPpsDelayVal_i_1)) + ) + ) + (net bPushPpsDelayVal_i_2_n_0 (joined + (portref I0 (instanceref bPushPpsDelayVal_i_1)) + (portref I0 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I5 (instanceref aTdcResetLcl_i_2)) + (portref O (instanceref bPushPpsDelayVal_i_2)) + ) + ) + (net bPushPpsDelayVal_i_3_n_0 (joined + (portref I1 (instanceref bPushPpsDelayVal_i_1)) + (portref I1 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref O (instanceref bPushPpsDelayVal_i_3)) + ) + ) + (net bPushPpsDelayVal_i_4_n_0 (joined + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_4)) + (portref I4 (instanceref bPushPpsDelayVal_i_1)) + (portref I4 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref O (instanceref bPushPpsDelayVal_i_4)) + ) + ) + (net bPushPpsDelayVal_reg_n_0 (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__9)) + (portref Q (instanceref bPushPpsDelayVal_reg)) + ) + ) + (net bPushPulserEnableDelayVal (joined + (portref D (instanceref bPushPulserEnableDelayVal_reg)) + (portref O (instanceref bPushPulserEnableDelayVal_i_1)) + ) + ) + (net bPushPulserEnableDelayVal_reg_n_0 (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__10)) + (portref Q (instanceref bPushPulserEnableDelayVal_reg)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_0_ "bRePulsePeriod1CtrlReadbackSyncReset[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_10_ "bRePulsePeriod1CtrlReadbackSyncReset[10]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_11_ "bRePulsePeriod1CtrlReadbackSyncReset[11]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_12_ "bRePulsePeriod1CtrlReadbackSyncReset[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_13_ "bRePulsePeriod1CtrlReadbackSyncReset[13]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_14_ "bRePulsePeriod1CtrlReadbackSyncReset[14]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_15_ "bRePulsePeriod1CtrlReadbackSyncReset[15]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_16_ "bRePulsePeriod1CtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_17_ "bRePulsePeriod1CtrlReadbackSyncReset[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_18_ "bRePulsePeriod1CtrlReadbackSyncReset[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_19_ "bRePulsePeriod1CtrlReadbackSyncReset[19]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_1_ "bRePulsePeriod1CtrlReadbackSyncReset[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_20_ "bRePulsePeriod1CtrlReadbackSyncReset[20]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_21_ "bRePulsePeriod1CtrlReadbackSyncReset[21]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_22_ "bRePulsePeriod1CtrlReadbackSyncReset[22]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_23_ "bRePulsePeriod1CtrlReadbackSyncReset[23]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_24_ "bRePulsePeriod1CtrlReadbackSyncReset[24]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_25_ "bRePulsePeriod1CtrlReadbackSyncReset[25]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_26_ "bRePulsePeriod1CtrlReadbackSyncReset[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_27_ "bRePulsePeriod1CtrlReadbackSyncReset[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_28_ "bRePulsePeriod1CtrlReadbackSyncReset[28]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_29_ "bRePulsePeriod1CtrlReadbackSyncReset[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_2_ "bRePulsePeriod1CtrlReadbackSyncReset[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_30_ "bRePulsePeriod1CtrlReadbackSyncReset[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_31_ "bRePulsePeriod1CtrlReadbackSyncReset[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_3_ "bRePulsePeriod1CtrlReadbackSyncReset[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_4_ "bRePulsePeriod1CtrlReadbackSyncReset[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_5_ "bRePulsePeriod1CtrlReadbackSyncReset[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_6_ "bRePulsePeriod1CtrlReadbackSyncReset[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_7_ "bRePulsePeriod1CtrlReadbackSyncReset[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_8_ "bRePulsePeriod1CtrlReadbackSyncReset[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_9_ "bRePulsePeriod1CtrlReadbackSyncReset[9]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_0_ "bRePulsePeriod1CtrlReadback[0]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_10_ "bRePulsePeriod1CtrlReadback[10]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_11_ "bRePulsePeriod1CtrlReadback[11]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_12_ "bRePulsePeriod1CtrlReadback[12]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_13_ "bRePulsePeriod1CtrlReadback[13]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_14_ "bRePulsePeriod1CtrlReadback[14]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_15_ "bRePulsePeriod1CtrlReadback[15]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_16_ "bRePulsePeriod1CtrlReadback[16]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_17_ "bRePulsePeriod1CtrlReadback[17]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_18_ "bRePulsePeriod1CtrlReadback[18]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_19_ "bRePulsePeriod1CtrlReadback[19]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_1_ "bRePulsePeriod1CtrlReadback[1]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_20_ "bRePulsePeriod1CtrlReadback[20]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_21_ "bRePulsePeriod1CtrlReadback[21]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_22_ "bRePulsePeriod1CtrlReadback[22]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_23_ "bRePulsePeriod1CtrlReadback[23]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_24_ "bRePulsePeriod1CtrlReadback[24]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_25_ "bRePulsePeriod1CtrlReadback[25]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_26_ "bRePulsePeriod1CtrlReadback[26]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_27_ "bRePulsePeriod1CtrlReadback[27]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_28_ "bRePulsePeriod1CtrlReadback[28]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_29_ "bRePulsePeriod1CtrlReadback[29]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_2_ "bRePulsePeriod1CtrlReadback[2]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_30_ "bRePulsePeriod1CtrlReadback[30]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_31_ "bRePulsePeriod1CtrlReadback[31]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_3_ "bRePulsePeriod1CtrlReadback[3]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_4_ "bRePulsePeriod1CtrlReadback[4]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_5_ "bRePulsePeriod1CtrlReadback[5]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_6_ "bRePulsePeriod1CtrlReadback[6]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_7_ "bRePulsePeriod1CtrlReadback[7]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_8_ "bRePulsePeriod1CtrlReadback[8]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_9_ "bRePulsePeriod1CtrlReadback[9]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_0_ "bRePulsePeriod2CtrlReadbackSyncReset[0]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_10_ "bRePulsePeriod2CtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_1)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_11_ "bRePulsePeriod2CtrlReadbackSyncReset[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_12_ "bRePulsePeriod2CtrlReadbackSyncReset[12]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_13_ "bRePulsePeriod2CtrlReadbackSyncReset[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_14_ "bRePulsePeriod2CtrlReadbackSyncReset[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_15_ "bRePulsePeriod2CtrlReadbackSyncReset[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_16_ "bRePulsePeriod2CtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_17_ "bRePulsePeriod2CtrlReadbackSyncReset[17]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_18_ "bRePulsePeriod2CtrlReadbackSyncReset[18]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_19_ "bRePulsePeriod2CtrlReadbackSyncReset[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_1_ "bRePulsePeriod2CtrlReadbackSyncReset[1]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_20_ "bRePulsePeriod2CtrlReadbackSyncReset[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_21_ "bRePulsePeriod2CtrlReadbackSyncReset[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_22_ "bRePulsePeriod2CtrlReadbackSyncReset[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_23_ "bRePulsePeriod2CtrlReadbackSyncReset[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_24_ "bRePulsePeriod2CtrlReadbackSyncReset[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_25_ "bRePulsePeriod2CtrlReadbackSyncReset[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_26_ "bRePulsePeriod2CtrlReadbackSyncReset[26]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_27_ "bRePulsePeriod2CtrlReadbackSyncReset[27]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_28_ "bRePulsePeriod2CtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_1)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_29_ "bRePulsePeriod2CtrlReadbackSyncReset[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_2_ "bRePulsePeriod2CtrlReadbackSyncReset[2]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_30_ "bRePulsePeriod2CtrlReadbackSyncReset[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_31_ "bRePulsePeriod2CtrlReadbackSyncReset[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_3_ "bRePulsePeriod2CtrlReadbackSyncReset[3]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_4_ "bRePulsePeriod2CtrlReadbackSyncReset[4]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_7)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_5_ "bRePulsePeriod2CtrlReadbackSyncReset[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_6_ "bRePulsePeriod2CtrlReadbackSyncReset[6]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__6__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_7_ "bRePulsePeriod2CtrlReadbackSyncReset[7]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_8_ "bRePulsePeriod2CtrlReadbackSyncReset[8]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_9_ "bRePulsePeriod2CtrlReadbackSyncReset[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_0_ "bRePulsePeriod2CtrlReadback[0]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_10_ "bRePulsePeriod2CtrlReadback[10]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_11_ "bRePulsePeriod2CtrlReadback[11]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_12_ "bRePulsePeriod2CtrlReadback[12]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_13_ "bRePulsePeriod2CtrlReadback[13]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_14_ "bRePulsePeriod2CtrlReadback[14]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_15_ "bRePulsePeriod2CtrlReadback[15]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_16_ "bRePulsePeriod2CtrlReadback[16]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_17_ "bRePulsePeriod2CtrlReadback[17]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_18_ "bRePulsePeriod2CtrlReadback[18]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_19_ "bRePulsePeriod2CtrlReadback[19]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_1_ "bRePulsePeriod2CtrlReadback[1]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_20_ "bRePulsePeriod2CtrlReadback[20]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_21_ "bRePulsePeriod2CtrlReadback[21]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_22_ "bRePulsePeriod2CtrlReadback[22]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_23_ "bRePulsePeriod2CtrlReadback[23]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_24_ "bRePulsePeriod2CtrlReadback[24]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_25_ "bRePulsePeriod2CtrlReadback[25]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_26_ "bRePulsePeriod2CtrlReadback[26]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_27_ "bRePulsePeriod2CtrlReadback[27]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_28_ "bRePulsePeriod2CtrlReadback[28]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_29_ "bRePulsePeriod2CtrlReadback[29]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_2_ "bRePulsePeriod2CtrlReadback[2]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_30_ "bRePulsePeriod2CtrlReadback[30]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_31_ "bRePulsePeriod2CtrlReadback[31]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_3_ "bRePulsePeriod2CtrlReadback[3]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_4_ "bRePulsePeriod2CtrlReadback[4]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_5_ "bRePulsePeriod2CtrlReadback[5]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_6_ "bRePulsePeriod2CtrlReadback[6]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_7_ "bRePulsePeriod2CtrlReadback[7]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_8_ "bRePulsePeriod2CtrlReadback[8]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_9_ "bRePulsePeriod2CtrlReadback[9]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net bReRunEnable (joined + (portref D (instanceref bScratch_reg_8_)) + (portref O (instanceref bScratch_8__i_1)) + ) + ) + (net bReRunEnable_i_1_n_0 (joined + (portref D (instanceref bReRunEnable_reg)) + (portref O (instanceref bReRunEnable_i_1)) + ) + ) + (net bReRunEnable_reg_n_0 (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref I5 (instanceref bReRunEnable_i_1)) + (portref Q (instanceref bReRunEnable_reg)) + ) + ) + (net (rename bRegPortInFlat_0_ "bRegPortInFlat[0]") (joined + (portref I0 (instanceref bPushPpsDelayVal_i_3)) + (portref I1 (instanceref bClearTdcRegs_i_2)) + (portref I1 (instanceref bScratch_31__i_3)) + (portref I4 (instanceref aTdcResetLcl_i_2)) + (portref (member bRegPortInFlat 49)) + ) + ) + (net (rename bRegPortInFlat_10_ "bRegPortInFlat[10]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref I0 (instanceref bScratch_8__i_1)) + (portref I3 (instanceref bReRunEnable_i_1)) + (portref (member bRegPortInFlat 39)) + ) + ) + (net (rename bRegPortInFlat_11_ "bRegPortInFlat[11]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref I0 (instanceref bScratch_9__i_1)) + (portref I2 (instanceref bReRunEnable_i_1)) + (portref (member bRegPortInFlat 38)) + ) + ) + (net (rename bRegPortInFlat_12_ "bRegPortInFlat[12]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref I0 (instanceref bScratch_10__i_1)) + (portref (member bRegPortInFlat 37)) + ) + ) + (net (rename bRegPortInFlat_13_ "bRegPortInFlat[13]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref I0 (instanceref bScratch_11__i_1)) + (portref (member bRegPortInFlat 36)) + ) + ) + (net (rename bRegPortInFlat_14_ "bRegPortInFlat[14]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref I0 (instanceref bScratch_12__i_1)) + (portref I3 (instanceref bPpsClkCrossEn_i_1)) + (portref (member bRegPortInFlat 35)) + ) + ) + (net (rename bRegPortInFlat_15_ "bRegPortInFlat[15]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref I0 (instanceref bScratch_13__i_1)) + (portref I2 (instanceref bPpsClkCrossEn_i_1)) + (portref (member bRegPortInFlat 34)) + ) + ) + (net (rename bRegPortInFlat_16_ "bRegPortInFlat[16]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref I0 (instanceref bScratch_14__i_1)) + (portref (member bRegPortInFlat 33)) + ) + ) + (net (rename bRegPortInFlat_17_ "bRegPortInFlat[17]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref I0 (instanceref bScratch_15__i_1)) + (portref (member bRegPortInFlat 32)) + ) + ) + (net (rename bRegPortInFlat_18_ "bRegPortInFlat[18]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref I0 (instanceref bPpsClkCrossDelayVal_0__i_1)) + (portref (member bRegPortInFlat 31)) + ) + ) + (net (rename bRegPortInFlat_19_ "bRegPortInFlat[19]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref I0 (instanceref bPpsClkCrossDelayVal_1__i_1)) + (portref (member bRegPortInFlat 30)) + ) + ) + (net (rename bRegPortInFlat_1_ "bRegPortInFlat[1]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I1 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_7)) + (portref I2 (instanceref bRpOffsetStored_39__i_1)) + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_7)) + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_8)) + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I5 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref (member bRegPortInFlat 48)) + ) + ) + (net (rename bRegPortInFlat_20_ "bRegPortInFlat[20]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref I0 (instanceref bPpsClkCrossDelayVal_2__i_1)) + (portref (member bRegPortInFlat 29)) + ) + ) + (net (rename bRegPortInFlat_21_ "bRegPortInFlat[21]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref I0 (instanceref bPpsClkCrossDelayVal_3__i_2)) + (portref (member bRegPortInFlat 28)) + ) + ) + (net (rename bRegPortInFlat_22_ "bRegPortInFlat[22]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref I0 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I0 (instanceref bScratch_20__i_1)) + (portref I2 (instanceref bPushPpsDelayVal_i_1)) + (portref (member bRegPortInFlat 27)) + ) + ) + (net (rename bRegPortInFlat_23_ "bRegPortInFlat[23]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref I0 (instanceref bScratch_21__i_1)) + (portref (member bRegPortInFlat 26)) + ) + ) + (net (rename bRegPortInFlat_24_ "bRegPortInFlat[24]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref I0 (instanceref bScratch_22__i_1)) + (portref (member bRegPortInFlat 25)) + ) + ) + (net (rename bRegPortInFlat_25_ "bRegPortInFlat[25]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref I0 (instanceref bScratch_23__i_1)) + (portref (member bRegPortInFlat 24)) + ) + ) + (net (rename bRegPortInFlat_26_ "bRegPortInFlat[26]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref I0 (instanceref bScratch_24__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_0__i_1)) + (portref (member bRegPortInFlat 23)) + ) + ) + (net (rename bRegPortInFlat_27_ "bRegPortInFlat[27]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref I0 (instanceref bPulserEnableDelayVal_1__i_1)) + (portref (member bRegPortInFlat 22)) + ) + ) + (net (rename bRegPortInFlat_28_ "bRegPortInFlat[28]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref I0 (instanceref bPulserEnableDelayVal_2__i_1)) + (portref (member bRegPortInFlat 21)) + ) + ) + (net (rename bRegPortInFlat_29_ "bRegPortInFlat[29]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref I0 (instanceref bPulserEnableDelayVal_3__i_2)) + (portref (member bRegPortInFlat 20)) + ) + ) + (net (rename bRegPortInFlat_2_ "bRegPortInFlat[2]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref I0 (instanceref bClearTdcRegs_i_1)) + (portref I0 (instanceref bScratch_0__i_1)) + (portref I3 (instanceref bResetTdc_i_1)) + (portref (member bRegPortInFlat 47)) + ) + ) + (net (rename bRegPortInFlat_30_ "bRegPortInFlat[30]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref I0 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I0 (instanceref bScratch_28__i_1)) + (portref I2 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref (member bRegPortInFlat 19)) + ) + ) + (net (rename bRegPortInFlat_31_ "bRegPortInFlat[31]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref I0 (instanceref bScratch_29__i_1)) + (portref (member bRegPortInFlat 18)) + ) + ) + (net (rename bRegPortInFlat_32_ "bRegPortInFlat[32]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref I0 (instanceref bScratch_30__i_1)) + (portref (member bRegPortInFlat 17)) + ) + ) + (net (rename bRegPortInFlat_33_ "bRegPortInFlat[33]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref I0 (instanceref bScratch_31__i_2)) + (portref (member bRegPortInFlat 16)) + ) + ) + (net (rename bRegPortInFlat_34_ "bRegPortInFlat[34]") (joined + (portref I0 (instanceref aTdcResetLcl_i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_10)) + (portref I3 (instanceref bRpOffsetStored_39__i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref (member bRegPortInFlat 15)) + ) + ) + (net (rename bRegPortInFlat_35_ "bRegPortInFlat[35]") (joined + (portref I1 (instanceref aTdcResetLcl_i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_10)) + (portref I2 (instanceref bRpOffsetStored_39__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref (member bRegPortInFlat 14)) + ) + ) + (net (rename bRegPortInFlat_36_ "bRegPortInFlat[36]") (joined + (portref I0 (instanceref bPushPpsDelayVal_i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__27__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_12)) + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_5)) + (portref I0 (instanceref bScratch_31__i_4)) + (portref I1 (instanceref BlkIn_iDlyPush_i_1__0)) + (portref I1 (instanceref BlkIn_iDlyPush_i_1__4)) + (portref I1 (instanceref Gen0_FDCEx_i_1)) + (portref I1 (instanceref Gen0_FDCEx_i_1__1)) + (portref I1 (instanceref Gen0_FDCEx_i_1__2)) + (portref I1 (instanceref Gen0_FDCEx_i_1__3)) + (portref I1 (instanceref aTdcResetLcl_i_2)) + (portref I1 (instanceref bClearTdcRegs_i_3)) + (portref I2 (instanceref BlkIn_iDlyPush_i_1)) + (portref I2 (instanceref BlkIn_iDlyPush_i_1__1)) + (portref I2 (instanceref BlkIn_iDlyPush_i_1__2)) + (portref I2 (instanceref BlkIn_iDlyPush_i_1__3)) + (portref I2 (instanceref Gen0_FDCEx_i_1__0)) + (portref I2 (instanceref Gen0_FDCEx_i_1__4)) + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_4)) + (portref I4 (instanceref bRpOffsetStored_39__i_4)) + (portref I5 (instanceref bPpsClkCrossDelayVal_3__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__0__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_6)) + (portref I5 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref (member bRegPortInFlat 13)) + ) + ) + (net (rename bRegPortInFlat_37_ "bRegPortInFlat[37]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_7)) + (portref I0 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_9)) + (portref I1 (instanceref Gen0_FDCEx_i_3)) + (portref I1 (instanceref bPpsClkCrossDelayVal_3__i_3)) + (portref I1 (instanceref bPushPpsDelayVal_i_2)) + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_4)) + (portref I1 (instanceref bRpOffsetStored_39__i_4)) + (portref I2 (instanceref Gen0_FDCEx_i_3__0)) + (portref I2 (instanceref Gen0_FDCEx_i_3__1)) + (portref I2 (instanceref bRegPortOutLcl_Data__27__i_4)) + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_5)) + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_6)) + (portref I4 (instanceref bClearTdcRegs_i_2)) + (portref I4 (instanceref bRegPortOutLcl_Data__26__i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_4)) + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_5)) + (portref I4 (instanceref bScratch_31__i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_10)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_9)) + (portref (member bRegPortInFlat 12)) + ) + ) + (net (rename bRegPortInFlat_38_ "bRegPortInFlat[38]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_7)) + (portref I0 (instanceref bScratch_31__i_3)) + (portref I1 (instanceref bPushPpsDelayVal_i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_8)) + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I1 (instanceref bRpOffsetStored_39__i_1)) + (portref I2 (instanceref bClearTdcRegs_i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref I3 (instanceref aTdcResetLcl_i_2)) + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_4)) + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_5)) + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_10)) + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_9)) + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref (member bRegPortInFlat 11)) + ) + ) + (net (rename bRegPortInFlat_39_ "bRegPortInFlat[39]") (joined + (portref I0 (instanceref aTdcResetLcl_i_2)) + (portref I0 (instanceref bClearTdcRegs_i_3)) + (portref I1 (instanceref BlkIn_iDlyPush_i_1)) + (portref I1 (instanceref BlkIn_iDlyPush_i_1__1)) + (portref I1 (instanceref BlkIn_iDlyPush_i_1__2)) + (portref I1 (instanceref BlkIn_iDlyPush_i_1__3)) + (portref I1 (instanceref Gen0_FDCEx_i_1__0)) + (portref I1 (instanceref Gen0_FDCEx_i_1__4)) + (portref I1 (instanceref bPushPpsDelayVal_i_4)) + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_4)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_12)) + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_5)) + (portref I1 (instanceref bScratch_31__i_4)) + (portref I2 (instanceref BlkIn_iDlyPush_i_1__0)) + (portref I2 (instanceref BlkIn_iDlyPush_i_1__4)) + (portref I2 (instanceref Gen0_FDCEx_i_1)) + (portref I2 (instanceref Gen0_FDCEx_i_1__1)) + (portref I2 (instanceref Gen0_FDCEx_i_1__2)) + (portref I2 (instanceref Gen0_FDCEx_i_1__3)) + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__16__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_4)) + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_4)) + (portref I3 (instanceref bRpOffsetStored_39__i_4)) + (portref I4 (instanceref bPpsClkCrossDelayVal_3__i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_5)) + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_6)) + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_3)) + (portref (member bRegPortInFlat 10)) + ) + ) + (net (rename bRegPortInFlat_3_ "bRegPortInFlat[3]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref I0 (instanceref bScratch_1__i_1)) + (portref I2 (instanceref bResetTdc_i_1)) + (portref (member bRegPortInFlat 46)) + ) + ) + (net (rename bRegPortInFlat_40_ "bRegPortInFlat[40]") (joined + (portref I1 (instanceref Gen0_FDCEx_i_3__0)) + (portref I1 (instanceref Gen0_FDCEx_i_3__1)) + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_4)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_5)) + (portref I2 (instanceref Gen0_FDCEx_i_3)) + (portref I2 (instanceref bPpsClkCrossDelayVal_3__i_3)) + (portref I2 (instanceref bPushPpsDelayVal_i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_10)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_9)) + (portref I2 (instanceref bRpOffsetStored_39__i_4)) + (portref I3 (instanceref bClearTdcRegs_i_2)) + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_7)) + (portref I3 (instanceref bScratch_31__i_1)) + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_7)) + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_4)) + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_8)) + (portref (member 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"bRegPortOutLcl[Data][29]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_2_n_0 "bRegPortOutLcl[Data][29]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_3_n_0 "bRegPortOutLcl[Data][29]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_4_n_0 "bRegPortOutLcl[Data][29]_i_4_n_0") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_1_n_0 "bRegPortOutLcl[Data][2]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_2_n_0 "bRegPortOutLcl[Data][2]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_3_n_0 "bRegPortOutLcl[Data][2]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_4_n_0 "bRegPortOutLcl[Data][2]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_5_n_0 "bRegPortOutLcl[Data][2]_i_5_n_0") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_5)) + ) + ) + (net (rename bRegPortOutLcl_Data__30__i_1_n_0 "bRegPortOutLcl[Data][30]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__30_)) + (portref O (instanceref bRegPortOutLcl_Data__30__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__30__i_2_n_0 "bRegPortOutLcl[Data][30]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__30__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__30__i_3_n_0 "bRegPortOutLcl[Data][30]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__30__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__30__i_4_n_0 "bRegPortOutLcl[Data][30]_i_4_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__11__i_1)) + (portref I2 (instanceref bRegPortOutLcl_Data__14__i_1)) + (portref I2 (instanceref bRegPortOutLcl_Data__1__i_1)) + (portref I2 (instanceref bRegPortOutLcl_Data__20__i_1)) + (portref I2 (instanceref bRegPortOutLcl_Data__21__i_1)) + (portref I2 (instanceref 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(instanceref bRegPortOutLcl_Data__30__i_6)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_10_n_0 "bRegPortOutLcl[Data][31]_i_10_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref I2 (instanceref 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bRegPortOutLcl_Data__31__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_10)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_11_n_0 "bRegPortOutLcl[Data][31]_i_11_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref I0 (instanceref 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bRegPortOutLcl_Data__8__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_11)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_12_n_0 "bRegPortOutLcl[Data][31]_i_12_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_10)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_8)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_12)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_1_n_0 "bRegPortOutLcl[Data][31]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__31_)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_2_n_0 "bRegPortOutLcl[Data][31]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_3_n_0 "bRegPortOutLcl[Data][31]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_4_n_0 "bRegPortOutLcl[Data][31]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_5_n_0 "bRegPortOutLcl[Data][31]_i_5_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref I0 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(joined + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_5_n_0 "bRegPortOutLcl[Data][3]_i_5_n_0") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_5)) + ) + ) + (net (rename bRegPortOutLcl_Data__4__i_1_n_0 "bRegPortOutLcl[Data][4]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__4_)) + (portref O (instanceref bRegPortOutLcl_Data__4__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__4__i_2_n_0 "bRegPortOutLcl[Data][4]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__4__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__4__i_3_n_0 "bRegPortOutLcl[Data][4]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__4__i_3)) + ) + ) + (net (rename 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) + ) + (net (rename bRegPortOutLcl_Data__7__i_6_n_0 "bRegPortOutLcl[Data][7]_i_6_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__7__i_6)) + ) + ) + (net (rename bRegPortOutLcl_Data__8__i_1_n_0 "bRegPortOutLcl[Data][8]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__8_)) + (portref O (instanceref bRegPortOutLcl_Data__8__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__8__i_2_n_0 "bRegPortOutLcl[Data][8]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_1)) + (portref O (instanceref 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(instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I3 (instanceref bRpOffsetStored_39__i_1)) + (portref O (instanceref bRpOffsetStored_39__i_4)) + ) + ) + (net (rename bRpOffsetStored_3_ "bRpOffsetStored[3]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_3_)) + ) + ) + (net (rename bRpOffsetStored_3__i_1_n_0 "bRpOffsetStored[3]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_3_)) + (portref O (instanceref bRpOffsetStored_3__i_1)) + ) + ) + (net (rename bRpOffsetStored_4_ "bRpOffsetStored[4]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_4_)) + ) + ) + (net (rename bRpOffsetStored_4__i_1_n_0 "bRpOffsetStored[4]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_4_)) + (portref O (instanceref bRpOffsetStored_4__i_1)) + ) + ) + (net (rename bRpOffsetStored_5_ "bRpOffsetStored[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_5_)) + ) + ) + (net (rename bRpOffsetStored_5__i_1_n_0 "bRpOffsetStored[5]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_5_)) + (portref O (instanceref bRpOffsetStored_5__i_1)) + ) + ) + (net (rename bRpOffsetStored_6_ "bRpOffsetStored[6]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_6_)) + ) + ) + (net (rename bRpOffsetStored_6__i_1_n_0 "bRpOffsetStored[6]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_6_)) + (portref O (instanceref bRpOffsetStored_6__i_1)) + ) + ) + (net (rename bRpOffsetStored_7_ "bRpOffsetStored[7]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_7_)) + ) + ) + (net (rename bRpOffsetStored_7__i_1_n_0 "bRpOffsetStored[7]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_7_)) + (portref O (instanceref bRpOffsetStored_7__i_1)) + ) + ) + (net (rename bRpOffsetStored_8_ "bRpOffsetStored[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_8_)) + ) + ) + (net (rename bRpOffsetStored_8__i_1_n_0 "bRpOffsetStored[8]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_8_)) + (portref O (instanceref bRpOffsetStored_8__i_1)) + ) + ) + (net (rename bRpOffsetStored_9_ "bRpOffsetStored[9]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_9_)) + ) + ) + (net (rename bRpOffsetStored_9__i_1_n_0 "bRpOffsetStored[9]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_9_)) + (portref O (instanceref bRpOffsetStored_9__i_1)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_0_ "bRpPeriodCtrlReadbackSyncReset[0]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_10_ "bRpPeriodCtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_11_ "bRpPeriodCtrlReadbackSyncReset[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_12_ "bRpPeriodCtrlReadbackSyncReset[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_13_ "bRpPeriodCtrlReadbackSyncReset[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_14_ "bRpPeriodCtrlReadbackSyncReset[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_15_ "bRpPeriodCtrlReadbackSyncReset[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_16_ "bRpPeriodCtrlReadbackSyncReset[16]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_17_ "bRpPeriodCtrlReadbackSyncReset[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_18_ "bRpPeriodCtrlReadbackSyncReset[18]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_19_ "bRpPeriodCtrlReadbackSyncReset[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_1_ "bRpPeriodCtrlReadbackSyncReset[1]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_20_ "bRpPeriodCtrlReadbackSyncReset[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_21_ "bRpPeriodCtrlReadbackSyncReset[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_22_ "bRpPeriodCtrlReadbackSyncReset[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_23_ "bRpPeriodCtrlReadbackSyncReset[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_24_ "bRpPeriodCtrlReadbackSyncReset[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_25_ "bRpPeriodCtrlReadbackSyncReset[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_26_ "bRpPeriodCtrlReadbackSyncReset[26]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_27_ "bRpPeriodCtrlReadbackSyncReset[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_28_ "bRpPeriodCtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_29_ "bRpPeriodCtrlReadbackSyncReset[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_2_ "bRpPeriodCtrlReadbackSyncReset[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_30_ "bRpPeriodCtrlReadbackSyncReset[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_31_ "bRpPeriodCtrlReadbackSyncReset[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_3_ "bRpPeriodCtrlReadbackSyncReset[3]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_4_ "bRpPeriodCtrlReadbackSyncReset[4]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_5_ "bRpPeriodCtrlReadbackSyncReset[5]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_6_ "bRpPeriodCtrlReadbackSyncReset[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_7_ "bRpPeriodCtrlReadbackSyncReset[7]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_8_ "bRpPeriodCtrlReadbackSyncReset[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_9_ "bRpPeriodCtrlReadbackSyncReset[9]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadback_0_ "bRpPeriodCtrlReadback[0]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_10_ "bRpPeriodCtrlReadback[10]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_11_ "bRpPeriodCtrlReadback[11]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_12_ "bRpPeriodCtrlReadback[12]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_13_ "bRpPeriodCtrlReadback[13]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_14_ "bRpPeriodCtrlReadback[14]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_15_ "bRpPeriodCtrlReadback[15]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_16_ "bRpPeriodCtrlReadback[16]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_17_ "bRpPeriodCtrlReadback[17]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_18_ "bRpPeriodCtrlReadback[18]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_19_ "bRpPeriodCtrlReadback[19]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_1_ "bRpPeriodCtrlReadback[1]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_20_ "bRpPeriodCtrlReadback[20]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_21_ "bRpPeriodCtrlReadback[21]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_22_ "bRpPeriodCtrlReadback[22]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_23_ "bRpPeriodCtrlReadback[23]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_24_ "bRpPeriodCtrlReadback[24]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_25_ "bRpPeriodCtrlReadback[25]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_26_ "bRpPeriodCtrlReadback[26]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_27_ "bRpPeriodCtrlReadback[27]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_28_ "bRpPeriodCtrlReadback[28]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_29_ "bRpPeriodCtrlReadback[29]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_2_ "bRpPeriodCtrlReadback[2]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_30_ "bRpPeriodCtrlReadback[30]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_31_ "bRpPeriodCtrlReadback[31]") (joined + (portref D (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_3_ "bRpPeriodCtrlReadback[3]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_4_ "bRpPeriodCtrlReadback[4]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_5_ "bRpPeriodCtrlReadback[5]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_6_ "bRpPeriodCtrlReadback[6]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_7_ "bRpPeriodCtrlReadback[7]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_8_ "bRpPeriodCtrlReadback[8]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_9_ "bRpPeriodCtrlReadback[9]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_0_ "bRptPeriodCtrlReadbackSyncReset[0]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_10_ "bRptPeriodCtrlReadbackSyncReset[10]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_11_ "bRptPeriodCtrlReadbackSyncReset[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_12_ "bRptPeriodCtrlReadbackSyncReset[12]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_13_ "bRptPeriodCtrlReadbackSyncReset[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_14_ "bRptPeriodCtrlReadbackSyncReset[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_15_ "bRptPeriodCtrlReadbackSyncReset[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_16_ "bRptPeriodCtrlReadbackSyncReset[16]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_17_ "bRptPeriodCtrlReadbackSyncReset[17]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_18_ "bRptPeriodCtrlReadbackSyncReset[18]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_19_ "bRptPeriodCtrlReadbackSyncReset[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_1_ "bRptPeriodCtrlReadbackSyncReset[1]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_20_ "bRptPeriodCtrlReadbackSyncReset[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_21_ "bRptPeriodCtrlReadbackSyncReset[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_22_ "bRptPeriodCtrlReadbackSyncReset[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_23_ "bRptPeriodCtrlReadbackSyncReset[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_24_ "bRptPeriodCtrlReadbackSyncReset[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_25_ "bRptPeriodCtrlReadbackSyncReset[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_26_ "bRptPeriodCtrlReadbackSyncReset[26]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_27_ "bRptPeriodCtrlReadbackSyncReset[27]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_28_ "bRptPeriodCtrlReadbackSyncReset[28]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_29_ "bRptPeriodCtrlReadbackSyncReset[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_2_ "bRptPeriodCtrlReadbackSyncReset[2]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_30_ "bRptPeriodCtrlReadbackSyncReset[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_31_ "bRptPeriodCtrlReadbackSyncReset[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_3_ "bRptPeriodCtrlReadbackSyncReset[3]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_4_ "bRptPeriodCtrlReadbackSyncReset[4]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_5_ "bRptPeriodCtrlReadbackSyncReset[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_6_ "bRptPeriodCtrlReadbackSyncReset[6]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_7_ "bRptPeriodCtrlReadbackSyncReset[7]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_8_ "bRptPeriodCtrlReadbackSyncReset[8]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_9_ "bRptPeriodCtrlReadbackSyncReset[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadback_0_ "bRptPeriodCtrlReadback[0]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_10_ "bRptPeriodCtrlReadback[10]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_11_ "bRptPeriodCtrlReadback[11]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_12_ "bRptPeriodCtrlReadback[12]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_13_ "bRptPeriodCtrlReadback[13]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_14_ "bRptPeriodCtrlReadback[14]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_15_ "bRptPeriodCtrlReadback[15]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_16_ "bRptPeriodCtrlReadback[16]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_17_ "bRptPeriodCtrlReadback[17]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_18_ "bRptPeriodCtrlReadback[18]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_19_ "bRptPeriodCtrlReadback[19]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_1_ "bRptPeriodCtrlReadback[1]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_20_ "bRptPeriodCtrlReadback[20]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_21_ "bRptPeriodCtrlReadback[21]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_22_ "bRptPeriodCtrlReadback[22]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_23_ "bRptPeriodCtrlReadback[23]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_24_ "bRptPeriodCtrlReadback[24]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_25_ "bRptPeriodCtrlReadback[25]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_26_ "bRptPeriodCtrlReadback[26]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_27_ "bRptPeriodCtrlReadback[27]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_28_ "bRptPeriodCtrlReadback[28]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_29_ "bRptPeriodCtrlReadback[29]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_2_ "bRptPeriodCtrlReadback[2]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_30_ "bRptPeriodCtrlReadback[30]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_31_ "bRptPeriodCtrlReadback[31]") (joined + (portref D (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_3_ "bRptPeriodCtrlReadback[3]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_4_ "bRptPeriodCtrlReadback[4]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_5_ "bRptPeriodCtrlReadback[5]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_6_ "bRptPeriodCtrlReadback[6]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_7_ "bRptPeriodCtrlReadback[7]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_8_ "bRptPeriodCtrlReadback[8]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_9_ "bRptPeriodCtrlReadback[9]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bScratch_0_ "bScratch[0]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_6)) + (portref Q (instanceref bScratch_reg_0_)) + ) + ) + (net (rename bScratch_10_ "bScratch[10]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__10__i_3)) + (portref Q (instanceref bScratch_reg_10_)) + ) + ) + (net (rename bScratch_11_ "bScratch[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref bScratch_reg_11_)) + ) + ) + (net (rename bScratch_12_ "bScratch[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_1)) + (portref Q (instanceref bScratch_reg_12_)) + ) + ) + (net (rename bScratch_13_ "bScratch[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref bScratch_reg_13_)) + ) + ) + (net (rename bScratch_14_ "bScratch[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref bScratch_reg_14_)) + ) + ) + (net (rename bScratch_15_ "bScratch[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref bScratch_reg_15_)) + ) + ) + (net (rename bScratch_16_ "bScratch[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_4)) + (portref Q (instanceref bScratch_reg_16_)) + ) + ) + (net (rename bScratch_17_ "bScratch[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_1)) + (portref Q (instanceref bScratch_reg_17_)) + ) + ) + (net (rename bScratch_18_ "bScratch[18]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__18__i_1)) + (portref Q (instanceref bScratch_reg_18_)) + ) + ) + (net (rename bScratch_19_ "bScratch[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref bScratch_reg_19_)) + ) + ) + (net (rename bScratch_1_ "bScratch[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref Q (instanceref bScratch_reg_1_)) + ) + ) + (net (rename bScratch_20_ "bScratch[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref bScratch_reg_20_)) + ) + ) + (net (rename bScratch_21_ "bScratch[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref bScratch_reg_21_)) + ) + ) + (net (rename bScratch_22_ "bScratch[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref bScratch_reg_22_)) + ) + ) + (net (rename bScratch_23_ "bScratch[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref bScratch_reg_23_)) + ) + ) + (net (rename bScratch_24_ "bScratch[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref bScratch_reg_24_)) + ) + ) + (net (rename bScratch_25_ "bScratch[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref bScratch_reg_25_)) + ) + ) + (net (rename bScratch_26_ "bScratch[26]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__26__i_1)) + (portref Q (instanceref bScratch_reg_26_)) + ) + ) + (net (rename bScratch_27_ "bScratch[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_1)) + (portref Q (instanceref bScratch_reg_27_)) + ) + ) + (net (rename bScratch_28_ "bScratch[28]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_3)) + (portref Q (instanceref bScratch_reg_28_)) + ) + ) + (net (rename bScratch_29_ "bScratch[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref bScratch_reg_29_)) + ) + ) + (net (rename bScratch_2_ "bScratch[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref Q (instanceref bScratch_reg_2_)) + ) + ) + (net (rename bScratch_30_ "bScratch[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref bScratch_reg_30_)) + ) + ) + (net (rename bScratch_31_ "bScratch[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref bScratch_reg_31_)) + ) + ) + (net (rename bScratch_31__i_1_n_0 "bScratch[31]_i_1_n_0") (joined + (portref CE (instanceref bScratch_reg_0_)) + (portref CE (instanceref bScratch_reg_10_)) + (portref CE (instanceref bScratch_reg_11_)) + (portref CE (instanceref bScratch_reg_12_)) + (portref CE (instanceref bScratch_reg_13_)) + (portref CE (instanceref bScratch_reg_14_)) + (portref CE (instanceref bScratch_reg_15_)) + (portref CE (instanceref bScratch_reg_16_)) + (portref CE (instanceref bScratch_reg_17_)) + (portref CE (instanceref bScratch_reg_18_)) + (portref CE (instanceref bScratch_reg_19_)) + (portref CE (instanceref bScratch_reg_1_)) + (portref CE (instanceref bScratch_reg_20_)) + (portref CE (instanceref bScratch_reg_21_)) + (portref CE (instanceref bScratch_reg_22_)) + (portref CE (instanceref bScratch_reg_23_)) + (portref CE (instanceref bScratch_reg_24_)) + (portref CE (instanceref bScratch_reg_25_)) + (portref CE (instanceref bScratch_reg_26_)) + (portref CE (instanceref bScratch_reg_27_)) + (portref CE (instanceref bScratch_reg_28_)) + (portref CE (instanceref bScratch_reg_29_)) + (portref CE (instanceref bScratch_reg_2_)) + (portref CE (instanceref bScratch_reg_30_)) + (portref CE (instanceref bScratch_reg_31_)) + (portref CE (instanceref bScratch_reg_3_)) + (portref CE (instanceref bScratch_reg_4_)) + (portref CE (instanceref bScratch_reg_5_)) + (portref CE (instanceref bScratch_reg_6_)) + (portref CE (instanceref bScratch_reg_7_)) + (portref CE (instanceref bScratch_reg_8_)) + (portref CE (instanceref bScratch_reg_9_)) + (portref O (instanceref bScratch_31__i_1)) + ) + ) + (net (rename bScratch_31__i_3_n_0 "bScratch[31]_i_3_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_3__0)) + (portref I0 (instanceref Gen0_FDCEx_i_3__1)) + (portref I0 (instanceref bScratch_31__i_1)) + (portref I3 (instanceref Gen0_FDCEx_i_3)) + (portref I3 (instanceref bPpsClkCrossDelayVal_3__i_3)) + (portref O (instanceref bScratch_31__i_3)) + ) + ) + (net (rename bScratch_31__i_4_n_0 "bScratch[31]_i_4_n_0") (joined + (portref I2 (instanceref bScratch_31__i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__16__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__26__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_5)) + (portref O (instanceref bScratch_31__i_4)) + ) + ) + (net (rename bScratch_31__i_5_n_0 "bScratch[31]_i_5_n_0") (joined + (portref I5 (instanceref bScratch_31__i_1)) + (portref O (instanceref bScratch_31__i_5)) + ) + ) + (net (rename bScratch_3_ "bScratch[3]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__3__i_4)) + (portref Q (instanceref bScratch_reg_3_)) + ) + ) + (net (rename bScratch_4_ "bScratch[4]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_7)) + (portref Q (instanceref bScratch_reg_4_)) + ) + ) + (net (rename bScratch_5_ "bScratch[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref Q (instanceref bScratch_reg_5_)) + ) + ) + (net (rename bScratch_6_ "bScratch[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_1)) + (portref Q (instanceref bScratch_reg_6_)) + ) + ) + (net (rename bScratch_7_ "bScratch[7]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_4)) + (portref Q (instanceref bScratch_reg_7_)) + ) + ) + (net (rename bScratch_8_ "bScratch[8]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_4)) + (portref Q (instanceref bScratch_reg_8_)) + ) + ) + (net (rename bScratch_9_ "bScratch[9]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__9__i_4)) + (portref Q (instanceref bScratch_reg_9_)) + ) + ) + (net bSpOffsetStored (joined + (portref CE (instanceref bRpOffsetStored_reg_0_)) + (portref CE (instanceref bRpOffsetStored_reg_10_)) + (portref CE (instanceref bRpOffsetStored_reg_11_)) + (portref CE (instanceref bRpOffsetStored_reg_12_)) + (portref CE (instanceref bRpOffsetStored_reg_13_)) + (portref CE (instanceref bRpOffsetStored_reg_14_)) + (portref CE (instanceref bRpOffsetStored_reg_15_)) + (portref CE (instanceref bRpOffsetStored_reg_16_)) + (portref CE (instanceref bRpOffsetStored_reg_17_)) + (portref CE (instanceref bRpOffsetStored_reg_18_)) + (portref CE (instanceref bRpOffsetStored_reg_19_)) + (portref CE (instanceref bRpOffsetStored_reg_1_)) + (portref CE (instanceref bRpOffsetStored_reg_20_)) + (portref CE (instanceref bRpOffsetStored_reg_21_)) + (portref CE (instanceref bRpOffsetStored_reg_22_)) + (portref CE (instanceref bRpOffsetStored_reg_23_)) + (portref CE (instanceref bRpOffsetStored_reg_24_)) + (portref CE (instanceref bRpOffsetStored_reg_25_)) + (portref CE (instanceref bRpOffsetStored_reg_26_)) + (portref CE (instanceref bRpOffsetStored_reg_27_)) + (portref CE (instanceref bRpOffsetStored_reg_28_)) + (portref CE (instanceref bRpOffsetStored_reg_29_)) + (portref CE (instanceref bRpOffsetStored_reg_2_)) + (portref CE (instanceref bRpOffsetStored_reg_30_)) + (portref CE (instanceref bRpOffsetStored_reg_31_)) + (portref CE (instanceref bRpOffsetStored_reg_32_)) + (portref CE (instanceref bRpOffsetStored_reg_33_)) + (portref CE (instanceref bRpOffsetStored_reg_34_)) + (portref CE (instanceref bRpOffsetStored_reg_35_)) + (portref CE (instanceref bRpOffsetStored_reg_36_)) + (portref CE (instanceref bRpOffsetStored_reg_37_)) + (portref CE (instanceref bRpOffsetStored_reg_38_)) + (portref CE (instanceref bRpOffsetStored_reg_39_)) + (portref CE (instanceref bRpOffsetStored_reg_3_)) + (portref CE (instanceref bRpOffsetStored_reg_4_)) + (portref CE (instanceref bRpOffsetStored_reg_5_)) + (portref CE (instanceref bRpOffsetStored_reg_6_)) + (portref CE (instanceref bRpOffsetStored_reg_7_)) + (portref CE (instanceref bRpOffsetStored_reg_8_)) + (portref CE (instanceref bRpOffsetStored_reg_9_)) + (portref CE (instanceref bSpOffsetStored_reg_0_)) + (portref CE (instanceref bSpOffsetStored_reg_10_)) + (portref CE (instanceref bSpOffsetStored_reg_11_)) + (portref CE (instanceref bSpOffsetStored_reg_12_)) + (portref CE (instanceref bSpOffsetStored_reg_13_)) + (portref CE (instanceref bSpOffsetStored_reg_14_)) + (portref CE (instanceref bSpOffsetStored_reg_15_)) + (portref CE (instanceref bSpOffsetStored_reg_16_)) + (portref CE (instanceref bSpOffsetStored_reg_17_)) + (portref CE (instanceref bSpOffsetStored_reg_18_)) + (portref CE (instanceref bSpOffsetStored_reg_19_)) + (portref CE (instanceref bSpOffsetStored_reg_1_)) + (portref CE (instanceref bSpOffsetStored_reg_20_)) + (portref CE (instanceref bSpOffsetStored_reg_21_)) + (portref CE (instanceref bSpOffsetStored_reg_22_)) + (portref CE (instanceref bSpOffsetStored_reg_23_)) + (portref CE (instanceref bSpOffsetStored_reg_24_)) + (portref CE (instanceref bSpOffsetStored_reg_25_)) + (portref CE (instanceref bSpOffsetStored_reg_26_)) + (portref CE (instanceref bSpOffsetStored_reg_27_)) + (portref CE (instanceref bSpOffsetStored_reg_28_)) + (portref CE (instanceref bSpOffsetStored_reg_29_)) + (portref CE (instanceref bSpOffsetStored_reg_2_)) + (portref CE (instanceref bSpOffsetStored_reg_30_)) + (portref CE (instanceref bSpOffsetStored_reg_31_)) + (portref CE (instanceref bSpOffsetStored_reg_3_)) + (portref CE (instanceref bSpOffsetStored_reg_4_)) + (portref CE (instanceref bSpOffsetStored_reg_5_)) + (portref CE (instanceref bSpOffsetStored_reg_6_)) + (portref CE (instanceref bSpOffsetStored_reg_7_)) + (portref CE (instanceref bSpOffsetStored_reg_8_)) + (portref CE (instanceref bSpOffsetStored_reg_9_)) + (portref I1 (instanceref bOffsetUpdated_i_1)) + (portref O (instanceref bRpOffsetStored_39__i_1)) + ) + ) + (net (rename bSpOffsetStored_0__i_1_n_0 "bSpOffsetStored[0]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_0_)) + (portref O (instanceref bSpOffsetStored_0__i_1)) + ) + ) + (net (rename bSpOffsetStored_10__i_1_n_0 "bSpOffsetStored[10]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_10_)) + (portref O (instanceref bSpOffsetStored_10__i_1)) + ) + ) + (net (rename bSpOffsetStored_11__i_1_n_0 "bSpOffsetStored[11]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_11_)) + (portref O (instanceref bSpOffsetStored_11__i_1)) + ) + ) + (net (rename bSpOffsetStored_12__i_1_n_0 "bSpOffsetStored[12]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_12_)) + (portref O (instanceref bSpOffsetStored_12__i_1)) + ) + ) + (net (rename bSpOffsetStored_13__i_1_n_0 "bSpOffsetStored[13]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_13_)) + (portref O (instanceref bSpOffsetStored_13__i_1)) + ) + ) + (net (rename bSpOffsetStored_14__i_1_n_0 "bSpOffsetStored[14]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_14_)) + (portref O (instanceref bSpOffsetStored_14__i_1)) + ) + ) + (net (rename bSpOffsetStored_15__i_1_n_0 "bSpOffsetStored[15]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_15_)) + (portref O (instanceref bSpOffsetStored_15__i_1)) + ) + ) + (net (rename bSpOffsetStored_16__i_1_n_0 "bSpOffsetStored[16]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_16_)) + (portref O (instanceref bSpOffsetStored_16__i_1)) + ) + ) + (net (rename bSpOffsetStored_17__i_1_n_0 "bSpOffsetStored[17]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_17_)) + (portref O (instanceref bSpOffsetStored_17__i_1)) + ) + ) + (net (rename bSpOffsetStored_18__i_1_n_0 "bSpOffsetStored[18]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_18_)) + (portref O (instanceref bSpOffsetStored_18__i_1)) + ) + ) + (net (rename bSpOffsetStored_19__i_1_n_0 "bSpOffsetStored[19]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_19_)) + (portref O (instanceref bSpOffsetStored_19__i_1)) + ) + ) + (net (rename bSpOffsetStored_1__i_1_n_0 "bSpOffsetStored[1]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_1_)) + (portref O (instanceref bSpOffsetStored_1__i_1)) + ) + ) + (net (rename bSpOffsetStored_20__i_1_n_0 "bSpOffsetStored[20]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_20_)) + (portref O (instanceref bSpOffsetStored_20__i_1)) + ) + ) + (net (rename bSpOffsetStored_21__i_1_n_0 "bSpOffsetStored[21]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_21_)) + (portref O (instanceref bSpOffsetStored_21__i_1)) + ) + ) + (net (rename bSpOffsetStored_22__i_1_n_0 "bSpOffsetStored[22]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_22_)) + (portref O (instanceref bSpOffsetStored_22__i_1)) + ) + ) + (net (rename bSpOffsetStored_23__i_1_n_0 "bSpOffsetStored[23]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_23_)) + (portref O (instanceref bSpOffsetStored_23__i_1)) + ) + ) + (net (rename bSpOffsetStored_24__i_1_n_0 "bSpOffsetStored[24]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_24_)) + (portref O (instanceref bSpOffsetStored_24__i_1)) + ) + ) + (net (rename bSpOffsetStored_25__i_1_n_0 "bSpOffsetStored[25]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_25_)) + (portref O (instanceref bSpOffsetStored_25__i_1)) + ) + ) + (net (rename bSpOffsetStored_26__i_1_n_0 "bSpOffsetStored[26]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_26_)) + (portref O (instanceref bSpOffsetStored_26__i_1)) + ) + ) + (net (rename bSpOffsetStored_27__i_1_n_0 "bSpOffsetStored[27]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_27_)) + (portref O (instanceref bSpOffsetStored_27__i_1)) + ) + ) + (net (rename bSpOffsetStored_28__i_1_n_0 "bSpOffsetStored[28]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_28_)) + (portref O (instanceref bSpOffsetStored_28__i_1)) + ) + ) + (net (rename bSpOffsetStored_29__i_1_n_0 "bSpOffsetStored[29]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_29_)) + (portref O (instanceref bSpOffsetStored_29__i_1)) + ) + ) + (net (rename bSpOffsetStored_2__i_1_n_0 "bSpOffsetStored[2]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_2_)) + (portref O (instanceref bSpOffsetStored_2__i_1)) + ) + ) + (net (rename bSpOffsetStored_30__i_1_n_0 "bSpOffsetStored[30]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_30_)) + (portref O (instanceref bSpOffsetStored_30__i_1)) + ) + ) + (net (rename bSpOffsetStored_31__i_1_n_0 "bSpOffsetStored[31]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_31_)) + (portref O (instanceref bSpOffsetStored_31__i_1)) + ) + ) + (net (rename bSpOffsetStored_3__i_1_n_0 "bSpOffsetStored[3]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_3_)) + (portref O (instanceref bSpOffsetStored_3__i_1)) + ) + ) + (net (rename bSpOffsetStored_4__i_1_n_0 "bSpOffsetStored[4]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_4_)) + (portref O (instanceref bSpOffsetStored_4__i_1)) + ) + ) + (net (rename bSpOffsetStored_5__i_1_n_0 "bSpOffsetStored[5]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_5_)) + (portref O (instanceref bSpOffsetStored_5__i_1)) + ) + ) + (net (rename bSpOffsetStored_6__i_1_n_0 "bSpOffsetStored[6]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_6_)) + (portref O (instanceref bSpOffsetStored_6__i_1)) + ) + ) + (net (rename bSpOffsetStored_7__i_1_n_0 "bSpOffsetStored[7]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_7_)) + (portref O (instanceref bSpOffsetStored_7__i_1)) + ) + ) + (net (rename bSpOffsetStored_8__i_1_n_0 "bSpOffsetStored[8]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_8_)) + (portref O (instanceref bSpOffsetStored_8__i_1)) + ) + ) + (net (rename bSpOffsetStored_9__i_1_n_0 "bSpOffsetStored[9]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_9_)) + (portref O (instanceref bSpOffsetStored_9__i_1)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__0_ "bSpOffsetStored_reg_n_0_[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_0_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__10_ "bSpOffsetStored_reg_n_0_[10]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_10_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__11_ "bSpOffsetStored_reg_n_0_[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_11_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__12_ "bSpOffsetStored_reg_n_0_[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_12_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__13_ "bSpOffsetStored_reg_n_0_[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_13_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__14_ "bSpOffsetStored_reg_n_0_[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_14_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__15_ "bSpOffsetStored_reg_n_0_[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_15_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__16_ "bSpOffsetStored_reg_n_0_[16]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_16_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__17_ "bSpOffsetStored_reg_n_0_[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_17_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__18_ "bSpOffsetStored_reg_n_0_[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_18_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__19_ "bSpOffsetStored_reg_n_0_[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_19_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__1_ "bSpOffsetStored_reg_n_0_[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_1_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__20_ "bSpOffsetStored_reg_n_0_[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_20_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__21_ "bSpOffsetStored_reg_n_0_[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_21_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__22_ "bSpOffsetStored_reg_n_0_[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_22_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__23_ "bSpOffsetStored_reg_n_0_[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_23_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__24_ "bSpOffsetStored_reg_n_0_[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_24_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__25_ "bSpOffsetStored_reg_n_0_[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_25_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__26_ "bSpOffsetStored_reg_n_0_[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_26_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__27_ "bSpOffsetStored_reg_n_0_[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_27_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__28_ "bSpOffsetStored_reg_n_0_[28]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_28_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__29_ "bSpOffsetStored_reg_n_0_[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_29_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__2_ "bSpOffsetStored_reg_n_0_[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_2_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__30_ "bSpOffsetStored_reg_n_0_[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_30_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__31_ "bSpOffsetStored_reg_n_0_[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_31_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__3_ "bSpOffsetStored_reg_n_0_[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_3_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__4_ "bSpOffsetStored_reg_n_0_[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_4_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__5_ "bSpOffsetStored_reg_n_0_[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_5_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__6_ "bSpOffsetStored_reg_n_0_[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_6_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__7_ "bSpOffsetStored_reg_n_0_[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_7_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__8_ "bSpOffsetStored_reg_n_0_[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_8_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__9_ "bSpOffsetStored_reg_n_0_[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_9_)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_0_ "bSpPeriodCtrlReadbackSyncReset[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_10_ "bSpPeriodCtrlReadbackSyncReset[10]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_11_ "bSpPeriodCtrlReadbackSyncReset[11]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_12_ "bSpPeriodCtrlReadbackSyncReset[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_13_ "bSpPeriodCtrlReadbackSyncReset[13]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_14_ "bSpPeriodCtrlReadbackSyncReset[14]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_15_ "bSpPeriodCtrlReadbackSyncReset[15]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_16_ "bSpPeriodCtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_17_ "bSpPeriodCtrlReadbackSyncReset[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_18_ "bSpPeriodCtrlReadbackSyncReset[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_19_ "bSpPeriodCtrlReadbackSyncReset[19]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_1_ "bSpPeriodCtrlReadbackSyncReset[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_20_ "bSpPeriodCtrlReadbackSyncReset[20]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_21_ "bSpPeriodCtrlReadbackSyncReset[21]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_22_ "bSpPeriodCtrlReadbackSyncReset[22]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_23_ "bSpPeriodCtrlReadbackSyncReset[23]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_24_ "bSpPeriodCtrlReadbackSyncReset[24]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_25_ "bSpPeriodCtrlReadbackSyncReset[25]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_26_ "bSpPeriodCtrlReadbackSyncReset[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_27_ "bSpPeriodCtrlReadbackSyncReset[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_28_ "bSpPeriodCtrlReadbackSyncReset[28]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_29_ "bSpPeriodCtrlReadbackSyncReset[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_2_ "bSpPeriodCtrlReadbackSyncReset[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_30_ "bSpPeriodCtrlReadbackSyncReset[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_31_ "bSpPeriodCtrlReadbackSyncReset[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_3_ "bSpPeriodCtrlReadbackSyncReset[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_4_ "bSpPeriodCtrlReadbackSyncReset[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_5_ "bSpPeriodCtrlReadbackSyncReset[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_6_ "bSpPeriodCtrlReadbackSyncReset[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_7_ "bSpPeriodCtrlReadbackSyncReset[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_8_ "bSpPeriodCtrlReadbackSyncReset[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_9_ "bSpPeriodCtrlReadbackSyncReset[9]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadback_0_ "bSpPeriodCtrlReadback[0]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_10_ "bSpPeriodCtrlReadback[10]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_11_ "bSpPeriodCtrlReadback[11]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_12_ "bSpPeriodCtrlReadback[12]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_13_ "bSpPeriodCtrlReadback[13]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_14_ "bSpPeriodCtrlReadback[14]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_15_ "bSpPeriodCtrlReadback[15]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_16_ "bSpPeriodCtrlReadback[16]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_17_ "bSpPeriodCtrlReadback[17]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_18_ "bSpPeriodCtrlReadback[18]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_19_ "bSpPeriodCtrlReadback[19]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_1_ "bSpPeriodCtrlReadback[1]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_20_ "bSpPeriodCtrlReadback[20]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_21_ "bSpPeriodCtrlReadback[21]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_22_ "bSpPeriodCtrlReadback[22]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_23_ "bSpPeriodCtrlReadback[23]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_24_ "bSpPeriodCtrlReadback[24]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_25_ "bSpPeriodCtrlReadback[25]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_26_ "bSpPeriodCtrlReadback[26]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_27_ "bSpPeriodCtrlReadback[27]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_28_ "bSpPeriodCtrlReadback[28]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_29_ "bSpPeriodCtrlReadback[29]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_2_ "bSpPeriodCtrlReadback[2]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_30_ "bSpPeriodCtrlReadback[30]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_31_ "bSpPeriodCtrlReadback[31]") (joined + (portref D (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_3_ "bSpPeriodCtrlReadback[3]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_4_ "bSpPeriodCtrlReadback[4]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_5_ "bSpPeriodCtrlReadback[5]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_6_ "bSpPeriodCtrlReadback[6]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_7_ "bSpPeriodCtrlReadback[7]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_8_ "bSpPeriodCtrlReadback[8]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_9_ "bSpPeriodCtrlReadback[9]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_0_ "bSptPeriodCtrlReadbackSyncReset[0]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_10_ "bSptPeriodCtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_11_ "bSptPeriodCtrlReadbackSyncReset[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_12_ "bSptPeriodCtrlReadbackSyncReset[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_13_ "bSptPeriodCtrlReadbackSyncReset[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_14_ "bSptPeriodCtrlReadbackSyncReset[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_15_ "bSptPeriodCtrlReadbackSyncReset[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_16_ "bSptPeriodCtrlReadbackSyncReset[16]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_17_ "bSptPeriodCtrlReadbackSyncReset[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_18_ "bSptPeriodCtrlReadbackSyncReset[18]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_19_ "bSptPeriodCtrlReadbackSyncReset[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_1_ "bSptPeriodCtrlReadbackSyncReset[1]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_20_ "bSptPeriodCtrlReadbackSyncReset[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_21_ "bSptPeriodCtrlReadbackSyncReset[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_22_ "bSptPeriodCtrlReadbackSyncReset[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_23_ "bSptPeriodCtrlReadbackSyncReset[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_24_ "bSptPeriodCtrlReadbackSyncReset[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_25_ "bSptPeriodCtrlReadbackSyncReset[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_26_ "bSptPeriodCtrlReadbackSyncReset[26]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_27_ "bSptPeriodCtrlReadbackSyncReset[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_28_ "bSptPeriodCtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_29_ "bSptPeriodCtrlReadbackSyncReset[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_2_ "bSptPeriodCtrlReadbackSyncReset[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_30_ "bSptPeriodCtrlReadbackSyncReset[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_31_ "bSptPeriodCtrlReadbackSyncReset[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_3_ "bSptPeriodCtrlReadbackSyncReset[3]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_4_ "bSptPeriodCtrlReadbackSyncReset[4]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_5_ "bSptPeriodCtrlReadbackSyncReset[5]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_6_ "bSptPeriodCtrlReadbackSyncReset[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_7_ "bSptPeriodCtrlReadbackSyncReset[7]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_8_ "bSptPeriodCtrlReadbackSyncReset[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_9_ "bSptPeriodCtrlReadbackSyncReset[9]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadback_0_ "bSptPeriodCtrlReadback[0]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_10_ "bSptPeriodCtrlReadback[10]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_11_ "bSptPeriodCtrlReadback[11]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_12_ "bSptPeriodCtrlReadback[12]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_13_ "bSptPeriodCtrlReadback[13]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_14_ "bSptPeriodCtrlReadback[14]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_15_ "bSptPeriodCtrlReadback[15]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_16_ "bSptPeriodCtrlReadback[16]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_17_ "bSptPeriodCtrlReadback[17]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_18_ "bSptPeriodCtrlReadback[18]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_19_ "bSptPeriodCtrlReadback[19]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_1_ "bSptPeriodCtrlReadback[1]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_20_ "bSptPeriodCtrlReadback[20]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_21_ "bSptPeriodCtrlReadback[21]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_22_ "bSptPeriodCtrlReadback[22]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_23_ "bSptPeriodCtrlReadback[23]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_24_ "bSptPeriodCtrlReadback[24]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_25_ "bSptPeriodCtrlReadback[25]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_26_ "bSptPeriodCtrlReadback[26]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_27_ "bSptPeriodCtrlReadback[27]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_28_ "bSptPeriodCtrlReadback[28]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_29_ "bSptPeriodCtrlReadback[29]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_2_ "bSptPeriodCtrlReadback[2]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_30_ "bSptPeriodCtrlReadback[30]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_31_ "bSptPeriodCtrlReadback[31]") (joined + (portref D (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_3_ "bSptPeriodCtrlReadback[3]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_4_ "bSptPeriodCtrlReadback[4]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_5_ "bSptPeriodCtrlReadback[5]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_6_ "bSptPeriodCtrlReadback[6]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_7_ "bSptPeriodCtrlReadback[7]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_8_ "bSptPeriodCtrlReadback[8]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_9_ "bSptPeriodCtrlReadback[9]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net iDlyPush (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__4)) + (portref Q (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net mOffsetsValid (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__11)) + (portref mOffsetsValid) + ) + ) + (net (rename mRpOffset_0_ "mRpOffset[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref (member mRpOffset 39)) + ) + ) + (net (rename mRpOffset_10_ "mRpOffset[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref (member mRpOffset 29)) + ) + ) + (net (rename mRpOffset_11_ "mRpOffset[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref (member mRpOffset 28)) + ) + ) + (net (rename mRpOffset_12_ "mRpOffset[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref (member mRpOffset 27)) + ) + ) + (net (rename mRpOffset_13_ "mRpOffset[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref (member mRpOffset 26)) + ) + ) + (net (rename mRpOffset_14_ "mRpOffset[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref (member mRpOffset 25)) + ) + ) + (net (rename mRpOffset_15_ "mRpOffset[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref (member mRpOffset 24)) + ) + ) + (net (rename mRpOffset_16_ "mRpOffset[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref (member mRpOffset 23)) + ) + ) + (net (rename mRpOffset_17_ "mRpOffset[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref (member mRpOffset 22)) + ) + ) + (net (rename mRpOffset_18_ "mRpOffset[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref (member mRpOffset 21)) + ) + ) + (net (rename mRpOffset_19_ "mRpOffset[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref (member mRpOffset 20)) + ) + ) + (net (rename mRpOffset_1_ "mRpOffset[1]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref (member mRpOffset 38)) + ) + ) + (net (rename mRpOffset_20_ "mRpOffset[20]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref (member mRpOffset 19)) + ) + ) + (net (rename mRpOffset_21_ "mRpOffset[21]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref (member mRpOffset 18)) + ) + ) + (net (rename mRpOffset_22_ "mRpOffset[22]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref (member mRpOffset 17)) + ) + ) + (net (rename mRpOffset_23_ "mRpOffset[23]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref (member mRpOffset 16)) + ) + ) + (net (rename mRpOffset_24_ "mRpOffset[24]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref (member mRpOffset 15)) + ) + ) + (net (rename mRpOffset_25_ "mRpOffset[25]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref (member mRpOffset 14)) + ) + ) + (net (rename mRpOffset_26_ "mRpOffset[26]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref (member mRpOffset 13)) + ) + ) + (net (rename mRpOffset_27_ "mRpOffset[27]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref (member mRpOffset 12)) + ) + ) + (net (rename mRpOffset_28_ "mRpOffset[28]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref (member mRpOffset 11)) + ) + ) + (net (rename mRpOffset_29_ "mRpOffset[29]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref (member mRpOffset 10)) + ) + ) + (net (rename mRpOffset_2_ "mRpOffset[2]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref (member mRpOffset 37)) + ) + ) + (net (rename mRpOffset_30_ "mRpOffset[30]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref (member mRpOffset 9)) + ) + ) + (net (rename mRpOffset_31_ "mRpOffset[31]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref (member mRpOffset 8)) + ) + ) + (net (rename mRpOffset_32_ "mRpOffset[32]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref (member mRpOffset 7)) + ) + ) + (net (rename mRpOffset_33_ "mRpOffset[33]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref (member mRpOffset 6)) + ) + ) + (net (rename mRpOffset_34_ "mRpOffset[34]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref (member mRpOffset 5)) + ) + ) + (net (rename mRpOffset_35_ "mRpOffset[35]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref (member mRpOffset 4)) + ) + ) + (net (rename mRpOffset_36_ "mRpOffset[36]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref (member mRpOffset 3)) + ) + ) + (net (rename mRpOffset_37_ "mRpOffset[37]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref (member mRpOffset 2)) + ) + ) + (net (rename mRpOffset_38_ "mRpOffset[38]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref (member mRpOffset 1)) + ) + ) + (net (rename mRpOffset_39_ "mRpOffset[39]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref (member mRpOffset 0)) + ) + ) + (net (rename mRpOffset_3_ "mRpOffset[3]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref (member mRpOffset 36)) + ) + ) + (net (rename mRpOffset_4_ "mRpOffset[4]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref (member mRpOffset 35)) + ) + ) + (net (rename mRpOffset_5_ "mRpOffset[5]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref (member mRpOffset 34)) + ) + ) + (net (rename mRpOffset_6_ "mRpOffset[6]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref (member mRpOffset 33)) + ) + ) + (net (rename mRpOffset_7_ "mRpOffset[7]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref (member mRpOffset 32)) + ) + ) + (net (rename mRpOffset_8_ "mRpOffset[8]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref (member mRpOffset 31)) + ) + ) + (net (rename mRpOffset_9_ "mRpOffset[9]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref (member mRpOffset 30)) + ) + ) + (net (rename mSpOffset_0_ "mSpOffset[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref (member mSpOffset 39)) + ) + ) + (net (rename mSpOffset_10_ "mSpOffset[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref (member mSpOffset 29)) + ) + ) + (net (rename mSpOffset_11_ "mSpOffset[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref (member mSpOffset 28)) + ) + ) + (net (rename mSpOffset_12_ "mSpOffset[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref (member mSpOffset 27)) + ) + ) + (net (rename mSpOffset_13_ "mSpOffset[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref (member mSpOffset 26)) + ) + ) + (net (rename mSpOffset_14_ "mSpOffset[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref (member mSpOffset 25)) + ) + ) + (net (rename mSpOffset_15_ "mSpOffset[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref (member mSpOffset 24)) + ) + ) + (net (rename mSpOffset_16_ "mSpOffset[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref (member mSpOffset 23)) + ) + ) + (net (rename mSpOffset_17_ "mSpOffset[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref (member mSpOffset 22)) + ) + ) + (net (rename mSpOffset_18_ "mSpOffset[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref (member mSpOffset 21)) + ) + ) + (net (rename mSpOffset_19_ "mSpOffset[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref (member mSpOffset 20)) + ) + ) + (net (rename mSpOffset_1_ "mSpOffset[1]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref (member mSpOffset 38)) + ) + ) + (net (rename mSpOffset_20_ "mSpOffset[20]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref (member mSpOffset 19)) + ) + ) + (net (rename mSpOffset_21_ "mSpOffset[21]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref (member mSpOffset 18)) + ) + ) + (net (rename mSpOffset_22_ "mSpOffset[22]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref (member mSpOffset 17)) + ) + ) + (net (rename mSpOffset_23_ "mSpOffset[23]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref (member mSpOffset 16)) + ) + ) + (net (rename mSpOffset_24_ "mSpOffset[24]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref (member mSpOffset 15)) + ) + ) + (net (rename mSpOffset_25_ "mSpOffset[25]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref (member mSpOffset 14)) + ) + ) + (net (rename mSpOffset_26_ "mSpOffset[26]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref (member mSpOffset 13)) + ) + ) + (net (rename mSpOffset_27_ "mSpOffset[27]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref (member mSpOffset 12)) + ) + ) + (net (rename mSpOffset_28_ "mSpOffset[28]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref (member mSpOffset 11)) + ) + ) + (net (rename mSpOffset_29_ "mSpOffset[29]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref (member mSpOffset 10)) + ) + ) + (net (rename mSpOffset_2_ "mSpOffset[2]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref (member mSpOffset 37)) + ) + ) + (net (rename mSpOffset_30_ "mSpOffset[30]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref (member mSpOffset 9)) + ) + ) + (net (rename mSpOffset_31_ "mSpOffset[31]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref (member mSpOffset 8)) + ) + ) + (net (rename mSpOffset_32_ "mSpOffset[32]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref (member mSpOffset 7)) + ) + ) + (net (rename mSpOffset_33_ "mSpOffset[33]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref (member mSpOffset 6)) + ) + ) + (net (rename mSpOffset_34_ "mSpOffset[34]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref (member mSpOffset 5)) + ) + ) + (net (rename mSpOffset_35_ "mSpOffset[35]") (joined + (portref D (instanceref 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(portref I0 (instanceref bRpOffsetStored_33__i_1)) + (portref Q (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_74_out (joined + (portref I0 (instanceref bRpOffsetStored_34__i_1)) + (portref Q (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_75_out (joined + (portref I0 (instanceref bRpOffsetStored_35__i_1)) + (portref Q (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_76_out (joined + (portref I0 (instanceref bRpOffsetStored_36__i_1)) + (portref Q (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_77_out (joined + (portref I0 (instanceref bRpOffsetStored_37__i_1)) + (portref Q (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_78_out (joined + (portref I0 (instanceref bRpOffsetStored_38__i_1)) + (portref Q (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_79_out (joined + (portref I0 (instanceref bRpOffsetStored_39__i_2)) + (portref Q (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_7_out (joined + (portref I0 (instanceref bSpOffsetStored_7__i_1)) + (portref Q (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_8_out (joined + (portref I0 (instanceref bSpOffsetStored_8__i_1)) + (portref Q (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_9_out (joined + (portref I0 (instanceref bSpOffsetStored_9__i_1)) + (portref Q (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net rEnablePpsCrossing (joined + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rEnablePpsCrossing) + ) + ) + (net rEnableTdc (joined + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rEnableTdc) + ) + ) + (net rLoadRePulseCounts (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref rLoadRePulseCounts) + ) + ) + (net rLoadRpCounts (joined + (portref Q (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref rLoadRpCounts) + ) + ) + (net rLoadRptCounts (joined + (portref Q (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref rLoadRptCounts) + ) + ) + (net rPpsPulseCaptured (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref rPpsPulseCaptured) + ) + ) + (net (rename rPulserEnableDelayValTemp_0_ "rPulserEnableDelayValTemp[0]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_0_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_1_ "rPulserEnableDelayValTemp[1]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_1_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_2_ "rPulserEnableDelayValTemp[2]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_2_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_3_ "rPulserEnableDelayValTemp[3]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_3_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayVal_0_ "rPulserEnableDelayVal[0]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_0_)) + (portref (member rPulserEnableDelayVal 3)) + ) + ) + (net (rename rPulserEnableDelayVal_1_ "rPulserEnableDelayVal[1]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_1_)) + (portref (member rPulserEnableDelayVal 2)) + ) + ) + (net (rename rPulserEnableDelayVal_2_ "rPulserEnableDelayVal[2]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_2_)) + (portref (member rPulserEnableDelayVal 1)) + ) + ) + (net (rename rPulserEnableDelayVal_3_ "rPulserEnableDelayVal[3]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_3_)) + (portref (member rPulserEnableDelayVal 0)) + ) + ) + (net (rename rRePulseHighTimeInRClks_0_ "rRePulseHighTimeInRClks[0]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 23)) + ) + ) + (net (rename rRePulseHighTimeInRClks_10_ "rRePulseHighTimeInRClks[10]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 13)) + ) + ) + (net (rename rRePulseHighTimeInRClks_11_ "rRePulseHighTimeInRClks[11]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 12)) + ) + ) + (net (rename rRePulseHighTimeInRClks_12_ "rRePulseHighTimeInRClks[12]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 11)) + ) + ) + (net (rename rRePulseHighTimeInRClks_13_ "rRePulseHighTimeInRClks[13]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 10)) + ) + ) + (net (rename rRePulseHighTimeInRClks_14_ "rRePulseHighTimeInRClks[14]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 9)) + ) + ) + (net (rename rRePulseHighTimeInRClks_15_ "rRePulseHighTimeInRClks[15]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 8)) + ) + ) + (net (rename rRePulseHighTimeInRClks_16_ "rRePulseHighTimeInRClks[16]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 7)) + ) + ) + (net (rename rRePulseHighTimeInRClks_17_ "rRePulseHighTimeInRClks[17]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 6)) + ) + ) + (net (rename rRePulseHighTimeInRClks_18_ "rRePulseHighTimeInRClks[18]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 5)) + ) + ) + (net (rename rRePulseHighTimeInRClks_19_ "rRePulseHighTimeInRClks[19]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 4)) + ) + ) + (net (rename rRePulseHighTimeInRClks_1_ "rRePulseHighTimeInRClks[1]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 22)) + ) + ) + (net (rename rRePulseHighTimeInRClks_20_ "rRePulseHighTimeInRClks[20]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 3)) + ) + ) + (net (rename rRePulseHighTimeInRClks_21_ "rRePulseHighTimeInRClks[21]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 2)) + ) + ) + (net (rename rRePulseHighTimeInRClks_22_ "rRePulseHighTimeInRClks[22]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 1)) + ) + ) + (net (rename rRePulseHighTimeInRClks_2_ "rRePulseHighTimeInRClks[2]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 21)) + ) + ) + (net (rename rRePulseHighTimeInRClks_3_ "rRePulseHighTimeInRClks[3]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 20)) + ) + ) + (net (rename rRePulseHighTimeInRClks_4_ "rRePulseHighTimeInRClks[4]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 19)) + ) + ) + (net (rename rRePulseHighTimeInRClks_5_ "rRePulseHighTimeInRClks[5]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 18)) + ) + ) + (net (rename rRePulseHighTimeInRClks_6_ "rRePulseHighTimeInRClks[6]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 17)) + ) + ) + (net (rename rRePulseHighTimeInRClks_7_ "rRePulseHighTimeInRClks[7]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 16)) + ) + ) + (net (rename rRePulseHighTimeInRClks_8_ "rRePulseHighTimeInRClks[8]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 15)) + ) + ) + (net (rename rRePulseHighTimeInRClks_9_ "rRePulseHighTimeInRClks[9]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 14)) + ) + ) + (net (rename rRePulsePeriodInRClks_0_ "rRePulsePeriodInRClks[0]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 23)) + ) + ) + (net (rename rRePulsePeriodInRClks_10_ "rRePulsePeriodInRClks[10]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 13)) + ) + ) + (net (rename rRePulsePeriodInRClks_11_ "rRePulsePeriodInRClks[11]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 12)) + ) + ) + (net (rename rRePulsePeriodInRClks_12_ "rRePulsePeriodInRClks[12]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 11)) + ) + ) + (net (rename rRePulsePeriodInRClks_13_ "rRePulsePeriodInRClks[13]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 10)) + ) + ) + (net (rename rRePulsePeriodInRClks_14_ "rRePulsePeriodInRClks[14]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 9)) + ) + ) + (net (rename rRePulsePeriodInRClks_15_ "rRePulsePeriodInRClks[15]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 8)) + ) + ) + (net (rename rRePulsePeriodInRClks_16_ "rRePulsePeriodInRClks[16]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 7)) + ) + ) + (net (rename rRePulsePeriodInRClks_17_ "rRePulsePeriodInRClks[17]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 6)) + ) + ) + (net (rename rRePulsePeriodInRClks_18_ "rRePulsePeriodInRClks[18]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 5)) + ) + ) + (net (rename rRePulsePeriodInRClks_19_ "rRePulsePeriodInRClks[19]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 4)) + ) + ) + (net (rename rRePulsePeriodInRClks_1_ "rRePulsePeriodInRClks[1]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 22)) + ) + ) + (net (rename rRePulsePeriodInRClks_20_ "rRePulsePeriodInRClks[20]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 3)) + ) + ) + (net (rename rRePulsePeriodInRClks_21_ "rRePulsePeriodInRClks[21]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 2)) + ) + ) + (net (rename rRePulsePeriodInRClks_22_ "rRePulsePeriodInRClks[22]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 1)) + ) + ) + (net (rename rRePulsePeriodInRClks_23_ "rRePulsePeriodInRClks[23]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 0)) + ) + ) + (net (rename rRePulsePeriodInRClks_2_ "rRePulsePeriodInRClks[2]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 21)) + ) + ) + (net (rename rRePulsePeriodInRClks_3_ "rRePulsePeriodInRClks[3]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 20)) + ) + ) + (net (rename rRePulsePeriodInRClks_4_ "rRePulsePeriodInRClks[4]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 19)) + ) + ) + (net (rename rRePulsePeriodInRClks_5_ "rRePulsePeriodInRClks[5]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 18)) + ) + ) + (net (rename rRePulsePeriodInRClks_6_ "rRePulsePeriodInRClks[6]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 17)) + ) + ) + (net (rename rRePulsePeriodInRClks_7_ "rRePulsePeriodInRClks[7]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 16)) + ) + ) + (net (rename rRePulsePeriodInRClks_8_ "rRePulsePeriodInRClks[8]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 15)) + ) + ) + (net (rename rRePulsePeriodInRClks_9_ "rRePulsePeriodInRClks[9]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 14)) + ) + ) + (net rReRunEnable (joined + (portref Q (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rReRunEnable) + ) + ) + (net rResetTdc (joined + (portref Q (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rResetTdc) + ) + ) + (net rResetTdcDone (joined + (portref D (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref rResetTdcDone) + ) + ) + (net (rename rRpHighTimeInRClks_0_ "rRpHighTimeInRClks[0]") (joined + (portref Q (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member rRpHighTimeInRClks 15)) + ) + ) + (net (rename rRpHighTimeInRClks_10_ "rRpHighTimeInRClks[10]") (joined + (portref Q (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref (member rRpHighTimeInRClks 5)) + ) + ) + (net (rename rRpHighTimeInRClks_11_ "rRpHighTimeInRClks[11]") (joined + (portref Q (instanceref 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(member rRptHighTimeInRClks 1)) + ) + ) + (net (rename rRptHighTimeInRClks_1_ "rRptHighTimeInRClks[1]") (joined + (portref Q (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member rRptHighTimeInRClks 14)) + ) + ) + (net (rename rRptHighTimeInRClks_2_ "rRptHighTimeInRClks[2]") (joined + (portref Q (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member rRptHighTimeInRClks 13)) + ) + ) + (net (rename rRptHighTimeInRClks_3_ "rRptHighTimeInRClks[3]") (joined + (portref Q (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref (member rRptHighTimeInRClks 12)) + ) + ) + (net (rename rRptHighTimeInRClks_4_ "rRptHighTimeInRClks[4]") (joined + (portref Q (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref (member rRptHighTimeInRClks 11)) + ) + ) + (net (rename rRptHighTimeInRClks_5_ "rRptHighTimeInRClks[5]") (joined + (portref Q (instanceref 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"sPpsClkCrossDelayValTemp[2]") (joined + (portref D (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename sPpsClkCrossDelayValTemp_3_ "sPpsClkCrossDelayValTemp[3]") (joined + (portref D (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename sPpsClkCrossDelayVal_0_ "sPpsClkCrossDelayVal[0]") (joined + (portref Q (instanceref sPpsClkCrossDelayVal_reg_0_)) + (portref (member sPpsClkCrossDelayVal 3)) + ) + ) + (net (rename sPpsClkCrossDelayVal_1_ "sPpsClkCrossDelayVal[1]") (joined + (portref Q (instanceref sPpsClkCrossDelayVal_reg_1_)) + (portref (member sPpsClkCrossDelayVal 2)) + ) + ) + (net (rename sPpsClkCrossDelayVal_2_ "sPpsClkCrossDelayVal[2]") (joined + (portref Q (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref (member sPpsClkCrossDelayVal 1)) + ) + ) + (net (rename sPpsClkCrossDelayVal_3_ "sPpsClkCrossDelayVal[3]") (joined + (portref Q (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref (member sPpsClkCrossDelayVal 0)) + ) + ) + (net (rename sSpHighTimeInSClks_0_ "sSpHighTimeInSClks[0]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 15)) + ) + ) + (net (rename sSpHighTimeInSClks_10_ "sSpHighTimeInSClks[10]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 5)) + ) + ) + (net (rename sSpHighTimeInSClks_11_ "sSpHighTimeInSClks[11]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 4)) + ) + ) + (net (rename sSpHighTimeInSClks_12_ "sSpHighTimeInSClks[12]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 3)) + ) + ) + (net (rename sSpHighTimeInSClks_13_ "sSpHighTimeInSClks[13]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 2)) + ) + ) + (net (rename sSpHighTimeInSClks_14_ "sSpHighTimeInSClks[14]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 1)) + ) + ) + (net (rename sSpHighTimeInSClks_1_ "sSpHighTimeInSClks[1]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 14)) + ) + ) + (net (rename sSpHighTimeInSClks_2_ "sSpHighTimeInSClks[2]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 13)) + ) + ) + (net (rename sSpHighTimeInSClks_3_ "sSpHighTimeInSClks[3]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 12)) + ) + ) + (net (rename sSpHighTimeInSClks_4_ "sSpHighTimeInSClks[4]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 11)) + ) + ) + (net (rename sSpHighTimeInSClks_5_ "sSpHighTimeInSClks[5]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 10)) + ) + ) + (net (rename sSpHighTimeInSClks_6_ "sSpHighTimeInSClks[6]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 9)) + ) + ) + (net (rename sSpHighTimeInSClks_7_ "sSpHighTimeInSClks[7]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 8)) + ) + ) + (net (rename sSpHighTimeInSClks_8_ "sSpHighTimeInSClks[8]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 7)) + ) + ) + (net (rename sSpHighTimeInSClks_9_ "sSpHighTimeInSClks[9]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref (member sSpHighTimeInSClks 6)) + ) + ) + (net (rename sSpPeriodInSClks_0_ "sSpPeriodInSClks[0]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 15)) + ) + ) + (net (rename sSpPeriodInSClks_10_ "sSpPeriodInSClks[10]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 5)) + ) + ) + (net (rename sSpPeriodInSClks_11_ "sSpPeriodInSClks[11]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 4)) + ) + ) + (net (rename sSpPeriodInSClks_12_ "sSpPeriodInSClks[12]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 3)) + ) + ) + (net (rename sSpPeriodInSClks_13_ "sSpPeriodInSClks[13]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 2)) + ) + ) + (net (rename sSpPeriodInSClks_14_ "sSpPeriodInSClks[14]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 1)) + ) + ) + (net (rename sSpPeriodInSClks_15_ "sSpPeriodInSClks[15]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 0)) + ) + ) + (net (rename sSpPeriodInSClks_1_ "sSpPeriodInSClks[1]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 14)) + ) + ) + (net (rename sSpPeriodInSClks_2_ "sSpPeriodInSClks[2]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 13)) + ) + ) + (net (rename sSpPeriodInSClks_3_ "sSpPeriodInSClks[3]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 12)) + ) + ) + (net (rename sSpPeriodInSClks_4_ "sSpPeriodInSClks[4]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 11)) + ) + ) + (net (rename sSpPeriodInSClks_5_ "sSpPeriodInSClks[5]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 10)) + ) + ) + (net (rename sSpPeriodInSClks_6_ "sSpPeriodInSClks[6]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 9)) + ) + ) + (net (rename sSpPeriodInSClks_7_ "sSpPeriodInSClks[7]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 8)) + ) + ) + (net (rename sSpPeriodInSClks_8_ "sSpPeriodInSClks[8]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 7)) + ) + ) + (net (rename sSpPeriodInSClks_9_ "sSpPeriodInSClks[9]") (joined + (portref Q (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member sSpPeriodInSClks 6)) + ) + ) + (net (rename sSptHighTimeInSClks_0_ "sSptHighTimeInSClks[0]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 15)) + ) + ) + (net (rename sSptHighTimeInSClks_10_ "sSptHighTimeInSClks[10]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 5)) + ) + ) + (net (rename sSptHighTimeInSClks_11_ "sSptHighTimeInSClks[11]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 4)) + ) + ) + (net (rename sSptHighTimeInSClks_12_ "sSptHighTimeInSClks[12]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 3)) + ) + ) + (net (rename sSptHighTimeInSClks_13_ "sSptHighTimeInSClks[13]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 2)) + ) + ) + (net (rename sSptHighTimeInSClks_14_ "sSptHighTimeInSClks[14]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 1)) + ) + ) + (net (rename sSptHighTimeInSClks_1_ "sSptHighTimeInSClks[1]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 14)) + ) + ) + (net (rename sSptHighTimeInSClks_2_ "sSptHighTimeInSClks[2]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 13)) + ) + ) + (net (rename sSptHighTimeInSClks_3_ "sSptHighTimeInSClks[3]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 12)) + ) + ) + (net (rename sSptHighTimeInSClks_4_ "sSptHighTimeInSClks[4]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 11)) + ) + ) + (net (rename sSptHighTimeInSClks_5_ "sSptHighTimeInSClks[5]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 10)) + ) + ) + (net (rename sSptHighTimeInSClks_6_ "sSptHighTimeInSClks[6]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 9)) + ) + ) + (net (rename sSptHighTimeInSClks_7_ "sSptHighTimeInSClks[7]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 8)) + ) + ) + (net (rename sSptHighTimeInSClks_8_ "sSptHighTimeInSClks[8]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 7)) + ) + ) + (net (rename sSptHighTimeInSClks_9_ "sSptHighTimeInSClks[9]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref (member sSptHighTimeInSClks 6)) + ) + ) + (net (rename sSptPeriodInSClks_0_ "sSptPeriodInSClks[0]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 15)) + ) + ) + (net (rename sSptPeriodInSClks_10_ "sSptPeriodInSClks[10]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 5)) + ) + ) + (net (rename sSptPeriodInSClks_11_ "sSptPeriodInSClks[11]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 4)) + ) + ) + (net (rename sSptPeriodInSClks_12_ "sSptPeriodInSClks[12]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 3)) + ) + ) + (net (rename sSptPeriodInSClks_13_ "sSptPeriodInSClks[13]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 2)) + ) + ) + (net (rename sSptPeriodInSClks_14_ "sSptPeriodInSClks[14]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 1)) + ) + ) + (net (rename sSptPeriodInSClks_15_ "sSptPeriodInSClks[15]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 0)) + ) + ) + (net (rename sSptPeriodInSClks_1_ "sSptPeriodInSClks[1]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 14)) + ) + ) + (net (rename sSptPeriodInSClks_2_ "sSptPeriodInSClks[2]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 13)) + ) + ) + (net (rename sSptPeriodInSClks_3_ "sSptPeriodInSClks[3]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 12)) + ) + ) + (net (rename sSptPeriodInSClks_4_ "sSptPeriodInSClks[4]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 11)) + ) + ) + (net (rename sSptPeriodInSClks_5_ "sSptPeriodInSClks[5]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 10)) + ) + ) + (net (rename sSptPeriodInSClks_6_ "sSptPeriodInSClks[6]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 9)) + ) + ) + (net (rename sSptPeriodInSClks_7_ "sSptPeriodInSClks[7]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 8)) + ) + ) + (net (rename sSptPeriodInSClks_8_ "sSptPeriodInSClks[8]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 7)) + ) + ) + (net (rename sSptPeriodInSClks_9_ "sSptPeriodInSClks[9]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 6)) + ) + ) + ) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design SyncRegsIfc + (cellref SyncRegsIfc (libraryref work)) + (property part (string "xc7z100ffg900-2")) + ) +) diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf Binary files differnew file mode 100644 index 000000000..9679f2c63 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd new file mode 100644 index 000000000..6535bbd04 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd @@ -0,0 +1,1147 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- This top level module orchestrates both of the TDC Cores for the RP and SP. It +-- handles PPS capture, resets, re-run logic, and PPS crossing logic. The guts of the TDC +-- are all located in the Cores. +-- +-- This file (and the Cores) follows exactly the "TDC Detail" diagram from this document: +-- //MI/RF/HW/USRP/N310/HWCode/Common/Synchronization/design/Diagrams.vsdx +-- +-- +-- +-- To control this module: +-- 0) Default values expected to be driven on the control inputs: +-- aReset <= true +-- rResetTdc <= true +-- rEnableTdc <= false +-- rReRunEnable <= false +-- rEnablePpsCrossing <= false +-- sPpsClkCrossDelayVal <= don't care +-- Prior to starting the core, the Sync Pulse counters must be loaded. Apply the +-- correct count values to rRpPeriodInRClks, etc, and then pulse the load bit for +-- each RP and SP. It is critical that this step is performed before de-asserting +-- reset. +-- +-- 1) De-assert the global reset, aReset, as well as the synchronous reset, rResetTdc, +-- after all clocks are active and stable. Wait until rResetTdcDone is de-asserted. +-- If it doesn't de-assert, then one of your clocks isn't running. +-- +-- 2) At any point after rResetTdcDone de-asserts it is safe to assert rEnableTdc. +-- The rPpsPulse input is now actively listening for PPS activity and the TDC +-- will begin on the first PPS pulse received. After a PPS is received, the +-- rPpsPulseCaptured bit will assert and will remain asserted until aReset or +-- rResetTdc is asserted. +-- +-- 3) When the TDC measurement completes, mRpOffsetDone and mSpOffsetDone will assert +-- (not necessarily at the same time). The results of the measurements will be valid +-- on mRpOffset and mSpOffset. +-- +-- 4) To cross the PPS trigger into the SampleClk domain, first write the correct delay +-- value to sPpsClkCrossDelayVal. Then (or at the same time), enable the crossing +-- logic by asserting rEnablePpsCrossing. All subsequent PPS pulses will be crossed +-- deterministically. Although not the typical use case, sPpsClkCrossDelayVal can +-- be adjusted on the fly without producing output glitches, although output pulses +-- may be skipped. +-- +-- 5) To run the measurement again, assert the rReRunEnable input and capture the new +-- offsets whenever mRpOffsetValid or mSpOffsetValid asserts. +-- +-- +-- +-- Sync Pulse = RP and SP, which are the repeated pulses that are some integer +-- divisor of the Reference and Sample clocks. RP = Reference Pulse in the +-- RefClk domain. SP = Repeated TClk pulse in the SampleClk domain. +-- +-- +-- Clock period relationship requirements to meet system concerns: +-- 1) MeasClkPeriod < 2*RefClkPeriod +-- 2) MeasClkPeriod < 4*SampleClkPeriod +-- +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity TdcTop is + generic ( + -- Determines the maximum number of bits required to create the restart + -- pulser. This value is based off of the RefClk and RePulse rates. + kRClksPerRePulsePeriodBitsMax : integer range 3 to 32 := 24; + -- Determines the maximum number of bits required to create the Gated and Freerunning + -- sync pulsers. This value is based off of the RefClk and SyncPulse rates. + kRClksPerRpPeriodBitsMax : integer range 3 to 16 := 16; + -- This value is based off of the SampleClk and SyncPulse rates. + kSClksPerSpPeriodBitsMax : integer range 3 to 16 := 16; + -- Number of MeasClk periods required to count one period of RP or SP (in bits). + kPulsePeriodCntSize : integer := 13; + -- Number of FreqRef periods to be measured (in bits). + kFreqRefPeriodsToCheckSize: integer := 17; + -- Number of Sync Pulse Periods to be timestamped (in bits). + kSyncPeriodsToStampSize : integer := 10 + ); + port ( + + -- Clocks and Resets : -------------------------------------------------------------- + -- Asynchronous global reset. + aReset : in boolean; + -- Reference Clock + RefClk : in std_logic; + -- Sample Clock + SampleClk : in std_logic; + -- Measurement Clock must run at a very specific frequency, determined by the + -- SampleClk, RefClk, and Sync Pulse rates... oh and a lot of math/luck. + MeasClk : in std_logic; + + + -- Controls and Status : ------------------------------------------------------------ + -- Soft reset for the module. Wait until rResetTdcDone asserts before de-asserting + -- the reset. + rResetTdc : in boolean; + rResetTdcDone : out boolean; + -- Once enabled, the TDC waits for the next PPS pulse to begin measurements. Leave + -- this signal asserted for the measurement duration (there is no need to de-assert + -- it unless you want to capture a different PPS edge). + rEnableTdc : in boolean; + -- Assert this bit to allow the TDC to perform repeated measurements. + rReRunEnable : in boolean; + + -- Only required to pulse 1 RefClk cycle. + rPpsPulse : in boolean; + -- Debug, held asserted when pulse is captured. + rPpsPulseCaptured : out boolean; + + -- Programmable value for delaying the RP and SP pulsers from when the Restart + -- Pulser begins. + rPulserEnableDelayVal : in unsigned(3 downto 0); + + + -- Crossing PPS into Sample Clock : ------------------------------------------------- + -- Enable crossing rPpsPulse into SampleClk domain. This should remain de-asserted + -- until the TDC measurements are complete and sPpsClkCrossDelayVal is written. + rEnablePpsCrossing : in boolean; + -- Programmable delay value for crossing clock domains. This is used to compensate + -- for differences in sSP pulses across modules. This value is typically set once + -- after running initial synchronization. + sPpsClkCrossDelayVal : in unsigned(3 downto 0); + -- PPS pulse output on the SampleClk domain. + sPpsPulse : out boolean; + + + -- FTDC Measurement Results : ------------------------------------------------------- + -- Final FTDC measurements in MeasClk ticks. Done will assert when *Offset + -- becomes valid and will remain asserted until aReset or rResetTdc asserts. + -- FXP<+40,13> where kPulsePeriodCntSize is the number of integer bits. + mRpOffset : out unsigned(kPulsePeriodCntSize+ + kSyncPeriodsToStampSize+ + kFreqRefPeriodsToCheckSize-1 downto 0); + mSpOffset : out unsigned(kPulsePeriodCntSize+ + kSyncPeriodsToStampSize+ + kFreqRefPeriodsToCheckSize-1 downto 0); + mOffsetsDone : out boolean; + mOffsetsValid : out boolean; + + + -- Setup for Pulsers : -------------------------------------------------------------- + -- Only load these counts when rResetTdc is asserted and rEnableTdc is de-asserted!!! + -- If both of the above conditions are met, load the counts by pulsing Load + -- when the counts are valid. It is not necessary to keep the count values valid + -- after pulsing Load. + rLoadRePulseCounts : in boolean; -- RePulse + rRePulsePeriodInRClks : in unsigned(kRClksPerRePulsePeriodBitsMax - 1 downto 0); + rRePulseHighTimeInRClks : in unsigned(kRClksPerRePulsePeriodBitsMax - 1 downto 0); + rLoadRpCounts : in boolean; -- RP + rRpPeriodInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rRpHighTimeInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rLoadRptCounts : in boolean; -- RP-transfer + rRptPeriodInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rRptHighTimeInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + sLoadSpCounts : in boolean; -- SP + sSpPeriodInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sSpHighTimeInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sLoadSptCounts : in boolean; -- SP-transfer + sSptPeriodInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sSptHighTimeInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + + + -- Sync Pulse Outputs : ------------------------------------------------------------- + -- The repeating pulses can be useful for many things, including passing triggers. + -- The rising edges will always have a fixed (but unknown) phase relationship to one + -- another. This fixed phase relationship is valid across daughterboards and all + -- modules using the same Reference Clock and Sample Clock rates and sources. + rRpTransfer : out boolean; + sSpTransfer : out boolean; + + -- Pin bouncers out and in. Must go to unused and unconnected pins on the FPGA! + rGatedPulseToPin : inout std_logic; + sGatedPulseToPin : inout std_logic + ); +end TdcTop; + + +architecture struct of TdcTop is + + component TdcCore + generic ( + kSourceClksPerPulseMaxBits : integer range 3 to 16 := 16; + kPulsePeriodCntSize : integer := 13; + kFreqRefPeriodsToCheckSize : integer := 17; + kSyncPeriodsToStampSize : integer := 10); + port ( + aReset : in boolean; + MeasClk : in std_logic; + mResetPeriodMeas : in boolean; + mPeriodMeasDone : out boolean; + mResetTdcMeas : in boolean; + mRunTdcMeas : in boolean; + mGatedPulse : out boolean; + mAvgOffset : out unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + mAvgOffsetDone : out boolean; + mAvgOffsetValid : out boolean; + SourceClk : in std_logic; + sResetTdc : in boolean; + sSyncPulseLoadCnt : in boolean; + sSyncPulsePeriod : in unsigned(kSourceClksPerPulseMaxBits-1 downto 0); + sSyncPulseHighTime : in unsigned(kSourceClksPerPulseMaxBits-1 downto 0); + sSyncPulseEnable : in boolean; + sGatedPulse : out boolean; + sGatedPulseToPin : inout std_logic); + end component; + + --vhook_sigstart + signal mRP: boolean; + signal mRpOffsetDoneLcl: boolean; + signal mRpOffsetValidLcl: boolean; + signal mRunTdc: boolean; + signal mSP: boolean; + signal mSpOffsetDoneLcl: boolean; + signal mSpOffsetValidLcl: boolean; + signal rCrossTrigRFI: boolean; + signal rGatedCptrPulseIn: boolean; + signal rRePulse: boolean; + signal rRePulseEnable: boolean; + signal rRpEnable: boolean; + signal rRptPulse: boolean; + signal sSpEnable: boolean; + signal sSptPulse: boolean; + --vhook_sigend + + signal sSpEnable_ms : boolean; + + -- Delay chain for enables. + constant kDelaySizeForRpEnable : integer := 15; + constant kAddtlDelayForSpEnable : integer := 3; + signal rSyncPulseEnableDly : + std_logic_vector(kDelaySizeForRpEnable+ + kAddtlDelayForSpEnable-1 downto 0) := (others => '0'); + -- Adding kAddtlDelayForSpEnable stages, so this vector needs to handle one extra + -- bit of range (hence no -1 downto 0). + signal rSyncPulseEnableDlyVal : unsigned(rPulserEnableDelayVal'length downto 0); + + signal rResetTdcFlop_ms, rResetTdcFlop, + rResetTdcDone_ms, + rSpEnable, + mRunTdcEnable_ms, mRunTdcEnable, + mRunTdcEnableDly, mRunTdcEnableRe, + mResetTdc_ms, mResetTdc, + sResetTdc_ms, sResetTdc, + mRpValidStored, mSpValidStored, + mOffsetsValidLcl, + rPpsPulseDly, rPpsPulseRe, + mReRunEnable_ms, mReRunEnable : boolean; + + signal rPpsCaptured : std_logic; + + type EnableFsmState_t is (Disabled, WaitForRunComplete, ReRuns); + signal mEnableState : EnableFsmState_t; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sSpEnable_ms : signal is "true"; + attribute ASYNC_REG of sSpEnable : signal is "true"; + attribute ASYNC_REG of rResetTdcFlop_ms : signal is "true"; + attribute ASYNC_REG of rResetTdcFlop : signal is "true"; + attribute ASYNC_REG of rResetTdcDone_ms : signal is "true"; + attribute ASYNC_REG of rResetTdcDone : signal is "true"; + attribute ASYNC_REG of mRunTdcEnable_ms : signal is "true"; + attribute ASYNC_REG of mRunTdcEnable : signal is "true"; + attribute ASYNC_REG of mResetTdc_ms : signal is "true"; + attribute ASYNC_REG of mResetTdc : signal is "true"; + attribute ASYNC_REG of sResetTdc_ms : signal is "true"; + attribute ASYNC_REG of sResetTdc : signal is "true"; + attribute ASYNC_REG of mReRunEnable_ms : signal is "true"; + attribute ASYNC_REG of mReRunEnable : signal is "true"; + +begin + + + -- Generate Resets : ------------------------------------------------------------------ + -- Double-sync the reset to the MeasClk domain and then back to the RefClk domain to + -- prove it made it all the way into the TDC. Also move it into the SampleClk domain. + -- ------------------------------------------------------------------------------------ + GenResets : process(aReset, RefClk) + begin + if aReset then + rResetTdcFlop_ms <= true; + rResetTdcFlop <= true; + rResetTdcDone_ms <= true; + rResetTdcDone <= true; + elsif rising_edge(RefClk) then + -- Run this through a double-sync in case the user defaults it to false, which + -- could cause rResetTdcFlop_ms to go meta-stable. + rResetTdcFlop_ms <= rResetTdc; + rResetTdcFlop <= rResetTdcFlop_ms; + -- Second double-sync to move the reset from the MeasClk domain back to RefClk. + rResetTdcDone_ms <= mResetTdc; + rResetTdcDone <= rResetTdcDone_ms; + end if; + end process; + + GenResetsMeasClk : process(aReset, MeasClk) + begin + if aReset then + mResetTdc_ms <= true; + mResetTdc <= true; + elsif rising_edge(MeasClk) then + -- Move the reset from the RefClk to the MeasClk domain. + mResetTdc_ms <= rResetTdcFlop; + mResetTdc <= mResetTdc_ms; + end if; + end process; + + GenResetsSampleClk : process(aReset, SampleClk) + begin + if aReset then + sResetTdc_ms <= true; + sResetTdc <= true; + elsif rising_edge(SampleClk) then + -- Move the reset from the RefClk to the SampleClk domain. + sResetTdc_ms <= rResetTdcFlop; + sResetTdc <= sResetTdc_ms; + end if; + end process; + + + -- Generate Enables for TDCs : -------------------------------------------------------- + -- When the TDC is enabled by asserting rEnableTdc, we start "listening" for a PPS + -- rising edge to occur. We capture the first edge we see and then keep the all the + -- enables asserted until the TDC is disabled. + -- ------------------------------------------------------------------------------------ + rPpsPulseRe <= rPpsPulse and not rPpsPulseDly; + + EnableTdc : process(aReset, RefClk) + begin + if aReset then + rPpsPulseDly <= false; + rPpsCaptured <= '0'; + rSyncPulseEnableDly <= (others => '0'); + elsif rising_edge(RefClk) then + -- RE detector for PPS to ONLY trigger on the edge and not accidentally half + -- way through the high time. + rPpsPulseDly <= rPpsPulse; + -- When the TDC is enabled we capture the first PPS. This starts the Sync Pulses + -- (RP / SP) as well as enables the TDC measurement for capturing edges. Note + -- that this is independent from any synchronous reset such that we can control + -- the PPS capture and the edge capture independently. + if rEnableTdc then + if rPpsPulseRe then + rPpsCaptured <= '1'; + end if; + else + rPpsCaptured <= '0'; + rSyncPulseEnableDly <= (others => '0'); + end if; + + -- Delay chain for the enable bits. Shift left low to high. + rSyncPulseEnableDly <= + rSyncPulseEnableDly(rSyncPulseEnableDly'high-1 downto 0) & rPpsCaptured; + end if; + end process; + + rSyncPulseEnableDlyVal <= resize(rPulserEnableDelayVal, rSyncPulseEnableDlyVal'length); + + -- Enables for the RePulse/RP/SP. The RePulse enable must be asserted two cycles + -- before the other enables to allow the TDC to start running before the RP/SP begin. + rRePulseEnable <= rPpsCaptured = '1'; -- no delay + rRpEnable <= rSyncPulseEnableDly(to_integer(rSyncPulseEnableDlyVal)) = '1'; + rSpEnable <= rSyncPulseEnableDly(to_integer(rSyncPulseEnableDlyVal)+kAddtlDelayForSpEnable-1) = '1'; + + -- Local to output. + rPpsPulseCaptured <= rPpsCaptured = '1'; + + -- Sync rSpEnable to the SampleClk now... based on the "TDC 2.0" diagram. + SyncEnableToSampleClk : process(aReset, SampleClk) + begin + if aReset then + sSpEnable_ms <= false; + sSpEnable <= false; + elsif rising_edge(SampleClk) then + sSpEnable_ms <= rSpEnable; + sSpEnable <= sSpEnable_ms; + end if; + end process; + + --vhook_e Pulser ReRunPulser + --vhook_a kClksPerPulseMaxBits kRClksPerRePulsePeriodBitsMax + --vhook_a Clk RefClk + --vhook_a cLoadLimits rLoadRePulseCounts + --vhook_a cPeriod rRePulsePeriodInRClks + --vhook_a cHighTime rRePulseHighTimeInRClks + --vhook_a cEnablePulse rRePulseEnable + --vhook_a cPulse rRePulse + ReRunPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kRClksPerRePulsePeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => rLoadRePulseCounts, --in boolean + cPeriod => rRePulsePeriodInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => rRePulseHighTimeInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rRePulseEnable, --in boolean + cPulse => rRePulse); --out boolean + + mRunTdcEnableRe <= mRunTdcEnable and not mRunTdcEnableDly; + + -- FSM to generate the master Run signal, as well as the repeat run. + SyncEnableToMeasClk : process(aReset, MeasClk) + begin + if aReset then + mRunTdcEnable_ms <= false; + mRunTdcEnable <= false; + mReRunEnable_ms <= false; + mReRunEnable <= false; + mRunTdcEnableDly <= false; + mRunTdc <= false; + mEnableState <= Disabled; + elsif rising_edge(MeasClk) then + -- rRePulse is many, many MeasClk cycles high/low, so this is safe to double-sync. + mRunTdcEnable_ms <= rRePulse; + mRunTdcEnable <= mRunTdcEnable_ms; + mReRunEnable_ms <= rReRunEnable; + mReRunEnable <= mReRunEnable_ms; + + mRunTdcEnableDly <= mRunTdcEnable; + + -- STATE MACHINE STARTUP !!! ------------------------------------------------------ + -- This state machine starts safely because it cannot change state until + -- mRunTdcEnable is asserted, which cannot happen until several cycles after + -- aReset de-assertion due to the double-synchronizer from the RefClk domain. + -- -------------------------------------------------------------------------------- + -- De-assert strobe. + mRunTdc <= false; + + case mEnableState is + -- Transition to WaitForRunComplete when the TDC is enabled. Pulse mRunTdc here, + -- and then wait for it to complete in WaitForRunComplete. + when Disabled => + if mRunTdcEnableRe then + mRunTdc <= true; + mEnableState <= WaitForRunComplete; + end if; + + -- The TDC measurement is complete when both offsets are valid. Go to the re-run + -- state regardless of whether re-runs are enabled. If they aren't we just sit + -- there and wait for more instructions... + when WaitForRunComplete => + if mOffsetsValidLcl then + mEnableState <= ReRuns; + end if; + + -- Only pulse mRunTdc again if re-runs are enabled and the rising edge of + -- the enable signal occurs. This guarantees our RP/SP have the correct phase + -- relationship every time the TDC is run. + when ReRuns => + if mReRunEnable and mRunTdcEnableRe then + mRunTdc <= true; + mEnableState <= WaitForRunComplete; + end if; + + when others => + mEnableState <= Disabled; + end case; + + -- Synchronous reset for FSM. + if mResetTdc then + mEnableState <= Disabled; + mRunTdc <= false; + end if; + + end if; + end process; + + + + -- Generate Output Valid Signals : ---------------------------------------------------- + -- Depending on how fast SW can read the measurements (and in what order they read) + -- the readings could be out of sync with one another. This section conditions the + -- output valid signals from each core and asserts a single output valid pulse after + -- BOTH valids have asserted. It is agnostic to the order in which the valids assert. + -- It creates a delay in the output valid assertion. Minimal delay is one MeasClk cycle + -- if the core valids assert together. Worst-case delay is two MeasClk cycles after + -- the latter of the two valids asserts. This is acceptable delay because the core + -- cannot be re-run until both valids have asserted (mOffsetsValidLcl is fed back into + -- the ReRun FSM above). + -- ------------------------------------------------------------------------------------ + ConditionDataValidProc : process(aReset, MeasClk) is + begin + if aReset then + mOffsetsValidLcl <= false; + mRpValidStored <= false; + mSpValidStored <= false; + elsif rising_edge(MeasClk) then + -- Reset the strobe signals. + mOffsetsValidLcl <= false; + + -- First, we're sensitive to the TDC sync reset signal. + if mResetTdc then + mOffsetsValidLcl <= false; + mRpValidStored <= false; + mSpValidStored <= false; + -- Case 1: Both Valid signals pulse at the same time. + -- Case 4: Both Valid signals have been stored independently. Yes, this incurs + -- a one-cycle delay in the output valid (from when the second one asserts) + -- but it makes for cleaner code and is safe because by design because the + -- valid signals cannot assert again for a longggg time. + elsif (mRpOffsetValidLcl and mSpOffsetValidLcl) or + (mRpValidStored and mSpValidStored) then + mOffsetsValidLcl <= true; + mRpValidStored <= false; + mSpValidStored <= false; + -- Case 2: RP Valid pulses alone. + elsif mRpOffsetValidLcl then + mRpValidStored <= true; + -- Case 3: SP Valid pulses alone. + elsif mSpOffsetValidLcl then + mSpValidStored <= true; + end if; + end if; + end process; + + -- Local to output. + mOffsetsValid <= mOffsetsValidLcl; + -- Only assert done with both cores are done. + mOffsetsDone <= mRpOffsetDoneLcl and mSpOffsetDoneLcl; + + + + -- Reference Clock TDC (RP) : --------------------------------------------------------- + -- mRP is only used for testbenching purposes, so ignore vhook warnings. + --vhook_nowarn mRP + -- ------------------------------------------------------------------------------------ + + --vhook TdcCore RpTdc + --vhook_g kSourceClksPerPulseMaxBits kRClksPerRpPeriodBitsMax + --vhook_a mResetPeriodMeas mResetTdc + --vhook_a mResetTdcMeas mResetTdc + --vhook_a mPeriodMeasDone open + --vhook_a mRunTdcMeas mRunTdc + --vhook_a mGatedPulse mRP + --vhook_a mAvgOffset mRpOffset + --vhook_a mAvgOffsetDone mRpOffsetDoneLcl + --vhook_a mAvgOffsetValid mRpOffsetValidLcl + --vhook_a SourceClk RefClk + --vhook_a sResetTdc rResetTdcFlop + --vhook_a sSyncPulseLoadCnt rLoadRpCounts + --vhook_a sSyncPulsePeriod rRpPeriodInRClks + --vhook_a sSyncPulseHighTime rRpHighTimeInRClks + --vhook_a sSyncPulseEnable rRpEnable + --vhook_a sGatedPulse open + --vhook_a {^sGated(.*)} rGated$1 + RpTdc: TdcCore + generic map ( + kSourceClksPerPulseMaxBits => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + MeasClk => MeasClk, --in std_logic + mResetPeriodMeas => mResetTdc, --in boolean + mPeriodMeasDone => open, --out boolean + mResetTdcMeas => mResetTdc, --in boolean + mRunTdcMeas => mRunTdc, --in boolean + mGatedPulse => mRP, --out boolean + mAvgOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mAvgOffsetDone => mRpOffsetDoneLcl, --out boolean + mAvgOffsetValid => mRpOffsetValidLcl, --out boolean + SourceClk => RefClk, --in std_logic + sResetTdc => rResetTdcFlop, --in boolean + sSyncPulseLoadCnt => rLoadRpCounts, --in boolean + sSyncPulsePeriod => rRpPeriodInRClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseHighTime => rRpHighTimeInRClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseEnable => rRpEnable, --in boolean + sGatedPulse => open, --out boolean + sGatedPulseToPin => rGatedPulseToPin); --inout std_logic + + --vhook_e Pulser RpTransferPulse + --vhook_a kClksPerPulseMaxBits kRClksPerRpPeriodBitsMax + --vhook_a Clk RefClk + --vhook_a cLoadLimits rLoadRptCounts + --vhook_a cPeriod rRptPeriodInRClks + --vhook_a cHighTime rRptHighTimeInRClks + --vhook_a cEnablePulse rRpEnable + --vhook_a cPulse rRptPulse + RpTransferPulse: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kRClksPerRpPeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => rLoadRptCounts, --in boolean + cPeriod => rRptPeriodInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => rRptHighTimeInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rRpEnable, --in boolean + cPulse => rRptPulse); --out boolean + + -- Local to output + rRpTransfer <= rRptPulse; + + + -- Sample Clock TDC (SP) : ------------------------------------------------------------ + -- mSP is only used for testbenching purposes, so ignore vhook warnings. + --vhook_nowarn mSP + -- ------------------------------------------------------------------------------------ + + --vhook TdcCore SpTdc + --vhook_g kSourceClksPerPulseMaxBits kSClksPerSpPeriodBitsMax + --vhook_a mResetPeriodMeas mResetTdc + --vhook_a mResetTdcMeas mResetTdc + --vhook_a mPeriodMeasDone open + --vhook_a mRunTdcMeas mRunTdc + --vhook_a mGatedPulse mSP + --vhook_a mAvgOffset mSpOffset + --vhook_a mAvgOffsetDone mSpOffsetDoneLcl + --vhook_a mAvgOffsetValid mSpOffsetValidLcl + --vhook_a SourceClk SampleClk + --vhook_a sResetTdc sResetTdc + --vhook_a sSyncPulseLoadCnt sLoadSpCounts + --vhook_a sSyncPulsePeriod sSpPeriodInSClks + --vhook_a sSyncPulseHighTime sSpHighTimeInSClks + --vhook_a sSyncPulseEnable sSpEnable + --vhook_a sGatedPulse open + --vhook_a {^sGated(.*)} sGated$1 + SpTdc: TdcCore + generic map ( + kSourceClksPerPulseMaxBits => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + MeasClk => MeasClk, --in std_logic + mResetPeriodMeas => mResetTdc, --in boolean + mPeriodMeasDone => open, --out boolean + mResetTdcMeas => mResetTdc, --in boolean + mRunTdcMeas => mRunTdc, --in boolean + mGatedPulse => mSP, --out boolean + mAvgOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mAvgOffsetDone => mSpOffsetDoneLcl, --out boolean + mAvgOffsetValid => mSpOffsetValidLcl, --out boolean + SourceClk => SampleClk, --in std_logic + sResetTdc => sResetTdc, --in boolean + sSyncPulseLoadCnt => sLoadSpCounts, --in boolean + sSyncPulsePeriod => sSpPeriodInSClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseHighTime => sSpHighTimeInSClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseEnable => sSpEnable, --in boolean + sGatedPulse => open, --out boolean + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + --vhook_e Pulser SpTransferPulse + --vhook_a kClksPerPulseMaxBits kSClksPerSpPeriodBitsMax + --vhook_a Clk SampleClk + --vhook_a cLoadLimits sLoadSptCounts + --vhook_a cPeriod sSptPeriodInSClks + --vhook_a cHighTime sSptHighTimeInSClks + --vhook_a cEnablePulse sSpEnable + --vhook_a cPulse sSptPulse + SpTransferPulse: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kSClksPerSpPeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => SampleClk, --in std_logic + cLoadLimits => sLoadSptCounts, --in boolean + cPeriod => sSptPeriodInSClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => sSptHighTimeInSClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => sSpEnable, --in boolean + cPulse => sSptPulse); --out boolean + + -- Local to output + sSpTransfer <= sSptPulse; + + + -- Cross PPS to SampleClk : ---------------------------------------------------------- + -- Cross it safely and with deterministic delay. + -- ------------------------------------------------------------------------------------ + + -- Keep the module from over-pulsing itself by gating the input with the RFI signal, + -- although at 1 Hz, this module should never run into the RFI de-asserted case + -- by design. + rGatedCptrPulseIn <= rCrossTrigRFI and rPpsPulseRe; + + --vhook_e CrossTrigger CrossCptrPulse + --vhook_a rRP rRptPulse + --vhook_a rReadyForInput rCrossTrigRFI + --vhook_a rEnableTrigger rEnablePpsCrossing + --vhook_a rTriggerIn rGatedCptrPulseIn + --vhook_a sSP sSptPulse + --vhook_a sElasticBufferPtr sPpsClkCrossDelayVal + --vhook_a sTriggerOut sPpsPulse + CrossCptrPulse: entity work.CrossTrigger (rtl) + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + rRP => rRptPulse, --in boolean + rReadyForInput => rCrossTrigRFI, --out boolean + rEnableTrigger => rEnablePpsCrossing, --in boolean + rTriggerIn => rGatedCptrPulseIn, --in boolean + SampleClk => SampleClk, --in std_logic + sSP => sSptPulse, --in boolean + sElasticBufferPtr => sPpsClkCrossDelayVal, --in unsigned(3:0) + sTriggerOut => sPpsPulse); --out boolean + + +end struct; + + + + + + + +-------------------------------------------------------------------------------- +-- Testbench for TdcTop +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity tb_TdcTop is end tb_TdcTop; + +architecture test of tb_TdcTop is + + -- Constants for the clock periods. + constant kSPer : time := 8.000 ns; -- 125.00 MHz + constant kMPer : time := 5.050 ns; -- 198.00 MHz + constant kRPer : time := 100.000 ns; -- 10.00 MHz + + constant kRClksPerRePulsePeriodBitsMax : integer := 24; + constant kRClksPerRpPeriodBitsMax : integer := 16; + constant kSClksPerSpPeriodBitsMax : integer := 16; + + -- Constants for the RP/SP pulses, based on the clock frequencies above. The periods + -- should all divide into one another without remainders, so this is safe to do... + -- High time is 50% duty cycle, or close to it if the period isn't a round number. + constant kRpPeriod : time := 1000 ns; + constant kRpPeriodInRClks : integer := kRpPeriod/kRPer; + constant kRpHighTimeInRClks : integer := integer(floor(real(kRpPeriodInRClks)/2.0)); + constant kRptPeriod : time := 25000 ns; + constant kRptPeriodInRClks : integer := kRptPeriod/kRPer; + constant kRptHighTimeInRClks : integer := integer(floor(real(kRptPeriodInRClks)/2.0)); + constant kSpPeriod : time := 800 ns; + constant kSpPeriodInSClks : integer := kSpPeriod/kSPer; + constant kSpHighTimeInSClks : integer := integer(floor(real(kSpPeriodInSClks)/2.0)); + constant kSptPeriod : time := 25000 ns; + constant kSptPeriodInSClks : integer := kSptPeriod/kSPer; + constant kSptHighTimeInSClks : integer := integer(floor(real(kSptPeriodInSClks)/2.0)); + constant kRePulsePeriod : time := 2.500 ms; + constant kRePulsePeriodInRClks : integer := kRePulsePeriod/kRPer; + constant kRePulseHighTimeInRClks : integer := integer(floor(real(kRePulsePeriodInRClks)/2.0)); + + -- This doesn't come out to a nice number (or shouldn't), but that's ok. Round up. + constant kMeasClksPerRp : integer := kRpPeriod/kMPer+1; + + -- Inputs to DUT + constant kPulsePeriodCntSize : integer := integer(ceil(log2(real(kMeasClksPerRp)))); + constant kFreqRefPeriodsToCheckSize: integer := 12; -- usually 17, but to save run time... + constant kSyncPeriodsToStampSize : integer := 10; + + constant kMeasurementTimeout : time := + kMPer*(kMeasClksPerRp*(2**kSyncPeriodsToStampSize) + + 40*(2**kSyncPeriodsToStampSize) + + kMeasClksPerRp*(2**kFreqRefPeriodsToCheckSize) + ); + + --vhook_sigstart + signal aReset: boolean; + signal MeasClk: std_logic := '0'; + signal mOffsetsDone: boolean; + signal mOffsetsValid: boolean; + signal mRpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal mSpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal RefClk: std_logic := '0'; + signal rEnablePpsCrossing: boolean; + signal rEnableTdc: boolean; + signal rGatedPulseToPin: std_logic; + signal rLoadRePulseCounts: boolean; + signal rLoadRpCounts: boolean; + signal rLoadRptCounts: boolean; + signal rPpsPulse: boolean; + signal rPpsPulseCaptured: boolean; + signal rPulserEnableDelayVal: unsigned(3 downto 0); + signal rReRunEnable: boolean; + signal rResetTdc: boolean; + signal rResetTdcDone: boolean; + signal rRpTransfer: boolean; + signal SampleClk: std_logic := '0'; + signal sGatedPulseToPin: std_logic; + signal sLoadSpCounts: boolean; + signal sLoadSptCounts: boolean; + signal sPpsClkCrossDelayVal: unsigned(3 downto 0); + signal sPpsPulse: boolean; + signal sSpTransfer: boolean; + --vhook_sigend + + signal StopSim : boolean; + signal EnableOutputChecks : boolean := true; + + signal ExpectedRpOutput, + ExpectedFinalMeas, + ExpectedSpOutput : real := 0.0; + + alias mRunTdc is <<signal .tb_TdcTop.dutx.mRunTdc : boolean>>; + alias mSP is <<signal .tb_TdcTop.dutx.mSP : boolean>>; + alias mRP is <<signal .tb_TdcTop.dutx.mRP : boolean>>; + + procedure ClkWait( + signal Clk : in std_logic; + X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + + function OffsetToReal (Offset : unsigned) return real is + variable TempVar : real := 0.0; + begin + TempVar := + real(to_integer( + Offset(Offset'high downto kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize))) + + real(to_integer( + Offset(kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize-1 downto 0)))* + real(2.0**(-(kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize))); + return TempVar; + end OffsetToReal; + +begin + + SampleClk <= not SampleClk after kSPer/2 when not StopSim else '0'; + RefClk <= not RefClk after kRPer/2 when not StopSim else '0'; + MeasClk <= not MeasClk after kMPer/2 when not StopSim else '0'; + + + main: process + begin + -- Defaults, per instructions in Purpose + sPpsClkCrossDelayVal <= to_unsigned(0, sPpsClkCrossDelayVal'length); + rPulserEnableDelayVal <= to_unsigned(1, rPulserEnableDelayVal'length); + rResetTdc <= true; + rEnableTdc <= false; + rReRunEnable <= false; + rEnablePpsCrossing <= false; + rPpsPulse <= false; + rLoadRePulseCounts <= false; + rLoadRpCounts <= false; + rLoadRptCounts <= false; + sLoadSpCounts <= false; + sLoadSptCounts <= false; + + aReset <= true, false after kRPer*4; + ClkWait(RefClk,10); + + -- Step 0 : ------------------------------------------------------------------------- + -- Prior to de-asserting reset, we need to load the counters, so pulse the loads. + ClkWait(RefClk); + rLoadRePulseCounts <= true; + rLoadRpCounts <= true; + rLoadRptCounts <= true; + ClkWait(RefClk); + rLoadRePulseCounts <= false; + rLoadRpCounts <= false; + rLoadRptCounts <= false; + ClkWait(SampleClk); + sLoadSpCounts <= true; + sLoadSptCounts <= true; + ClkWait(SampleClk); + sLoadSpCounts <= false; + sLoadSptCounts <= false; + + + -- Step 1 : ------------------------------------------------------------------------- + report "De-asserting Synchronous Reset..." severity note; + ClkWait(RefClk); + rResetTdc <= false; + wait until not rResetTdcDone for (kRPer*4)+(kMPer*2); + assert not rResetTdcDone + report "rRestTdcDone didn't de-assert in time" + severity error; + + + -- Step 2 : ------------------------------------------------------------------------- + report "Enabling TDC Measurement & Capturing PPS..." severity note; + rEnableTdc <= true; + ClkWait(RefClk,5); + + -- Trigger a PPS one-cycle pulse. + rPpsPulse <= true; + ClkWait(RefClk); + rPpsPulse <= false; + ClkWait(RefClk); + assert rPpsPulseCaptured report "PPS not captured" severity error; + + + -- Step 3 : ------------------------------------------------------------------------- + report "Waiting for Measurements to Complete..." severity note; + wait until mOffsetsDone for kMeasurementTimeout; + assert mOffsetsDone + report "Offset measurements not completed within timeout" + severity error; + + -- Offset values checked below in CheckOutput. + + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + + + -- Step 4 : ------------------------------------------------------------------------- + -- Trigger another PPS one-cycle pulse to watch it all cross over correctly. + -- Issue the trigger around where a real PPS pulse will come (RE of RP). + -- First, set the programmable delay sPpsClkCrossDelayVal. + ClkWait(SampleClk); + sPpsClkCrossDelayVal <= to_unsigned(4, sPpsClkCrossDelayVal'length); + ClkWait(RefClk); + rEnablePpsCrossing <= true; + wait until rRpTransfer and not rRpTransfer'delayed; + rPpsPulse <= true; + ClkWait(RefClk); + rPpsPulse <= false; + ClkWait(RefClk); + + -- We expect the PPS output pulse to arrive after FE and RE of sSP have passed, + -- and then a few extra cycles of SampleClk delay on there as well. + wait until (not sSpTransfer) and ( sSpTransfer'delayed); -- FE + wait until ( sSpTransfer) and (not sSpTransfer'delayed); -- RE + ClkWait(SampleClk, 2 + to_integer(sPpsClkCrossDelayVal)); + -- Check on falling edge of clock. + wait until falling_edge(SampleClk); + assert sPpsPulse and not sPpsPulse'delayed(kSPer) report "sPpsPulse did not assert"; + wait until falling_edge(SampleClk); + assert not sPpsPulse report "sPpsPulse did not pulse correctly"; + + + -- Step 5 : ------------------------------------------------------------------------- + report "Repeating TDC Measurement..." severity note; + ClkWait(RefClk); + rReRunEnable <= true; + + -- Now wait for the measurement to complete. + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + + -- Offset values checked below in CheckOutput. + + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + + ClkWait(MeasClk,100); + + + -- Let it run for a while : --------------------------------------------------------- + for i in 0 to 9 loop + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + end loop; + + + -- And stop it : -------------------------------------------------------------------- + report "Stopping Repeating TDC Measurements..." severity note; + ClkWait(RefClk); + rReRunEnable <= false; + -- Wait to make sure it doesn't keep going. + wait until mOffsetsValid + for 2*(kMPer*(kMeasClksPerRp*(2**kSyncPeriodsToStampSize) + 40*(2**kSyncPeriodsToStampSize))); + assert not mOffsetsValid; + + + + -- Let it run for a while : --------------------------------------------------------- + report "Starting again Repeating TDC Measurements..." severity note; + ClkWait(RefClk); + rReRunEnable <= true; + for i in 0 to 2 loop + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + end loop; + + + StopSim <= true; + wait; + end process; + + + ExpectedFinalMeasGen : process + variable StartTime : time := 0 ns; + begin + wait until rPpsPulse; + wait until rRpTransfer; + StartTime := now; + wait until sSpTransfer; + ExpectedFinalMeas <= real((now - StartTime)/1 ps)/real((kSPer/1 ps)); + wait until rResetTdc; + end process; + + + ExpectedRpOutputGen : process + variable StartTime : time := 0 ns; + begin + wait until mRunTdc; + StartTime := now; + wait until mRP; + ExpectedRpOutput <= real((now - StartTime)/1 ps)/real((kMPer/1 ps)); + wait until mOffsetsValid; + end process; + + ExpectedSpOutputGen : process + variable StartTime : time := 0 ns; + begin + wait until mRunTdc; + StartTime := now; + wait until mSP; + ExpectedSpOutput <= real((now - StartTime)/1 ps)/real((kMPer/1 ps)); + wait until mOffsetsValid; + end process; + + CheckOutput : process(MeasClk) + begin + if falling_edge(MeasClk) then + if EnableOutputChecks then + + if mOffsetsValid then + assert (OffsetToReal(mRpOffset) < ExpectedRpOutput + 1.0) and + (OffsetToReal(mRpOffset) > ExpectedRpOutput - 1.0) + report "Mismatch between mRpOffset and expected!" & LF & + "Actual: " & real'image(OffsetToReal(mRpOffset)) & LF & + "Expect: " & real'image(ExpectedRpOutput) + severity error; + assert (OffsetToReal(mSpOffset) < ExpectedSpOutput + 1.0) and + (OffsetToReal(mSpOffset) > ExpectedSpOutput - 1.0) + report "Mismatch between mSpOffset and expected!" & LF & + "Actual: " & real'image(OffsetToReal(mSpOffset)) & LF & + "Expect: " & real'image(ExpectedSpOutput) + severity error; + end if; + end if; + end if; + end process; + + + --vhook_e TdcTop dutx + --vhook_a rRpPeriodInRClks to_unsigned(kRpPeriodInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a rRpHighTimeInRClks to_unsigned(kRpHighTimeInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a sSpPeriodInSClks to_unsigned(kSpPeriodInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a sSpHighTimeInSClks to_unsigned(kSpHighTimeInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a rRptPeriodInRClks to_unsigned(kRptPeriodInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a rRptHighTimeInRClks to_unsigned(kRptHighTimeInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a sSptPeriodInSClks to_unsigned(kSptPeriodInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a sSptHighTimeInSClks to_unsigned(kSptHighTimeInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a rRePulsePeriodInRClks to_unsigned(kRePulsePeriodInRClks, kRClksPerRePulsePeriodBitsMax) + --vhook_a rRePulseHighTimeInRClks to_unsigned(kRePulseHighTimeInRClks, kRClksPerRePulsePeriodBitsMax) + dutx: entity work.TdcTop (struct) + generic map ( + kRClksPerRePulsePeriodBitsMax => kRClksPerRePulsePeriodBitsMax, --integer range 3:32 :=24 + kRClksPerRpPeriodBitsMax => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kSClksPerSpPeriodBitsMax => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + rResetTdc => rResetTdc, --in boolean + rResetTdcDone => rResetTdcDone, --out boolean + rEnableTdc => rEnableTdc, --in boolean + rReRunEnable => rReRunEnable, --in boolean + rPpsPulse => rPpsPulse, --in boolean + rPpsPulseCaptured => rPpsPulseCaptured, --out boolean + rPulserEnableDelayVal => rPulserEnableDelayVal, --in unsigned(3:0) + rEnablePpsCrossing => rEnablePpsCrossing, --in boolean + sPpsClkCrossDelayVal => sPpsClkCrossDelayVal, --in unsigned(3:0) + sPpsPulse => sPpsPulse, --out boolean + mRpOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mSpOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mOffsetsDone => mOffsetsDone, --out boolean + mOffsetsValid => mOffsetsValid, --out boolean + rLoadRePulseCounts => rLoadRePulseCounts, --in boolean + rRePulsePeriodInRClks => to_unsigned(kRePulsePeriodInRClks, kRClksPerRePulsePeriodBitsMax), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rRePulseHighTimeInRClks => to_unsigned(kRePulseHighTimeInRClks, kRClksPerRePulsePeriodBitsMax), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rLoadRpCounts => rLoadRpCounts, --in boolean + rRpPeriodInRClks => to_unsigned(kRpPeriodInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRpHighTimeInRClks => to_unsigned(kRpHighTimeInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rLoadRptCounts => rLoadRptCounts, --in boolean + rRptPeriodInRClks => to_unsigned(kRptPeriodInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRptHighTimeInRClks => to_unsigned(kRptHighTimeInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + sLoadSpCounts => sLoadSpCounts, --in boolean + sSpPeriodInSClks => to_unsigned(kSpPeriodInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSpHighTimeInSClks => to_unsigned(kSpHighTimeInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sLoadSptCounts => sLoadSptCounts, --in boolean + sSptPeriodInSClks => to_unsigned(kSptPeriodInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSptHighTimeInSClks => to_unsigned(kSptHighTimeInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + rRpTransfer => rRpTransfer, --out boolean + sSpTransfer => sSpTransfer, --out boolean + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd new file mode 100644 index 000000000..1ab235fe2 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd @@ -0,0 +1,397 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- Wrapper for the TDC and register control modules. +-- +-- vreview_group Tdc +-- vreview_reviewers dabaker sgupta jmarsar +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + +entity TdcWrapper is + port ( + -- Clocks and Resets : -------------------------------------------------------------- + -- Bus Clock and synchronous bus reset. + BusClk : in std_logic; + bBusReset : in std_logic; + -- Reference Clock + RefClk : in std_logic; + -- Sample Clock + SampleClk : in std_logic; + -- Measurement Clock must run at a very specific frequency, determined by the + -- SampleClk, RefClk, and Sync Pulse rates... oh and a lot of math. + MeasClk : in std_logic; + + + -- Register Port: ------------------------------------------------------------------- + bSyncRegPortOut : out RegPortOut_t; + bSyncRegPortIn : in RegPortIn_t; + + + -- PPS In and Out : ----------------------------------------------------------------- + -- Only required to pulse 1 RefClk cycle. + rPpsPulse : in std_logic; + -- PPS pulse output on the SampleClk domain. + sPpsPulse : out std_logic; + + + -- Sync Pulse Outputs : ------------------------------------------------------------- + -- The repeating pulses can be useful for many things, including passing triggers. + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + + -- Pin bouncers out and in. Must go to unused and unconnected pins on the FPGA! + rGatedPulseToPin : inout std_logic; + sGatedPulseToPin : inout std_logic + ); +end TdcWrapper; + + +architecture struct of TdcWrapper is + + component SyncRegsIfc + port ( + aBusReset : in std_logic; + bBusReset : in std_logic; + BusClk : in std_logic; + aTdcReset : out std_logic; + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + RefClk : in std_logic; + rResetTdc : out std_logic; + rResetTdcDone : in std_logic; + rEnableTdc : out std_logic; + rReRunEnable : out std_logic; + rEnablePpsCrossing : out std_logic; + rPpsPulseCaptured : in std_logic; + rPulserEnableDelayVal : out std_logic_vector(3 downto 0); + SampleClk : in std_logic; + sPpsClkCrossDelayVal : out std_logic_vector(3 downto 0); + MeasClk : in std_logic; + mRpOffset : in std_logic_vector(39 downto 0); + mSpOffset : in std_logic_vector(39 downto 0); + mOffsetsDone : in std_logic; + mOffsetsValid : in std_logic; + rLoadRePulseCounts : out std_logic; + rRePulsePeriodInRClks : out std_logic_vector(23 downto 0); + rRePulseHighTimeInRClks : out std_logic_vector(23 downto 0); + rLoadRpCounts : out std_logic; + rRpPeriodInRClks : out std_logic_vector(15 downto 0); + rRpHighTimeInRClks : out std_logic_vector(15 downto 0); + rLoadRptCounts : out std_logic; + rRptPeriodInRClks : out std_logic_vector(15 downto 0); + rRptHighTimeInRClks : out std_logic_vector(15 downto 0); + sLoadSpCounts : out std_logic; + sSpPeriodInSClks : out std_logic_vector(15 downto 0); + sSpHighTimeInSClks : out std_logic_vector(15 downto 0); + sLoadSptCounts : out std_logic; + sSptPeriodInSClks : out std_logic_vector(15 downto 0); + sSptHighTimeInSClks : out std_logic_vector(15 downto 0)); + end component; + + -- Generic values for the TdcTop instantiation below. These generics are the maximum + -- of possible values for all combinations of Sample and Reference clocks for the N3xx + -- family of devices. + constant kRClksPerRePulsePeriodBitsMax : integer := 24; + constant kRClksPerRpPeriodBitsMax : integer := 16; + constant kSClksPerSpPeriodBitsMax : integer := 16; + constant kPulsePeriodCntSize : integer := 13; + -- The following are ideal values for balancing measurement time and accuracy, based + -- on calcs given in the spec doc. + constant kFreqRefPeriodsToCheckSize : integer := 17; + constant kSyncPeriodsToStampSize : integer := 10; + + --vhook_sigstart + signal aTdcReset: std_logic; + signal bSyncRegPortInFlat: std_logic_vector(49 downto 0); + signal bSyncRegPortOutFlat: std_logic_vector(33 downto 0); + signal mOffsetsDone: boolean; + signal mOffsetsValid: boolean; + signal mRpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal mSpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal rEnablePpsCrossing: std_logic; + signal rEnableTdc: std_logic; + signal rLoadRePulseCounts: std_logic; + signal rLoadRpCounts: std_logic; + signal rLoadRptCounts: std_logic; + signal rPpsPulseCaptured: boolean; + signal rPulserEnableDelayVal: std_logic_vector(3 downto 0); + signal rRePulseHighTimeInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0); + signal rRePulsePeriodInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0); + signal rReRunEnable: std_logic; + signal rResetTdc: std_logic; + signal rResetTdcDone: boolean; + signal rRpHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRpPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRptHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRptPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRpTransferBool: boolean; + signal sLoadSpCounts: std_logic; + signal sLoadSptCounts: std_logic; + signal sPpsClkCrossDelayVal: std_logic_vector(3 downto 0); + signal sPpsPulseAsyncReset: boolean; + signal sSpHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSpPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSptHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSptPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSpTransferBool: boolean; + --vhook_sigend + + signal rPpsPulseAsyncReset_ms, rPpsPulseAsyncReset, + sPpsPulseOut_ms, sPpsPulseOut : std_logic := '0'; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of rPpsPulseAsyncReset_ms : signal is "true"; + attribute ASYNC_REG of rPpsPulseAsyncReset : signal is "true"; + attribute ASYNC_REG of sPpsPulseOut_ms : signal is "true"; + attribute ASYNC_REG of sPpsPulseOut : signal is "true"; + +begin + + -- Cross the PPS from the no-reset domain into the aTdcReset domain since there is a + -- reset crossing going into the TdcWrapper (reset by aTdcReset)! No clock domain + -- crossing here, so crossing a single-cycle pulse is safe. + DoubleSyncToAsyncReset : process (aTdcReset, RefClk) + begin + if to_boolean(aTdcReset) then + rPpsPulseAsyncReset_ms <= '0'; + rPpsPulseAsyncReset <= '0'; + elsif rising_edge(RefClk) then + rPpsPulseAsyncReset_ms <= rPpsPulse; + rPpsPulseAsyncReset <= rPpsPulseAsyncReset_ms; + end if; + end process; + + -- In a similar fashion, cross the output PPS trigger from the async aTdcReset domain + -- to the no-reset of the rest of the design. The odds of this signal triggering a + -- failure are astronomically low (since it only pulses one clock cycle per second), + -- but two flops is worth the assurance it won't mess something else up downstream. + -- Note this double-sync mainly protects against the reset assertion case, since in the + -- de-assertion case sPpsPulseAsyncReset should be zero and not transition for a long + -- time afterwards. Again no clock crossing here, so crossing a single-cycle pulse + -- is safe. + DoubleSyncToNoReset : process (SampleClk) + begin + if rising_edge(SampleClk) then + sPpsPulseOut_ms <= to_stdlogic(sPpsPulseAsyncReset); + sPpsPulseOut <= sPpsPulseOut_ms; + end if; + end process; + + sPpsPulse <= sPpsPulseOut; + + + rRpTransfer <= to_stdlogic(rRpTransferBool); + sSpTransfer <= to_stdlogic(sSpTransferBool); + + --vhook_e TdcTop + --vhook_a aReset to_boolean(aTdcReset) + --vhook_a rResetTdc to_boolean(rResetTdc) + --vhook_a rEnableTdc to_boolean(rEnableTdc) + --vhook_a rReRunEnable to_boolean(rReRunEnable) + --vhook_a rPpsPulse to_boolean(rPpsPulseAsyncReset) + --vhook_a rLoadRePulseCounts to_boolean(rLoadRePulseCounts) + --vhook_a rLoadRpCounts to_boolean(rLoadRpCounts) + --vhook_a rLoadRptCounts to_boolean(rLoadRptCounts) + --vhook_a sLoadSpCounts to_boolean(sLoadSpCounts) + --vhook_a sLoadSptCounts to_boolean(sLoadSptCounts) + --vhook_a rEnablePpsCrossing to_boolean(rEnablePpsCrossing) + --vhook_a rPulserEnableDelayVal unsigned(rPulserEnableDelayVal) + --vhook_a sPpsClkCrossDelayVal unsigned(sPpsClkCrossDelayVal) + --vhook_a rRpTransfer rRpTransferBool + --vhook_a sSpTransfer sSpTransferBool + --vhook_a sPpsPulse sPpsPulseAsyncReset + --vhook_p {^rR(.*)In(.*)Clks} unsigned(rR$1In$2Clks) + --vhook_p {^sS(.*)In(.*)Clks} unsigned(sS$1In$2Clks) + TdcTopx: entity work.TdcTop (struct) + generic map ( + kRClksPerRePulsePeriodBitsMax => kRClksPerRePulsePeriodBitsMax, --integer range 3:32 :=24 + kRClksPerRpPeriodBitsMax => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kSClksPerSpPeriodBitsMax => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => to_boolean(aTdcReset), --in boolean + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + rResetTdc => to_boolean(rResetTdc), --in boolean + rResetTdcDone => rResetTdcDone, --out boolean + rEnableTdc => to_boolean(rEnableTdc), --in boolean + rReRunEnable => to_boolean(rReRunEnable), --in boolean + rPpsPulse => to_boolean(rPpsPulseAsyncReset), --in boolean + rPpsPulseCaptured => rPpsPulseCaptured, --out boolean + rPulserEnableDelayVal => unsigned(rPulserEnableDelayVal), --in unsigned(3:0) + rEnablePpsCrossing => to_boolean(rEnablePpsCrossing), --in boolean + sPpsClkCrossDelayVal => unsigned(sPpsClkCrossDelayVal), --in unsigned(3:0) + sPpsPulse => sPpsPulseAsyncReset, --out boolean + mRpOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mSpOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mOffsetsDone => mOffsetsDone, --out boolean + mOffsetsValid => mOffsetsValid, --out boolean + rLoadRePulseCounts => to_boolean(rLoadRePulseCounts), --in boolean + rRePulsePeriodInRClks => unsigned(rRePulsePeriodInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rRePulseHighTimeInRClks => unsigned(rRePulseHighTimeInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rLoadRpCounts => to_boolean(rLoadRpCounts), --in boolean + rRpPeriodInRClks => unsigned(rRpPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRpHighTimeInRClks => unsigned(rRpHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rLoadRptCounts => to_boolean(rLoadRptCounts), --in boolean + rRptPeriodInRClks => unsigned(rRptPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRptHighTimeInRClks => unsigned(rRptHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + sLoadSpCounts => to_boolean(sLoadSpCounts), --in boolean + sSpPeriodInSClks => unsigned(sSpPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSpHighTimeInSClks => unsigned(sSpHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sLoadSptCounts => to_boolean(sLoadSptCounts), --in boolean + sSptPeriodInSClks => unsigned(sSptPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSptHighTimeInSClks => unsigned(sSptHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + rRpTransfer => rRpTransferBool, --out boolean + sSpTransfer => sSpTransferBool, --out boolean + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + -- Expand/compress the RegPort for moving through the netlist boundary. + bSyncRegPortOut <= Unflatten(bSyncRegPortOutFlat); + bSyncRegPortInFlat <= Flatten(bSyncRegPortIn); + + --vhook SyncRegsIfc + --vhook_# Tying this low is safe because the sync reset is used inside SyncRegsIfc. + --vhook_a aBusReset '0' + --vhook_a bRegPortInFlat bSyncRegPortInFlat + --vhook_a bRegPortOutFlat bSyncRegPortOutFlat + --vhook_a rResetTdcDone to_stdlogic(rResetTdcDone) + --vhook_a rPpsPulseCaptured to_stdlogic(rPpsPulseCaptured) + --vhook_a mOffsetsDone to_stdlogic(mOffsetsDone) + --vhook_a mOffsetsValid to_stdlogic(mOffsetsValid) + --vhook_a mRpOffset std_logic_vector(mRpOffset) + --vhook_a mSpOffset std_logic_vector(mSpOffset) + SyncRegsIfcx: SyncRegsIfc + port map ( + aBusReset => '0', --in std_logic + bBusReset => bBusReset, --in std_logic + BusClk => BusClk, --in std_logic + aTdcReset => aTdcReset, --out std_logic + bRegPortInFlat => bSyncRegPortInFlat, --in std_logic_vector(49:0) + bRegPortOutFlat => bSyncRegPortOutFlat, --out std_logic_vector(33:0) + RefClk => RefClk, --in std_logic + rResetTdc => rResetTdc, --out std_logic + rResetTdcDone => to_stdlogic(rResetTdcDone), --in std_logic + rEnableTdc => rEnableTdc, --out std_logic + rReRunEnable => rReRunEnable, --out std_logic + rEnablePpsCrossing => rEnablePpsCrossing, --out std_logic + rPpsPulseCaptured => to_stdlogic(rPpsPulseCaptured), --in std_logic + rPulserEnableDelayVal => rPulserEnableDelayVal, --out std_logic_vector(3:0) + SampleClk => SampleClk, --in std_logic + sPpsClkCrossDelayVal => sPpsClkCrossDelayVal, --out std_logic_vector(3:0) + MeasClk => MeasClk, --in std_logic + mRpOffset => std_logic_vector(mRpOffset), --in std_logic_vector(39:0) + mSpOffset => std_logic_vector(mSpOffset), --in std_logic_vector(39:0) + mOffsetsDone => to_stdlogic(mOffsetsDone), --in std_logic + mOffsetsValid => to_stdlogic(mOffsetsValid), --in std_logic + rLoadRePulseCounts => rLoadRePulseCounts, --out std_logic + rRePulsePeriodInRClks => rRePulsePeriodInRClks, --out std_logic_vector(23:0) + rRePulseHighTimeInRClks => rRePulseHighTimeInRClks, --out std_logic_vector(23:0) + rLoadRpCounts => rLoadRpCounts, --out std_logic + rRpPeriodInRClks => rRpPeriodInRClks, --out std_logic_vector(15:0) + rRpHighTimeInRClks => rRpHighTimeInRClks, --out std_logic_vector(15:0) + rLoadRptCounts => rLoadRptCounts, --out std_logic + rRptPeriodInRClks => rRptPeriodInRClks, --out std_logic_vector(15:0) + rRptHighTimeInRClks => rRptHighTimeInRClks, --out std_logic_vector(15:0) + sLoadSpCounts => sLoadSpCounts, --out std_logic + sSpPeriodInSClks => sSpPeriodInSClks, --out std_logic_vector(15:0) + sSpHighTimeInSClks => sSpHighTimeInSClks, --out std_logic_vector(15:0) + sLoadSptCounts => sLoadSptCounts, --out std_logic + sSptPeriodInSClks => sSptPeriodInSClks, --out std_logic_vector(15:0) + sSptHighTimeInSClks => sSptHighTimeInSClks); --out std_logic_vector(15:0) + + +end struct; + + +-------------------------------------------------------------------------------- +-- Testbench for TdcWrapper +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + +entity tb_TdcWrapper is end tb_TdcWrapper; + +architecture test of tb_TdcWrapper is + + --vhook_sigstart + signal bBusReset: std_logic; + signal bSyncRegPortIn: RegPortIn_t; + signal bSyncRegPortOut: RegPortOut_t; + signal BusClk: std_logic := '0'; + signal MeasClk: std_logic := '0'; + signal RefClk: std_logic := '0'; + signal rGatedPulseToPin: std_logic; + signal rPpsPulse: std_logic; + signal rRpTransfer: std_logic; + signal SampleClk: std_logic := '0'; + signal sGatedPulseToPin: std_logic; + signal sPpsPulse: std_logic; + signal sSpTransfer: std_logic; + --vhook_sigend + +begin + + --vhook_e TdcWrapper dutx + dutx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sPpsPulse, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + main: process + + begin + report "TdcWrapper Test is EMPTY! (but that's ok in this case)" severity note; + --vhook_nowarn tb_TdcWrapper.test.* + wait; + end process; + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs new file mode 100644 index 000000000..85bb60752 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs @@ -0,0 +1,34 @@ +# +# Copyright 2017 Ettus Research LLC +# + +################################################## +# DB IFC Sources +################################################## +MAGNESIUM_DB_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/db_ifc/, \ +DbCore.vhd \ +DaughterboardRegs.vhd \ +ClockingRegs.vhd \ +PkgMgPersonality.vhd \ +PkgDaughterboardRegMap.vhd \ +PkgClockingRegMap.vhd \ +PkgJesdConfig.vhd \ +RadioClocking.vhd \ +Jesd204bXcvrCore.edf \ +)) + +MAGNESIUM_TOP_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +n3xx.v \ +)) + +MAGNESIUM_DB_TIMING_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db_timing.xdc \ +)) + +MAGNESIUM_DB0_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db0_pins.xdc \ +)) + +MAGNESIUM_DB1_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db1_pins.xdc \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile new file mode 100644 index 000000000..3fbb7d3bb --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile @@ -0,0 +1,22 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +.PHONY: all clean + +SRCS=TopCpld.qpf TopCpld.qsf Timing.sdc PkgMgCpld.vhd PkgSetup.vhd TopCpld.vhd + +all: output_files/TopCpld.svf + +cpld-magnesium-revc.svf: output_files/TopCpld.pof + quartus_cpf --convert --frequency 10.0MHz --voltage 3.3 --operation p $? $@ + +output_files/TopCpld.pof: $(SRCS) + quartus_map TopCpld + quartus_fit TopCpld + quartus_asm TopCpld + quartus_sta TopCpld + +clean: + rm -rf db incremental_db output_files simulation cpld-magnesium-revc.svf + diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd new file mode 100644 index 000000000..327183bea --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd @@ -0,0 +1,424 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgMgCpld.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgMgCpld is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- SignatureReg : 0x0 (TopCpld.vhd) + -- MinorRevReg : 0x1 (TopCpld.vhd) + -- MajorRevReg : 0x2 (TopCpld.vhd) + -- BuildCodeLSB : 0x3 (TopCpld.vhd) + -- BuildCodeMSB : 0x4 (TopCpld.vhd) + -- Scratch : 0x5 (TopCpld.vhd) + -- CpldControl : 0x10 (TopCpld.vhd) + -- LmkControl : 0x11 (TopCpld.vhd) + -- LoStatus : 0x12 (TopCpld.vhd) + -- MykonosControl : 0x13 (TopCpld.vhd) + -- PlScratch : 0x40 (TopCpld.vhd) + -- PlCpldControl : 0x41 (TopCpld.vhd) + -- TxCh1_Idle : 0x50 (TopCpld.vhd) + -- RxCh1_0_Idle : 0x51 (TopCpld.vhd) + -- RxCh1_1_Idle : 0x52 (TopCpld.vhd) + -- TxCh1_TxOn : 0x53 (TopCpld.vhd) + -- RxCh1_0_RxOn : 0x54 (TopCpld.vhd) + -- RxCh1_1_RxOn : 0x55 (TopCpld.vhd) + -- TxCh2_Idle : 0x60 (TopCpld.vhd) + -- RxCh2_0_Idle : 0x61 (TopCpld.vhd) + -- RxCh2_1_Idle : 0x62 (TopCpld.vhd) + -- TxCh2_TxOn : 0x63 (TopCpld.vhd) + -- RxCh2_0_RxOn : 0x64 (TopCpld.vhd) + -- RxCh2_1_RxOn : 0x65 (TopCpld.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group PsSpi_CpldRegisters +--=============================================================================== + + -- SignatureReg Register (from TopCpld.vhd) + constant kSignatureReg : integer := 16#0#; -- Register Offset + constant kSignatureRegSize: integer := 16; -- register width in bits + constant kSignatureRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kProductSignatureSize : integer := 16; --SignatureReg:ProductSignature + constant kProductSignatureMsb : integer := 15; --SignatureReg:ProductSignature + constant kProductSignature : integer := 0; --SignatureReg:ProductSignature + + -- MinorRevReg Register (from TopCpld.vhd) + constant kMinorRevReg : integer := 16#1#; -- Register Offset + constant kMinorRevRegSize: integer := 16; -- register width in bits + constant kMinorRevRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kCpldMinorRevisionSize : integer := 16; --MinorRevReg:CpldMinorRevision + constant kCpldMinorRevisionMsb : integer := 15; --MinorRevReg:CpldMinorRevision + constant kCpldMinorRevision : integer := 0; --MinorRevReg:CpldMinorRevision + + -- MajorRevReg Register (from TopCpld.vhd) + constant kMajorRevReg : integer := 16#2#; -- Register Offset + constant kMajorRevRegSize: integer := 16; -- register width in bits + constant kMajorRevRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kCpldMajorRevisionSize : integer := 16; --MajorRevReg:CpldMajorRevision + constant kCpldMajorRevisionMsb : integer := 15; --MajorRevReg:CpldMajorRevision + constant kCpldMajorRevision : integer := 0; --MajorRevReg:CpldMajorRevision + + -- BuildCodeLSB Register (from TopCpld.vhd) + constant kBuildCodeLSB : integer := 16#3#; -- Register Offset + constant kBuildCodeLSBSize: integer := 16; -- register width in bits + constant kBuildCodeLSBMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kBuildCodeHHSize : integer := 8; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeHHMsb : integer := 7; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeHH : integer := 0; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeDDSize : integer := 8; --BuildCodeLSB:BuildCodeDD + constant kBuildCodeDDMsb : integer := 15; --BuildCodeLSB:BuildCodeDD + constant kBuildCodeDD : integer := 8; --BuildCodeLSB:BuildCodeDD + + -- BuildCodeMSB Register (from TopCpld.vhd) + constant kBuildCodeMSB : integer := 16#4#; -- Register Offset + constant kBuildCodeMSBSize: integer := 16; -- register width in bits + constant kBuildCodeMSBMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kBuildCodeMMSize : integer := 8; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeMMMsb : integer := 7; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeMM : integer := 0; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeYYSize : integer := 8; --BuildCodeMSB:BuildCodeYY + constant kBuildCodeYYMsb : integer := 15; --BuildCodeMSB:BuildCodeYY + constant kBuildCodeYY : integer := 8; --BuildCodeMSB:BuildCodeYY + + -- Scratch Register (from TopCpld.vhd) + constant kScratch : integer := 16#5#; -- Register Offset + constant kScratchSize: integer := 16; -- register width in bits + constant kScratchMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kScratchValSize : integer := 16; --Scratch:ScratchVal + constant kScratchValMsb : integer := 15; --Scratch:ScratchVal + constant kScratchVal : integer := 0; --Scratch:ScratchVal + + -- CpldControl Register (from TopCpld.vhd) + constant kCpldControl : integer := 16#10#; -- Register Offset + constant kCpldControlSize: integer := 16; -- register width in bits + constant kCpldControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kCpldResetSize : integer := 1; --CpldControl:CpldReset + constant kCpldResetMsb : integer := 0; --CpldControl:CpldReset + constant kCpldReset : integer := 0; --CpldControl:CpldReset + + -- LmkControl Register (from TopCpld.vhd) + constant kLmkControl : integer := 16#11#; -- Register Offset + constant kLmkControlSize: integer := 16; -- register width in bits + constant kLmkControlMask : std_logic_vector(15 downto 0) := X"0010"; + constant kVcxoControlSize : integer := 1; --LmkControl:VcxoControl + constant kVcxoControlMsb : integer := 4; --LmkControl:VcxoControl + constant kVcxoControl : integer := 4; --LmkControl:VcxoControl + + -- LoStatus Register (from TopCpld.vhd) + constant kLoStatus : integer := 16#12#; -- Register Offset + constant kLoStatusSize: integer := 16; -- register width in bits + constant kLoStatusMask : std_logic_vector(15 downto 0) := X"0011"; + constant kRxLoLockDetectSize : integer := 1; --LoStatus:RxLoLockDetect + constant kRxLoLockDetectMsb : integer := 0; --LoStatus:RxLoLockDetect + constant kRxLoLockDetect : integer := 0; --LoStatus:RxLoLockDetect + constant kTxLoLockDetectSize : integer := 1; --LoStatus:TxLoLockDetect + constant kTxLoLockDetectMsb : integer := 4; --LoStatus:TxLoLockDetect + constant kTxLoLockDetect : integer := 4; --LoStatus:TxLoLockDetect + + -- MykonosControl Register (from TopCpld.vhd) + constant kMykonosControl : integer := 16#13#; -- Register Offset + constant kMykonosControlSize: integer := 16; -- register width in bits + constant kMykonosControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kMykonosResetSize : integer := 1; --MykonosControl:MykonosReset + constant kMykonosResetMsb : integer := 0; --MykonosControl:MykonosReset + constant kMykonosReset : integer := 0; --MykonosControl:MykonosReset + +--=============================================================================== +-- Register Group PlSpi_FrontEndControl +--=============================================================================== + + -- Enumerated type Rx1Switch1 + constant kRx1Switch1Size : integer := 4; + constant kTxRxInput : integer := 0; -- Rx1Switch1:TxRxInput + constant kRxLoCalInput : integer := 1; -- Rx1Switch1:RxLoCalInput + constant kTrxSwitchOutput : integer := 2; -- Rx1Switch1:TrxSwitchOutput + constant kRx2Input : integer := 3; -- Rx1Switch1:Rx2Input + + -- Enumerated type Rx1Switch2 + constant kRx1Switch2Size : integer := 4; + constant kShutdownSw2 : integer := 0; -- Rx1Switch2:ShutdownSw2 + constant kLowerFilterBankToSwitch3 : integer := 1; -- Rx1Switch2:LowerFilterBankToSwitch3 + constant kBypassPathToSwitch6 : integer := 2; -- Rx1Switch2:BypassPathToSwitch6 + constant kUpperFilterBankToSwitch4 : integer := 3; -- Rx1Switch2:UpperFilterBankToSwitch4 + + -- Enumerated type Rx1Switch3 + constant kRx1Switch3Size : integer := 7; + constant kFilter2100x2850MHz : integer := 0; -- Rx1Switch3:Filter2100x2850MHz + constant kFilter0490LpMHz : integer := 1; -- Rx1Switch3:Filter0490LpMHz + constant kFilter1600x2250MHz : integer := 2; -- Rx1Switch3:Filter1600x2250MHz + constant kFilter0440x0530MHz : integer := 4; -- Rx1Switch3:Filter0440x0530MHz + constant kFilter0650x1000MHz : integer := 5; -- Rx1Switch3:Filter0650x1000MHz + constant kFilter1100x1575MHz : integer := 6; -- Rx1Switch3:Filter1100x1575MHz + constant kShutdownSw3 : integer := 7; -- Rx1Switch3:ShutdownSw3 + + -- Enumerated type Rx1Switch4 + constant kRx1Switch4Size : integer := 3; + constant kFilter2100x2850MHzFrom : integer := 1; -- Rx1Switch4:Filter2100x2850MHzFrom + constant kFilter1600x2250MHzFrom : integer := 2; -- Rx1Switch4:Filter1600x2250MHzFrom + constant kFilter2700HpMHz : integer := 4; -- Rx1Switch4:Filter2700HpMHz + + -- Enumerated type Rx1Switch5 + constant kRx1Switch5Size : integer := 4; + constant kFilter0440x0530MHzFrom : integer := 1; -- Rx1Switch5:Filter0440x0530MHzFrom + constant kFilter1100x1575MHzFrom : integer := 2; -- Rx1Switch5:Filter1100x1575MHzFrom + constant kFilter0490LpMHzFrom : integer := 4; -- Rx1Switch5:Filter0490LpMHzFrom + constant kFilter0650x1000MHzFrom : integer := 8; -- Rx1Switch5:Filter0650x1000MHzFrom + + -- Enumerated type Rx1Switch6 + constant kRx1Switch6Size : integer := 3; + constant kLowerFilterBankFromSwitch5 : integer := 1; -- Rx1Switch6:LowerFilterBankFromSwitch5 + constant kUpperFilterBankFromSwitch4 : integer := 2; -- Rx1Switch6:UpperFilterBankFromSwitch4 + constant kBypassPathFromSwitch2 : integer := 4; -- Rx1Switch6:BypassPathFromSwitch2 + + -- Enumerated type TrxSwitch + constant kTrxSwitchSize : integer := 4; + constant kFromLowerFilterBankTxSw1 : integer := 0; -- TrxSwitch:FromLowerFilterBankTxSw1 + constant kFromTxUpperFilterBankLp6400MHz : integer := 1; -- TrxSwitch:FromTxUpperFilterBankLp6400MHz + constant kRxChannelPath : integer := 2; -- TrxSwitch:RxChannelPath + constant kBypassPathToTxSw3 : integer := 3; -- TrxSwitch:BypassPathToTxSw3 + + -- Enumerated type TxSwitch1 + constant kTxSwitch1Size : integer := 4; + constant kShutdownTxSw1 : integer := 0; -- TxSwitch1:ShutdownTxSw1 + constant kFromTxFilterLp1700MHz : integer := 1; -- TxSwitch1:FromTxFilterLp1700MHz + constant kFromTxFilterLp3400MHz : integer := 2; -- TxSwitch1:FromTxFilterLp3400MHz + constant kFromTxFilterLp0800MHz : integer := 3; -- TxSwitch1:FromTxFilterLp0800MHz + + -- Enumerated type TxSwitch2 + constant kTxSwitch2Size : integer := 4; + constant kToTxFilterLp3400MHz : integer := 1; -- TxSwitch2:ToTxFilterLp3400MHz + constant kToTxFilterLp1700MHz : integer := 2; -- TxSwitch2:ToTxFilterLp1700MHz + constant kToTxFilterLp0800MHz : integer := 4; -- TxSwitch2:ToTxFilterLp0800MHz + constant kToTxFilterLp6400MHz : integer := 8; -- TxSwitch2:ToTxFilterLp6400MHz + + -- Enumerated type TxSwitch3 + constant kTxSwitch3Size : integer := 2; + constant kToTxFilterBanks : integer := 0; -- TxSwitch3:ToTxFilterBanks + constant kBypassPathToTrxSw : integer := 1; -- TxSwitch3:BypassPathToTrxSw + + -- PlScratch Register (from TopCpld.vhd) + constant kPlScratch : integer := 16#40#; -- Register Offset + constant kPlScratchSize: integer := 16; -- register width in bits + constant kPlScratchMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kPlScratchValSize : integer := 16; --PlScratch:PlScratchVal + constant kPlScratchValMsb : integer := 15; --PlScratch:PlScratchVal + constant kPlScratchVal : integer := 0; --PlScratch:PlScratchVal + + -- PlCpldControl Register (from TopCpld.vhd) + constant kPlCpldControl : integer := 16#41#; -- Register Offset + constant kPlCpldControlSize: integer := 16; -- register width in bits + constant kPlCpldControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kPlCpldResetSize : integer := 1; --PlCpldControl:PlCpldReset + constant kPlCpldResetMsb : integer := 0; --PlCpldControl:PlCpldReset + constant kPlCpldReset : integer := 0; --PlCpldControl:PlCpldReset + + -- TxCh1_Idle Register (from TopCpld.vhd) + constant kTxCh1_Idle : integer := 16#50#; -- Register Offset + constant kTxCh1_IdleSize: integer := 16; -- register width in bits + constant kTxCh1_IdleMask : std_logic_vector(15 downto 0) := X"7fff"; + constant kCh1TxSw1Size : integer := 2; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw1Msb : integer := 1; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw1 : integer := 0; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw2Size : integer := 4; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw2Msb : integer := 5; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw2 : integer := 2; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw3Size : integer := 1; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxSw3Msb : integer := 6; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxSw3 : integer := 6; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxLowbandMixerPathSelectSize : integer := 1; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxLowbandMixerPathSelectMsb : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxLowbandMixerPathSelect : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxMixerEnSize : integer := 1; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxMixerEnMsb : integer := 8; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxMixerEn : integer := 8; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxAmpEnSize : integer := 1; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxAmpEnMsb : integer := 9; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxAmpEn : integer := 9; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxPaEnSize : integer := 1; --TxCh1_Idle:Ch1TxPaEn + constant kCh1TxPaEnMsb : integer := 10; --TxCh1_Idle:Ch1TxPaEn + constant kCh1TxPaEn : integer := 10; --TxCh1_Idle:Ch1TxPaEn + constant kCh1SwTrxSize : integer := 2; --TxCh1_Idle:Ch1SwTrx + constant kCh1SwTrxMsb : integer := 12; --TxCh1_Idle:Ch1SwTrx + constant kCh1SwTrx : integer := 11; --TxCh1_Idle:Ch1SwTrx + constant kCh1TxLedSize : integer := 1; --TxCh1_Idle:Ch1TxLed + constant kCh1TxLedMsb : integer := 13; --TxCh1_Idle:Ch1TxLed + constant kCh1TxLed : integer := 13; --TxCh1_Idle:Ch1TxLed + constant kCh1MykEnTxSize : integer := 1; --TxCh1_Idle:Ch1MykEnTx + constant kCh1MykEnTxMsb : integer := 14; --TxCh1_Idle:Ch1MykEnTx + constant kCh1MykEnTx : integer := 14; --TxCh1_Idle:Ch1MykEnTx + + -- RxCh1_0_Idle Register (from TopCpld.vhd) + constant kRxCh1_0_Idle : integer := 16#51#; -- Register Offset + constant kRxCh1_0_IdleSize: integer := 16; -- register width in bits + constant kRxCh1_0_IdleMask : std_logic_vector(15 downto 0) := X"3fff"; + constant kCh1RxSw1Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw1Msb : integer := 1; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw1 : integer := 0; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw2Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw2Msb : integer := 3; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw2 : integer := 2; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw3Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw3Msb : integer := 6; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw3 : integer := 4; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw4Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw4Msb : integer := 9; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw4 : integer := 7; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw5Size : integer := 4; --RxCh1_0_Idle:Ch1RxSw5 + constant kCh1RxSw5Msb : integer := 13; --RxCh1_0_Idle:Ch1RxSw5 + constant kCh1RxSw5 : integer := 10; --RxCh1_0_Idle:Ch1RxSw5 + + -- RxCh1_1_Idle Register (from TopCpld.vhd) + constant kRxCh1_1_Idle : integer := 16#52#; -- Register Offset + constant kRxCh1_1_IdleSize: integer := 16; -- register width in bits + constant kRxCh1_1_IdleMask : std_logic_vector(15 downto 0) := X"07ff"; + constant kCh1RxSw6Size : integer := 3; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxSw6Msb : integer := 2; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxSw6 : integer := 0; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxLowbandMixerPathSelectSize : integer := 1; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxLowbandMixerPathSelectMsb : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxLowbandMixerPathSelect : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxMixerEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxMixerEnMsb : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxMixerEn : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxAmpEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxAmpEnMsb : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxAmpEn : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxLna1EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna1EnMsb : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna1En : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna2EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1RxLna2EnMsb : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1RxLna2En : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1Rx2LedSize : integer := 1; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1Rx2LedMsb : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1Rx2Led : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1RxLedSize : integer := 1; --RxCh1_1_Idle:Ch1RxLed + constant kCh1RxLedMsb : integer := 9; --RxCh1_1_Idle:Ch1RxLed + constant kCh1RxLed : integer := 9; --RxCh1_1_Idle:Ch1RxLed + constant kCh1MykEnRxSize : integer := 1; --RxCh1_1_Idle:Ch1MykEnRx + constant kCh1MykEnRxMsb : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx + constant kCh1MykEnRx : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx + + -- TxCh1_TxOn Register (from TopCpld.vhd) + constant kTxCh1_TxOn : integer := 16#53#; -- Register Offset + constant kTxCh1_TxOnSize: integer := 16; -- register width in bits + constant kTxCh1_TxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh1_0_RxOn Register (from TopCpld.vhd) + constant kRxCh1_0_RxOn : integer := 16#54#; -- Register Offset + constant kRxCh1_0_RxOnSize: integer := 16; -- register width in bits + constant kRxCh1_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh1_1_RxOn Register (from TopCpld.vhd) + constant kRxCh1_1_RxOn : integer := 16#55#; -- Register Offset + constant kRxCh1_1_RxOnSize: integer := 16; -- register width in bits + constant kRxCh1_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- TxCh2_Idle Register (from TopCpld.vhd) + constant kTxCh2_Idle : integer := 16#60#; -- Register Offset + constant kTxCh2_IdleSize: integer := 16; -- register width in bits + constant kTxCh2_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_0_Idle Register (from TopCpld.vhd) + constant kRxCh2_0_Idle : integer := 16#61#; -- Register Offset + constant kRxCh2_0_IdleSize: integer := 16; -- register width in bits + constant kRxCh2_0_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_1_Idle Register (from TopCpld.vhd) + constant kRxCh2_1_Idle : integer := 16#62#; -- Register Offset + constant kRxCh2_1_IdleSize: integer := 16; -- register width in bits + constant kRxCh2_1_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- TxCh2_TxOn Register (from TopCpld.vhd) + constant kTxCh2_TxOn : integer := 16#63#; -- Register Offset + constant kTxCh2_TxOnSize: integer := 16; -- register width in bits + constant kTxCh2_TxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_0_RxOn Register (from TopCpld.vhd) + constant kRxCh2_0_RxOn : integer := 16#64#; -- Register Offset + constant kRxCh2_0_RxOnSize: integer := 16; -- register width in bits + constant kRxCh2_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_1_RxOn Register (from TopCpld.vhd) + constant kRxCh2_1_RxOn : integer := 16#65#; -- Register Offset + constant kRxCh2_1_RxOnSize: integer := 16; -- register width in bits + constant kRxCh2_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + +end package; + +package body PkgMgCpld is + + -- function kSignatureRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMinorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMajorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kBuildCodeLSBRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kBuildCodeMSBRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kScratchRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kLmkControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kLoStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMykonosControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPlScratchRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPlCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh1_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh2_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh2_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd new file mode 100644 index 000000000..e19358912 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd @@ -0,0 +1,259 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgSetup.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 September 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Default values for front end config and CPLD constants. +-- +-- Contains the revision constants that must be bumped when the CPLD is updated. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgMgCpld.all; + +package PkgSetup is + + + constant kRdWtWidth : integer := 1; + constant kAddrWidth : integer := 7; + constant kDataWidth : integer := 16; + constant kTotalWidth : integer := kRdWtWidth + kAddrWidth + kDataWidth; + + subtype InterfaceData_t is std_logic_vector(kDataWidth-1 downto 0); + + constant kSignature : InterfaceData_t := x"CAFE"; + + + -- UPDATE THESE REVISIONS when making changes to the CPLD ----------------------------- + -- ------------------------------------------------------------------------------------ + constant kMinorRev : InterfaceData_t := std_logic_vector(to_unsigned(0,kDataWidth)); + constant kMajorRev : InterfaceData_t := std_logic_vector(to_unsigned(5,kDataWidth)); + -- Currently just the timestamp of the build time/date: yymmddhh + constant kBuildCode : std_logic_vector(31 downto 0) := X"18010408"; + + + function kTxChDefault return InterfaceData_t; + function kTxChDefaultRun return InterfaceData_t; + function kRxChDefault0 return InterfaceData_t; + function kRxChDefault1 return InterfaceData_t; + function kRxChDefault0Run return InterfaceData_t; + function kRxChDefault1Run return InterfaceData_t; + + function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Tx2TrxMod (kCh1Val : std_logic_vector) return std_logic_vector; + + function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector; + + +end package; + +package body PkgSetup is + + function kTxChDefault return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize)); + RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kShutdownTxSw1, kCh1TxSw1Size)); + RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size)); + RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size)); + RetVal(kCh1TxLowbandMixerPathSelect) := '0'; + RetVal(kCh1TxMixerEn) := '0'; + RetVal(kCh1TxAmpEn) := '0'; + RetVal(kCh1TxPaEn) := '0'; + RetVal(kCh1TxLed) := '0'; + RetVal(kCh1MykEnTx) := '1'; + return RetVal; + end kTxChDefault; + + function kTxChDefaultRun return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize)); + RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kFromTxFilterLp3400MHz, kCh1TxSw1Size)); + RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size)); + RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size)); + RetVal(kCh1TxLowbandMixerPathSelect) := '0'; + RetVal(kCh1TxMixerEn) := '0'; + RetVal(kCh1TxAmpEn) := '1'; + RetVal(kCh1TxPaEn) := '1'; + RetVal(kCh1TxLed) := '1'; + RetVal(kCh1MykEnTx) := '1'; + return RetVal; + end kTxChDefaultRun; + + + + + function kRxChDefault0 return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size)); + RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kShutdownSw2, kCh1RxSw2Size)); + RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kShutdownSw3, kCh1RxSw3Size)); + RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size)); + RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size)); + return RetVal; + end kRxChDefault0; + + function kRxChDefault1 return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size)); + RetVal(kCh1RxLowbandMixerPathSelect) := '0'; + RetVal(kCh1RxMixerEn) := '0'; + RetVal(kCh1RxAmpEn) := '0'; + RetVal(kCh1RxLna1En) := '0'; + RetVal(kCh1RxLna2En) := '0'; + RetVal(kCh1Rx2Led) := '0'; + RetVal(kCh1RxLed) := '0'; + RetVal(kCh1MykEnRx) := '1'; + return RetVal; + end kRxChDefault1; + + function kRxChDefault0Run return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size)); + RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kLowerFilterBankToSwitch3, kCh1RxSw2Size)); + RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kFilter2100x2850MHz, kCh1RxSw3Size)); + RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size)); + RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size)); + return RetVal; + end kRxChDefault0Run; + + function kRxChDefault1Run return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size)); + RetVal(kCh1RxLowbandMixerPathSelect) := '0'; + RetVal(kCh1RxMixerEn) := '0'; + RetVal(kCh1RxAmpEn) := '1'; + RetVal(kCh1RxLna1En) := '1'; + RetVal(kCh1RxLna2En) := '1'; + RetVal(kCh1Rx2Led) := '1'; -- turn on a LED for grins + RetVal(kCh1RxLed) := '0'; + RetVal(kCh1MykEnRx) := '1'; + return RetVal; + end kRxChDefault1Run; + + + + + + + function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 2); + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3); + return RetVal; + end Tx2Switch2Mod; + + function Tx2TrxMod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + if kCh1Val = "00" then RetVal := "00"; + elsif kCh1Val = "01" then RetVal := "10"; + elsif kCh1Val = "10" then RetVal := "01"; + elsif kCh1Val = "11" then RetVal := "11"; + else RetVal := "00"; end if; + return RetVal; + end Tx2TrxMod; + + + + function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "00" then RetVal := "01"; + elsif kCh1Val = "01" then RetVal := "00"; + elsif kCh1Val = "10" then RetVal := "11"; + elsif kCh1Val = "11" then RetVal := "10"; + else RetVal := "00"; end if; + return RetVal; + end Rx2Switch1Mod; + + function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "00" then RetVal := "00"; + elsif kCh1Val = "01" then RetVal := "11"; + elsif kCh1Val = "10" then RetVal := "10"; + elsif kCh1Val = "11" then RetVal := "01"; + else RetVal := "00"; end if; + return RetVal; + end Rx2Switch2Mod; + + function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "000" then RetVal := "100"; + elsif kCh1Val = "001" then RetVal := "101"; + elsif kCh1Val = "010" then RetVal := "110"; + elsif kCh1Val = "011" then RetVal := "011"; + elsif kCh1Val = "100" then RetVal := "001"; + elsif kCh1Val = "101" then RetVal := "000"; + elsif kCh1Val = "110" then RetVal := "010"; + elsif kCh1Val = "111" then RetVal := "111"; + else RetVal := "000"; end if; + return RetVal; + end Rx2Switch3Mod; + + function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2); + return RetVal; + end Rx2Switch4Mod; + + function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 2); + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3); + return RetVal; + end Rx2Switch5Mod; + + function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2); + return RetVal; + end Rx2Switch6Mod; + + +end package body;
\ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc new file mode 100644 index 000000000..496814662 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc @@ -0,0 +1,160 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + +# All the magic numbers come from the "/n3xx/dboards/mg/doc/mg_timing.xlsx" timing +# analysis spreadsheet. Analysis should be re-performed every time a board rev occurs +# that affects the CPLD interfaces. + +## PS Slave Constraints ################################################################# +# - PsClk Rate +# - PsClk to SDI +# - PsClk to LE (sync and async paths) +# - PsClk to SDO + +# Maximum 4 MHz clock rate! This is heavily limited by the read data turnaround time... +# and could be up to 20 MHz if only performing writes. +create_clock -name PsClk -period 250 [get_ports {PsSpiSck}] + +# SDI is both registered in the CPLD and used as a direct passthrough. First constrain +# the input delay on the local paths inside the CPLD. Passthrough constraints +# are handled elsewhere. + +set PsSdiInputDelayMax 22.303 +set PsSdiInputDelayMin -19.019 + +# SDI is driven from the PS on the falling edge of the Clk. Worst-case data-clock skew +# is around +/-20ns due to FPGA routing delays and board buffering. Complete timing +# analysis is performed and recorded elsewhere. +set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiSdi] -clock_fall +set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiSdi] -clock_fall + +# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and +# synchronously to latch data. First, constrain the overall input delay for sync use. +# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives +# but we still constrain it identically to the SDI in case something goes amiss. +set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiLe] -clock_fall +set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiLe] -clock_fall +# Then set a false path only on the async reset flops. +set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMosiIndex[*]|*] +set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMisoIndex[*]|*] + +# Constrain MISO as snugly as possible through the CPLD without making the tools work +# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns. +# Math for Max = T_clk/2 - 60 = 250/2 - 60 = 65 ns. +set PsSdoOutputDelayMax 60 +set PsSdoOutputDelayMin -10 + +set_output_delay -clock PsClk -max $PsSdoOutputDelayMax [get_ports sPsSpiSdo] +set_output_delay -clock PsClk -min $PsSdoOutputDelayMin [get_ports sPsSpiSdo] + + + +## PL Slave Constraints ################################################################# +# - PlClk Rate +# - PlClk to SDI +# - PlClk to LE (sync and async paths) +# - PlClk to SDO + +# Maximum 5 MHz clock rate! +create_clock -name PlClk -period 200 [get_ports {PlSpiSck}] + +# SDI is both registered in the CPLD and used as a direct passthrough. First constrain +# the input delay on the local paths inside the CPLD. Passthrough constraints +# are handled elsewhere. + +set PlSdiInputDelayMax 10.445 +set PlSdiInputDelayMin -10.378 + +# SDI is driven from the FPGA on the falling edge of the Clk. Worst-case data-clock skew +# is around +/-10ns. Complete timing analysis is performed and recorded elsewhere. +set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiSdi] -clock_fall +set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiSdi] -clock_fall + +# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and +# synchronously to latch data. First, constrain the overall input delay for sync use. +# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives +# but we still constrain it identically to the SDI in case something goes amiss. +set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiLe] -clock_fall +set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiLe] -clock_fall +# Then set a false path only on the async reset flops. +set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMosiIndex[*]|*}] +set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMisoIndex[*]|*}] + +# Constrain MISO as snugly as possible through the CPLD without making the tools work +# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns. +# Math for Max = T_clk/2 - 35 = 200/2 - 35 = 65 ns. +set PlSdoOutputDelayMax 35 +set PlSdoOutputDelayMin -10 + +set_output_delay -clock PlClk -max $PlSdoOutputDelayMax [get_ports lPlSpiSdo] +set_output_delay -clock PlClk -min $PlSdoOutputDelayMin [get_ports lPlSpiSdo] + + + +## Passthrough Constraints ############################################################## +# - LMK SYNC +# - PlClk/PsClk passthrough +# - SDI passthrough for both +# - SDO return mux passthrough for both +# - Cs_n passthrough for both + +# LMK Sync Passthrough: constrain min and max delays for output +set_max_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 17 +set_min_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 2 + +# SPI Passthroughs: constrain min and max delays for outputs and inputs. +# Since the SDI ports have input delays pre-defined above, we have to remove those from +# the delay analysis here by adding the input delay to the constraint. +# Similarly, for the SDO pins add the output delay to the constraint. +set SpiMaxDelay 25 +set SpiMinDelay 5 + +# PS +set_max_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMax + $SpiMaxDelay] +set_min_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMin + $SpiMinDelay] +set_max_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMaxDelay +set_min_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMinDelay +set_max_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMaxDelay +set_min_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMinDelay +set_max_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMaxDelay + $PsSdoOutputDelayMax] +set_min_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMinDelay + $PsSdoOutputDelayMin] + +# PL +set_max_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMax + $SpiMaxDelay] +set_min_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMin + $SpiMinDelay] +set_max_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMaxDelay +set_min_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMinDelay +set_max_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMaxDelay +set_min_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMinDelay +set_max_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMaxDelay + $PlSdoOutputDelayMax] +set_min_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMinDelay + $PlSdoOutputDelayMin] + + + +## Async Inputs ######################################################################### +# aLmkStatus2 aRxLoLockDetect aTxLoLockDetect +set_false_path -from [get_ports {aRxLoLockDetect}] +set_false_path -from [get_ports {aTxLoLockDetect}] + + + +## Async Outputs ######################################################################## +# aMkReset_n aVcxoCtrl +set_false_path -to [get_ports {aMkReset_n}] +set_false_path -to [get_ports {aVcxoCtrl}] + + + +## Sync Front End Outputs ############################################################### +# All we need to do here is constrain for maximum path delay from the aAtr(Rx|Tx)(1|2) +# control bits toggling to the outputs for aCh1* and aCh2* toggling. Just in case the +# user attempts to write the ATR while it's in use, we also constrain from the flops +# to the pins... which covers all paths... so just to -to option is needed. +set_max_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 40 +set_min_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 5 + +# We don't care about the LED timing whatsoever. Let's not have them clogging up our +# precious timing paths. +set_false_path -to [get_ports {aCh*Led*}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf new file mode 100644 index 000000000..e16aaf0af --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 14:51:27 February 24, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "14:51:27 February 24, 2017" + +# Revisions + +PROJECT_REVISION = "TopCpld" diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf new file mode 100644 index 000000000..64238c87a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf @@ -0,0 +1,313 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 14:51:27 February 24, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TopCpld_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX V" +set_global_assignment -name DEVICE 5M570ZF256I5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:51:27 FEBRUARY 24, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name SDC_FILE Timing.sdc +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_SVF_FILE ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + +set_location_assignment PIN_C3 -to aCh2RxSw4[0] +set_location_assignment PIN_C2 -to aCh2TxPaEn +set_location_assignment PIN_D3 -to aCh2RxSw6[0] +set_location_assignment PIN_D1 -to aCh2RxSw4[1] +set_location_assignment PIN_D2 -to aCh2TxSw3 +set_location_assignment PIN_E1 -to aCh2RxSw4[2] +set_location_assignment PIN_E4 -to aCh2RxSw7[1] +set_location_assignment PIN_F2 -to aCh2RxSw6[1] +set_location_assignment PIN_E3 -to aCh2RxSw7[0] +set_location_assignment PIN_F1 -to aCh2RxSw5[0] +set_location_assignment PIN_E2 -to aCh2RxSw5[1] +set_location_assignment PIN_G2 -to aCh2RxSw5[3] +set_location_assignment PIN_F3 -to aCh2TxSw4[0] +set_location_assignment PIN_G1 -to aCh2RxSw6[2] +set_location_assignment PIN_G3 -to aCh2TxSw4[1] +set_location_assignment PIN_H2 -to aCh2TxAmpEn +set_location_assignment PIN_H1 -to aCh2RxSw5[2] +set_location_assignment PIN_J1 -to aCh2TxMixerEn +set_location_assignment PIN_H5 -to aLoSpiSync +set_location_assignment PIN_J2 -to aCh2RxMixerEn +#set_location_assignment PIN_L3 -to aLmkSpiSdio +set_location_assignment PIN_K1 -to aCh2TxSw5[1] +set_location_assignment PIN_K2 -to aCh2TxSw5[0] +set_location_assignment PIN_M2 -to aLmkSpiSdio +set_location_assignment PIN_L1 -to aCh2RxSw8[0] +set_location_assignment PIN_M3 -to lPlSpiSdi +set_location_assignment PIN_L2 -to aCh2RxSw8[1] +set_location_assignment PIN_M1 -to aCh2RxAmpEn +set_location_assignment PIN_N2 -to aLmkSpiSck +set_location_assignment PIN_N1 -to aLmkSpiCs_n +set_location_assignment PIN_N3 -to PlSpiSck +# set_location_assignment PIN_P2 -to lPlSpiLe +set_location_assignment PIN_R3 -to aMkReset_n +set_location_assignment PIN_R1 -to lPlSpiLe +set_location_assignment PIN_T2 -to aLmkSync +set_location_assignment PIN_R4 -to aVcxoCtrl +set_location_assignment PIN_T4 -to aDacDin +set_location_assignment PIN_T5 -to aDacSync_n +set_location_assignment PIN_R6 -to aPlSpiAddr[2] +set_location_assignment PIN_R5 -to aDacSck +set_location_assignment PIN_T6 -to aPlSpiAddr[1] +set_location_assignment PIN_R7 -to aLmkClkinSel[0] +set_location_assignment PIN_T7 -to lPlSpiSdo +set_location_assignment PIN_P8 -to sPsSpiLe +set_location_assignment PIN_R8 -to aPsSpiAddr[1] +set_location_assignment PIN_P9 -to aPlSpiAddr[0] +set_location_assignment PIN_T8 -to PsSpiSck +set_location_assignment PIN_T9 -to aPsSpiAddr[0] +set_location_assignment PIN_R9 -to sPsSpiSdi +set_location_assignment PIN_P10 -to aAtrRx1 +set_location_assignment PIN_T10 -to sPsSpiSdo +set_location_assignment PIN_P11 -to aAtrTx2 +set_location_assignment PIN_R10 -to aRxLoLockDetect +set_location_assignment PIN_R12 -to aRxLoSck +set_location_assignment PIN_T11 -to aTxLoLockDetect +set_location_assignment PIN_P12 -to aAtrRx2 +set_location_assignment PIN_R11 -to aRxLoDin +set_location_assignment PIN_T12 -to aRxLoCs_n +set_location_assignment PIN_R13 -to aTxLoDin +set_location_assignment PIN_T13 -to aRxLoMuxOut +set_location_assignment PIN_P13 -to aAtrTx1 +set_location_assignment PIN_T15 -to aTxLoSck +set_location_assignment PIN_R14 -to aTxLoCs_n +set_location_assignment PIN_R16 -to aTxLoMuxOut +set_location_assignment PIN_P14 -to aMkTx1En +set_location_assignment PIN_N15 -to aMkRx2En +set_location_assignment PIN_P15 -to aMkRx1En +set_location_assignment PIN_N16 -to aMkTx2En +set_location_assignment PIN_K15 -to aCh1TxSw5[1] +set_location_assignment PIN_L14 -to aCh1RxMixerEn +set_location_assignment PIN_K16 -to aCh1TxMixerEn +set_location_assignment PIN_K14 -to aCh1RxSw8[0] +set_location_assignment PIN_J15 -to aCh1TxAmpEn +set_location_assignment PIN_J14 -to aCh1RxSw8[1] +set_location_assignment PIN_J16 -to aCh1TxSw5[0] +set_location_assignment PIN_H14 -to aCh1RxAmpEn +set_location_assignment PIN_H16 -to aCh1TxSw4[0] +set_location_assignment PIN_G14 -to aCh1TxSw4[1] +set_location_assignment PIN_H15 -to aCh1RxSw5[1] +set_location_assignment PIN_F14 -to aCh1RxSw7[1] +set_location_assignment PIN_G16 -to aCh1RxSw5[0] +set_location_assignment PIN_G15 -to aCh1RxSw4[0] +set_location_assignment PIN_E14 -to aCh1RxSw6[1] +set_location_assignment PIN_F16 -to aCh1RxSw2[1] +set_location_assignment PIN_E13 -to aCh1RxSw7[0] +set_location_assignment PIN_F15 -to aCh1RxSw2[0] +set_location_assignment PIN_D14 -to aCh1RxSw6[2] +set_location_assignment PIN_E16 -to aCh1RxSw6[0] +set_location_assignment PIN_E15 -to aCh1TxSw3 +set_location_assignment PIN_C15 -to aCh1RxSw5[2] +set_location_assignment PIN_D16 -to aCh1TxPaEn +set_location_assignment PIN_C14 -to aCh1RxSw4[1] +set_location_assignment PIN_D15 -to aCh1RxSw5[3] +set_location_assignment PIN_B14 -to aCh1TxSw2[3] +set_location_assignment PIN_B16 -to aCh1RxLna2En +set_location_assignment PIN_C13 -to aCh1RxSw4[2] +set_location_assignment PIN_A15 -to aCh1TxSw2[2] +set_location_assignment PIN_B13 -to aCh1TxSw2[1] +set_location_assignment PIN_A13 -to aCh1TxSw2[0] +set_location_assignment PIN_C12 -to aCh1RxSw1[0] +set_location_assignment PIN_B12 -to aCh1TxSw1[0] +set_location_assignment PIN_D12 -to aCh1RxSw1[1] +set_location_assignment PIN_A12 -to aCh1TxSw1[1] +set_location_assignment PIN_C11 -to aCh1LedTx +set_location_assignment PIN_B11 -to aCh1RxLna1En +set_location_assignment PIN_D11 -to aCh2RxSw1[1] +set_location_assignment PIN_A11 -to aCh1RxSw3[2] +set_location_assignment PIN_C10 -to aCh1LedRx +set_location_assignment PIN_B10 -to aCh1RxSw3[1] +set_location_assignment PIN_C9 -to aCh1LedRx2 +set_location_assignment PIN_A10 -to aCh1RxSw3[0] +set_location_assignment PIN_C8 -to aCh2LedRx2 +set_location_assignment PIN_B9 -to aCh1SwTrx[1] +set_location_assignment PIN_A9 -to aCh1SwTrx[0] +set_location_assignment PIN_A8 -to aCh2SwTrx[0] +set_location_assignment PIN_C7 -to aCh2RxSw3[0] +set_location_assignment PIN_B8 -to aCh2SwTrx[1] +set_location_assignment PIN_C6 -to aCh2LedRx +set_location_assignment PIN_A7 -to aCh2RxSw3[1] +set_location_assignment PIN_B5 -to aCh2TxSw1[0] +set_location_assignment PIN_C5 -to aCh2RxSw1[0] +set_location_assignment PIN_A6 -to aCh2TxSw1[1] +set_location_assignment PIN_D5 -to aCh2LedTx +set_location_assignment PIN_B6 -to aCh2RxSw3[2] +set_location_assignment PIN_B4 -to aCh2RxLna2En +set_location_assignment PIN_A5 -to aCh2RxLna1En +set_location_assignment PIN_C4 -to aCh2RxSw2[0] +set_location_assignment PIN_A4 -to aCh2TxSw2[1] +set_location_assignment PIN_D4 -to aCh2RxSw2[1] +set_location_assignment PIN_A2 -to aCh2TxSw2[3] +set_location_assignment PIN_B3 -to aCh2TxSw2[0] +set_location_assignment PIN_B1 -to aCh2TxSw2[2] + +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name GENERATE_JAM_FILE ON +set_global_assignment -name GENERATE_JBC_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxPaEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSdio +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkReset_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSync +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aVcxoCtrl +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSync_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to lPlSpiSdo +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sPsSpiSdo +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxPaEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedTx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedTx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[2] +set_global_assignment -name SEED 11 +set_global_assignment -name VHDL_FILE PkgMgCpld.vhd +set_global_assignment -name VHDL_FILE PkgSetup.vhd +set_global_assignment -name VHDL_FILE TopCpld.vhd +set_global_assignment -name TOP_LEVEL_ENTITY TopCpld diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd new file mode 100644 index 000000000..4e3488f54 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd @@ -0,0 +1,1228 @@ +------------------------------------------------------------------------------- +-- +-- File: TopCpld.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 24 October 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Top level file for the Magnesium CPLD. +-- +-- This file instantiates two SPI slave ports. One slave port comes from the PS +-- of the motherboard Zynq. It has three slave select pins, mapped as follows: +-- sPlsSpiLe = CPLD Internal Registers +-- aPsSpiAddr(0) = LMK Endpoint +-- aPsSpiAddr(1) = Phase DAC Endpoint +-- +-- The other slave port comes from the PL of the motherboard Zynq. It also has +-- three slave select pins: +-- lPlSpiLe = CPLD Internal Registers +-- aPlSpiAddr(0) = TX Lowband LO +-- aPlSpiAddr(1) = RX Lowband LO +-- +-- The final address line for the PL slave is used as a passthrough for the LMK +-- SYNC pin. +-- +-- +-- For either SPI interface, the CPLD has internal registers that can be addressed +-- whenever the appropriate slave select is driven asserted. These register groups +-- are completely independent from one another, meaning the PS SPI interface cannot +-- access the PL registers, and vice-versa. +-- +-- See the register interface XML at the bottom of this file for details on how +-- each SPI port is expected to be driven, and for the register maps for the PS +-- and PL slaves. +-- +-- +-- BUMPING THE REVISION: +-- In PkgSetup the kMinorRev and kMajorRev are defined. Whenever a change +-- is made to the CPLD, no matter how small, bump the kMinorRev value. If this change +-- breaks compatibility with current HW or SW drivers, increment the kMajorRev value +-- and reset the kMinorRev to zero. Similarly, there is a constant to define the build +-- code, kBuildCode. Currently this is simply the year, month, day, and hour the CPLD is +-- built, but could be user-definable. +-- +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +library work; + use work.PkgMgCpld.all; + use work.PkgSetup.all; + +entity TopCpld is + port( + + -- SPI Port Incoming from FPGA -- + PlSpiSck : in std_logic; + lPlSpiSdi : in std_logic; + lPlSpiSdo : out std_logic; + lPlSpiLe : in std_logic; + aPlSpiAddr : in std_logic_vector(2 downto 0); + + -- SPI Port Incoming from PS -- + PsSpiSck : in std_logic; + sPsSpiSdi : in std_logic; + sPsSpiSdo : out std_logic; + sPsSpiLe : in std_logic; + aPsSpiAddr : in std_logic_vector(1 downto 0); + + -- ATR bits from FPGA -- + aAtrRx1 : in std_logic; + aAtrRx2 : in std_logic; + aAtrTx1 : in std_logic; + aAtrTx2 : in std_logic; + + -- Ch 1 TX (15 bits) -- + aCh1LedTx : out std_logic; + + aCh1TxPaEn : out std_logic; + aCh1TxAmpEn : out std_logic; + aCh1TxMixerEn : out std_logic; + + aCh1TxSw1 : out std_logic_vector(1 downto 0); + aCh1TxSw2 : out std_logic_vector(3 downto 0); + aCh1TxSw3 : out std_logic; + aCh1TxSw4 : out std_logic_vector(1 downto 0); + aCh1TxSw5 : out std_logic_vector(1 downto 0); + + -- Ch 1 RX (29 bits) -- + aCh1LedRx : out std_logic; + aCh1LedRx2 : out std_logic; + + aCh1RxAmpEn : out std_logic; + aCh1RxMixerEn : out std_logic; + aCh1RxLna1En : out std_logic; + aCh1RxLna2En : out std_logic; + aCh1SwTrx : out std_logic_vector(1 downto 0); + + aCh1RxSw1 : out std_logic_vector(1 downto 0); + aCh1RxSw2 : out std_logic_vector(1 downto 0); + aCh1RxSw3 : out std_logic_vector(2 downto 0); + aCh1RxSw4 : out std_logic_vector(2 downto 0); + aCh1RxSw5 : out std_logic_vector(3 downto 0); + aCh1RxSw6 : out std_logic_vector(2 downto 0); + aCh1RxSw7 : out std_logic_vector(1 downto 0); + aCh1RxSw8 : out std_logic_vector(1 downto 0); + + -- Ch 2 TX -- + aCh2LedTx : out std_logic; + + aCh2TxPaEn : out std_logic; + aCh2TxAmpEn : out std_logic; + aCh2TxMixerEn : out std_logic; + + aCh2TxSw1 : out std_logic_vector(1 downto 0); + aCh2TxSw2 : out std_logic_vector(3 downto 0); + aCh2TxSw3 : out std_logic; + aCh2TxSw4 : out std_logic_vector(1 downto 0); + aCh2TxSw5 : out std_logic_vector(1 downto 0); + + -- Ch 2 RX -- + aCh2LedRx : out std_logic; + aCh2LedRx2 : out std_logic; + + aCh2RxAmpEn : out std_logic; + aCh2RxMixerEn : out std_logic; + aCh2RxLna1En : out std_logic; + aCh2RxLna2En : out std_logic; + aCh2SwTrx : out std_logic_vector(1 downto 0); + + aCh2RxSw1 : out std_logic_vector(1 downto 0); + aCh2RxSw2 : out std_logic_vector(1 downto 0); + aCh2RxSw3 : out std_logic_vector(2 downto 0); + aCh2RxSw4 : out std_logic_vector(2 downto 0); + aCh2RxSw5 : out std_logic_vector(3 downto 0); + aCh2RxSw6 : out std_logic_vector(2 downto 0); + aCh2RxSw7 : out std_logic_vector(1 downto 0); + aCh2RxSw8 : out std_logic_vector(1 downto 0); + + -- LMK -- + aLmkSpiSdio : out std_logic; + aLmkSpiSck : out std_logic; + aLmkSpiCs_n : out std_logic; + aLmkClkinSel : in std_logic_vector(0 downto 0); -- SDO + aLmkSync : out std_logic; -- direct connect to aPlSpiAddr(2) + + -- Phase DAC -- + aDacDin : out std_logic; + aDacSync_n : out std_logic; + aDacSck : out std_logic; + aVcxoCtrl : out std_logic; -- @PS-REG-WR + + -- RX and TX LOs -- (timed) + aLoSpiSync : in std_logic; -- Clock! (unused atm, only for reclocking + aRxLoSck : out std_logic; -- the SPI bus if needed for sync) + aRxLoDin : out std_logic; + aRxLoCs_n : out std_logic; + aRxLoMuxOut : in std_logic; + aRxLoLockDetect : in std_logic; -- @PS-REG-RD + aTxLoSck : out std_logic; + aTxLoDin : out std_logic; + aTxLoCs_n : out std_logic; + aTxLoMuxOut : in std_logic; + aTxLoLockDetect : in std_logic; -- @PS-REG-RD + + -- Mykonos Interface -- + aMkReset_n : out std_logic; -- @PS-REG-WR + aMkRx1En : out std_logic; + aMkRx2En : out std_logic; + aMkTx1En : out std_logic; + aMkTx2En : out std_logic + + ); +end TopCpld; + + +architecture RTL of TopCpld is + + -- PS MOSI + signal sCpldPsSpiActive : boolean; + signal sPsMosiIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal sPsMosiBuffer : InterfaceData_t := (others => '0'); + signal sPsRd : boolean := false; + signal sPsRegAddr : unsigned(kAddrWidth-1 downto 0) := (others => '0'); + + -- PS MISO + signal sPsCpldMiso : std_logic; + signal sPsMisoIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal sPsMisoBuffer : std_logic_vector(kTotalWidth-1 downto 0); + + -- PS Register Signals + signal aRxLoLockDetect_ms, sRxLoLockDetect, + aTxLoLockDetect_ms, sTxLoLockDetect : std_logic := '0'; + signal sReset : boolean := false; + signal sScratchVal : InterfaceData_t := (others => '0'); + signal sVcxoControl : std_logic := '1'; + signal sMykonosReset : std_logic := '0'; + + -- PL MOSI + signal lCpldPlSpiActive : boolean; + signal lPlMosiIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal lPlMosiBuffer : InterfaceData_t := (others => '0'); + signal lPlRd : boolean := false; + signal lPlRegAddr : unsigned(kAddrWidth-1 downto 0) := (others => '0'); + + -- PL MISO + signal lPlCpldMiso : std_logic; + signal lPlMisoIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal lPlMisoBuffer : std_logic_vector(kTotalWidth-1 downto 0); + + -- PL Register Signals + signal lScratchVal : InterfaceData_t := (others => '0'); + signal lReset : boolean := false; + + -- See PkgSetup for each Default definition. + signal lTxCh1IdleReg : InterfaceData_t := kTxChDefault; + signal lTxCh2IdleReg : InterfaceData_t := kTxChDefault; + + signal lTxCh1TxOnReg : InterfaceData_t := kTxChDefaultRun; + signal lTxCh2TxOnReg : InterfaceData_t := kTxChDefaultRun; + + signal lRxCh1_0IdleReg : InterfaceData_t := kRxChDefault0; + signal lRxCh1_1IdleReg : InterfaceData_t := kRxChDefault1; + signal lRxCh2_0IdleReg : InterfaceData_t := kRxChDefault0; + signal lRxCh2_1IdleReg : InterfaceData_t := kRxChDefault1; + + signal lRxCh1_0RxOnReg : InterfaceData_t := kRxChDefault0Run; + signal lRxCh1_1RxOnReg : InterfaceData_t := kRxChDefault1Run; + signal lRxCh2_0RxOnReg : InterfaceData_t := kRxChDefault0Run; + signal lRxCh2_1RxOnReg : InterfaceData_t := kRxChDefault1Run; + + signal lTxCh1 : InterfaceData_t; + signal lTxCh2 : InterfaceData_t; + signal lRxCh1_0 : InterfaceData_t; + signal lRxCh1_1 : InterfaceData_t; + signal lRxCh2_0 : InterfaceData_t; + signal lRxCh2_1 : InterfaceData_t; + +begin + + + -- Direct Pass-through Pins : --------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + -- LMK SYNC assignment for direct passthrough to LMK from SPI Addr line. + aLmkSync <= aPlSpiAddr(2); + + + + -- PS SPI Interface : ----------------------------------------------------------------- + -- Composed of a few modules: + -- 1) PsMosiIndex - generate pointer for MOSI Buffer + -- 2) PsMosiBuffer - actually implement the buffer, only when the CPLD is targeted. + -- 3) PsMosiProcessing - process the MOSI data: sort into Rd/!Wt, Address, and Data. + -- This process works on the falling edge of the clock to register the pieces + -- of the MOSI packet as they are complete. The final falling edge registers + -- the data into the individual registers, so it is critical that the clock idle + -- LOW after the transaction is complete such that this final falling edge occurs. + -- 4) PsMisoBuffer - generate pointer for the MISO buffer. The buffer itself is + -- completely async. + -- 5) PsMisoBufferMux - Mux all the register data back into the MISO buffer. + -- 6) StatusSynchronizer - double-synchronizers for status bits from the LMK and LOs. + -- ------------------------------------------------------------------------------------ + + -- Decode the PS SPI Address bits... which are actually going to be used as individual + -- chip selects coming from the PS. + sCpldPsSpiActive <= sPsSpiLe = '0'; + aLmkSpiCs_n <= aPsSpiAddr(0); + aDacSync_n <= aPsSpiAddr(1); + + -- Assign the remainder of the SPI lines to the LMK and DAC. + aLmkSpiSck <= PsSpiSck; + aLmkSpiSdio <= sPsSpiSdi; + aDacSck <= PsSpiSck; + aDacDin <= sPsSpiSdi; + + -- Output mux for data back to the FPGA (PS core). The LMK and CPLD are the only + -- endpoints that have readback enabled. + sPsSpiSdo <= aLmkClkinSel(0) when aPsSpiAddr(0) = '0' else + sPsCpldMiso; + + + + -- Use the LE signal (Cs_n) as the asynchronous reset to the shift register counter. + -- LE will hold the counter in reset until this endpoint is targeted, when it will + -- release the reset (long before the clock toggles) and allow the shift operation + -- to begin. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PsSpiSck will not start toggling + -- until long after the asynchronous reset (sCpldPsSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PsMosiIndex : process(PsSpiSck, sCpldPsSpiActive) + begin + if not sCpldPsSpiActive then + sPsMosiIndex <= (others => '0'); + elsif rising_edge(PsSpiSck) then + sPsMosiIndex <= sPsMosiIndex + 1; + end if; + end process PsMosiIndex; + + + -- Shift in SDI (MOSI) data from the PS on the rising edge of the clock. Only use + -- synchronous resets from here on out. + PsMosiBuffer : process(PsSpiSck) + begin + if rising_edge(PsSpiSck) then + if sReset then + sPsMosiBuffer <= (others => '0'); + else + if sCpldPsSpiActive then + sPsMosiBuffer <= sPsMosiBuffer(sPsMosiBuffer'high-1 downto 0) & sPsSpiSdi; -- left shift + end if; + end if; + end if; + end process PsMosiBuffer; + + + -- As portions of the command and data packets become available, register them here + -- using the falling edge of the PS SPI clock. + PsMosiProcessing : process(PsSpiSck) + begin + if falling_edge(PsSpiSck) then + if sReset then + -- sReset is intentionally self-clearing. It clears on the first falling edge of + -- the next SPI transaction after it is set. Logic on the first rising edge of + -- that next transaction is therefore held in reset. This will not matter + -- as long as SW follows the recommended reset procedure (writing a '1' to reset + -- then writing a '0'), since the first bit of the transaction is '0' for a + -- write operation. + sReset <= false; + sScratchVal <= (others => '0'); + sVcxoControl <= '1'; + sMykonosReset <= '0'; + sPsRd <= false; + sPsRegAddr <= (others => '0'); + else + -- After the first bit is captured, we can determine if it is a write or read. + if (sPsMosiIndex = (kRdWtWidth)) then + sPsRd <= sPsMosiBuffer(0) = '1'; + end if; + + -- After the entire command word is captured, the address is ready for capture. + if (sPsMosiIndex = (kAddrWidth + kRdWtWidth)) then + sPsRegAddr <= unsigned(sPsMosiBuffer(kAddrWidth - 1 downto 0)); + end if; + + -- And finally after the entire transaction is complete we can save off the data + -- on the final falling edge of the SPI clock into it's appropriate place, based + -- off the address value captured above. + if (sPsMosiIndex = kTotalWidth) and (not sPsRd) then + + -- ---------------------------------------------------------------------------- + -- Assign writable register values here! -------------------------------------- + -- ---------------------------------------------------------------------------- + if (sPsRegAddr = kScratch) then + sScratchVal <= sPsMosiBuffer; + end if; + + if (sPsRegAddr = kCpldControl) then + sReset <= sPsMosiBuffer(kCpldReset) = '1'; + end if; + + if (sPsRegAddr = kLmkControl) then + sVcxoControl <= sPsMosiBuffer(kVcxoControl); + end if; + + if (sPsRegAddr = kMykonosControl) then + sMykonosReset <= sPsMosiBuffer(kMykonosReset); + end if; + + end if; + end if; + end if; + end process PsMosiProcessing; + + + -- Send MISO back to FPGA (PS) on the falling edge as well. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PsSpiSck will not start toggling + -- until long after the asynchronous reset (sCpldPsSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PsMisoBuffer : process(PsSpiSck, sCpldPsSpiActive) + begin + if not sCpldPsSpiActive then + sPsMisoIndex <= to_unsigned(kTotalWidth-1, sPsMisoIndex'length); + elsif falling_edge(PsSpiSck) then + if sPsMisoIndex > 0 then + sPsMisoIndex <= sPsMisoIndex - 1; + end if; + end if; + end process PsMisoBuffer; + + sPsCpldMiso <= sPsMisoBuffer(to_integer(sPsMisoIndex)); + + + -- Mux the register data from the CPLD back to the FPGA. + PsMisoBufferMux : process(sPsRegAddr, sScratchVal, sVcxoControl, + sTxLoLockDetect, sRxLoLockDetect, sMykonosReset) + begin + sPsMisoBuffer <= (others => '0'); + case to_integer(sPsRegAddr) is + when kSignatureReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kSignature; + when kMinorRevReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kMinorRev; + when kMajorRevReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kMajorRev; + when kBuildCodeLSB => sPsMisoBuffer(kDataWidth-1 downto 0) <= kBuildCode(15 downto 0); + when kBuildCodeMSB => sPsMisoBuffer(kDataWidth-1 downto 0) <= kBuildCode(31 downto 16); + when kScratch => sPsMisoBuffer(kDataWidth-1 downto 0) <= sScratchVal; + when kLmkControl => sPsMisoBuffer(kVcxoControl) <= sVcxoControl; + when kLoStatus => sPsMisoBuffer(kTxLoLockDetect) <= sTxLoLockDetect; + sPsMisoBuffer(kRxLoLockDetect) <= sRxLoLockDetect; + when kMykonosControl => sPsMisoBuffer(kMykonosReset) <= sMykonosReset; + when others => sPsMisoBuffer(kDataWidth-1 downto 0) <= (others => '0'); + end case; + end process PsMisoBufferMux; + + + -- Double-synchronize the async inputs to the PS clock domain. However, this clock + -- isn't toggling all the time. Whenever it is toggling, let's capture these bits. + StatusSynchronizer : process(PsSpiSck) + begin + if rising_edge(PsSpiSck) then + aRxLoLockDetect_ms <= aRxLoLockDetect; + sRxLoLockDetect <= aRxLoLockDetect_ms; + + aTxLoLockDetect_ms <= aTxLoLockDetect; + sTxLoLockDetect <= aTxLoLockDetect_ms; + end if; + end process; + + + -- PS SPI locals to outputs. + aVcxoCtrl <= sVcxoControl; + aMkReset_n <= not sMykonosReset; + + + + -- PL SPI Interface : ----------------------------------------------------------------- + -- Composed of a few modules: + -- 1) PlMosiIndex - generate pointer for MOSI Buffer + -- 2) PlMosiBuffer - actually implement the buffer, only when the CPLD is targeted. + -- 3) PlMosiProcessing - process the MOSI data: sort into Rd/!Wt, Address, and Data. + -- This process works on the falling edge of the clock to register the pieces + -- of the MOSI packet as they are complete. The final falling edge registers + -- the data into the individual registers, so it is critical that the clock idle + -- LOW after the transaction is complete such that this final falling edge occurs. + -- 4) PlMisoBuffer - generate pointer for the MISO buffer. The buffer itself is + -- completely async. + -- 5) PlMisoBufferMux - Mux all the register data back into the MISO buffer. + -- 6) StatusSynchronizer - double-synchronizers for status bits from the LMK and LOs. + -- ------------------------------------------------------------------------------------ + + -- Decode the PL SPI Address bits... which are actually going to be used as individual + -- chip selects coming from the PL. + lCpldPlSpiActive <= lPlSpiLe = '0'; + aTxLoCs_n <= aPlSpiAddr(0); + aRxLoCs_n <= aPlSpiAddr(1); + + -- Assign the remainder of the SPI lines to the LOs. + aRxLoSck <= PlSpiSck; + aRxLoDin <= lPlSpiSdi; + aTxLoSck <= PlSpiSck; + aTxLoDin <= lPlSpiSdi; + + -- Output mux for data back to the FPGA (PL core). The LMK and CPLD are the only + -- endpoints that have readback enabled. + lPlSpiSdo <= aTxLoMuxOut when aPlSpiAddr(0) = '0' else + aRxLoMuxOut when aPlSpiAddr(1) = '0' else + lPlCpldMiso; + + + + -- Use the LE signal (Cs_n) as the asynchronous reset to the shift register counter. + -- LE will hold the counter in reset until this endpoint is targeted, when it will + -- release the reset (long before the clock toggles) and allow the shift operation + -- to begin. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PlSpiSck will not start toggling + -- until long after the asynchronous reset (lCpldPlSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PlMosiIndex : process(PlSpiSck, lCpldPlSpiActive) + begin + if not lCpldPlSpiActive then + lPlMosiIndex <= (others => '0'); + elsif rising_edge(PlSpiSck) then + lPlMosiIndex <= lPlMosiIndex + 1; + end if; + end process PlMosiIndex; + + + -- Shift in SDI (MOSI) data from the PL on the rising edge of the clock. Only use + -- synchronous resets from here on out. + PlMosiBuffer : process(PlSpiSck) + begin + if rising_edge(PlSpiSck) then + if lReset then + lPlMosiBuffer <= (others => '0'); + else + if lCpldPlSpiActive then + lPlMosiBuffer <= lPlMosiBuffer(lPlMosiBuffer'high-1 downto 0) & lPlSpiSdi; -- left shift + end if; + end if; + end if; + end process PlMosiBuffer; + + + -- As portions of the command and data packets become available, register them here + -- using the falling edge of the PL SPI clock. + PlMosiProcessing : process(PlSpiSck) + begin + if falling_edge(PlSpiSck) then + if lReset then + -- lReset is intentionally self-clearing. It clears on the first falling edge of + -- the next SPI transaction after it is set. Logic on the first rising edge of + -- that next transaction is therefore held in reset. This will not matter + -- as long as SW follows the recommended reset procedure (writing a '1' to reset + -- then writing a '0'), since the first bit of the transaction is '0' for a + -- write operation. + lReset <= false; + lScratchVal <= (others => '0'); + lTxCh1IdleReg <= kTxChDefault; + lTxCh1TxOnReg <= kTxChDefault; + lTxCh2IdleReg <= kTxChDefault; + lTxCh2TxOnReg <= kTxChDefault; + lRxCh1_0IdleReg <= kRxChDefault0; + lRxCh1_1IdleReg <= kRxChDefault1; + lRxCh1_0RxOnReg <= kRxChDefault0; + lRxCh1_1RxOnReg <= kRxChDefault1; + lRxCh2_0IdleReg <= kRxChDefault0; + lRxCh2_1IdleReg <= kRxChDefault1; + lRxCh2_0RxOnReg <= kRxChDefault0; + lRxCh2_1RxOnReg <= kRxChDefault1; + lPlRd <= false; + lPlRegAddr <= (others => '0'); + else + -- After the first bit is captured, we can determine if it is a write or read. + if (lPlMosiIndex = (kRdWtWidth)) then + lPlRd <= lPlMosiBuffer(0) = '1'; + end if; + + -- After the entire command word is captured, the address is ready for capture. + if (lPlMosiIndex = (kAddrWidth + kRdWtWidth)) then + lPlRegAddr <= unsigned(lPlMosiBuffer(kAddrWidth - 1 downto 0)); + end if; + + -- And finally after the entire transaction is complete we can save off the data + -- on the final falling edge of the SPI clock into it's appropriate place, based + -- off the address value captured above. + if (lPlMosiIndex = kTotalWidth) and (not lPlRd) then + + -- ---------------------------------------------------------------------------- + -- Assign writable register values here! -------------------------------------- + -- ---------------------------------------------------------------------------- + if (lPlRegAddr = kPlScratch) then + lScratchVal <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kPlCpldControl) then + lReset <= lPlMosiBuffer(kCpldReset) = '1'; + end if; + + if (lPlRegAddr = kTxCh1_Idle) then + lTxCh1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh1_TxOn) then + lTxCh1TxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh2_Idle) then + lTxCh2IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh2_TxOn) then + lTxCh2TxOnReg <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kRxCh1_0_Idle) then + lRxCh1_0IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_1_Idle) then + lRxCh1_1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_0_RxOn) then + lRxCh1_0RxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_1_RxOn) then + lRxCh1_1RxOnReg <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kRxCh2_0_Idle) then + lRxCh2_0IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_1_Idle) then + lRxCh2_1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_0_RxOn) then + lRxCh2_0RxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_1_RxOn) then + lRxCh2_1RxOnReg <= lPlMosiBuffer; + end if; + + end if; + end if; + end if; + end process PlMosiProcessing; + + + -- Send MISO back to FPGA (PL) on the falling edge as well. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PlSpiSck will not start toggling + -- until long after the asynchronous reset (lCpldPlSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PlMisoBuffer : process(PlSpiSck, lCpldPlSpiActive) + begin + if not lCpldPlSpiActive then + lPlMisoIndex <= to_unsigned(kTotalWidth-1, lPlMisoIndex'length); + elsif falling_edge(PlSpiSck) then + if lPlMisoIndex > 0 then + lPlMisoIndex <= lPlMisoIndex - 1; + end if; + end if; + end process PlMisoBuffer; + + lPlCpldMiso <= lPlMisoBuffer(to_integer(lPlMisoIndex)); + + + -- Mux the register data from the CPLD back to the FPGA. + PlMisoBufferMux : process(lPlRegAddr, lScratchVal, lTxCh1IdleReg, lTxCh1TxOnReg, + lTxCh2IdleReg, lTxCh2TxOnReg, lRxCh1_0IdleReg, + lRxCh1_1IdleReg, lRxCh1_0RxOnReg, lRxCh1_1RxOnReg, + lRxCh2_0IdleReg, lRxCh2_1IdleReg, lRxCh2_0RxOnReg, + lRxCh2_1RxOnReg) + begin + lPlMisoBuffer <= (others => '0'); + case to_integer(lPlRegAddr) is + when kPlScratch => lPlMisoBuffer(kDataWidth-1 downto 0) <= lScratchVal; + when kTxCh1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh1IdleReg; + when kTxCh1_TxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh1TxOnReg; + when kTxCh2_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh2IdleReg; + when kTxCh2_TxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh2TxOnReg; + when kRxCh1_0_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_0IdleReg; + when kRxCh1_1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_1IdleReg; + when kRxCh1_0_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_0RxOnReg; + when kRxCh1_1_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_1RxOnReg; + when kRxCh2_0_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_0IdleReg; + when kRxCh2_1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_1IdleReg; + when kRxCh2_0_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_0RxOnReg; + when kRxCh2_1_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_1RxOnReg; + when others => lPlMisoBuffer(kDataWidth-1 downto 0) <= (others => '0'); + end case; + end process PlMisoBufferMux; + + + -- Use the ATR bits to mux the output values. + lTxCh1 <= lTxCh1IdleReg when aAtrTx1 = '0' else lTxCh1TxOnReg; + lTxCh2 <= lTxCh2IdleReg when aAtrTx2 = '0' else lTxCh2TxOnReg; + + lRxCh1_0 <= lRxCh1_0IdleReg when aAtrRx1 = '0' else lRxCh1_0RxOnReg; + lRxCh1_1 <= lRxCh1_1IdleReg when aAtrRx1 = '0' else lRxCh1_1RxOnReg; + lRxCh2_0 <= lRxCh2_0IdleReg when aAtrRx2 = '0' else lRxCh2_0RxOnReg; + lRxCh2_1 <= lRxCh2_1IdleReg when aAtrRx2 = '0' else lRxCh2_1RxOnReg; + + -- PL SPI locals to outputs. All the register values are set for Channel 1. Channel 2 + -- values are mixed around here in order for the same register settings to work for + -- Channel 1 and Channel 2, even though Ch2 switch configuration is different in HW. + aCh1LedTx <= lTxCh1(kCh1TxLed); + aCh1TxPaEn <= lTxCh1(kCh1TxPaEn); + aCh1TxAmpEn <= lTxCh1(kCh1TxAmpEn); + aCh1TxMixerEn <= lTxCh1(kCh1TxMixerEn); + aCh1TxSw1 <= lTxCh1(kCh1TxSw1Msb downto kCh1TxSw1); + aCh1TxSw2 <= lTxCh1(kCh1TxSw2Msb downto kCh1TxSw2); + aCh1TxSw3 <= lTxCh1(kCh1TxSw3); + aCh1TxSw4 <= "01" when lTxCh1(kCh1TxLowbandMixerPathSelect) = '1' else "10"; + aCh1TxSw5 <= "10" when lTxCh1(kCh1TxLowbandMixerPathSelect) = '1' else "01"; + aCh1SwTrx <= lTxCh1(kCh1SwTrxMsb downto kCh1SwTrx); + aMkTx1En <= lTxCh1(kCh1MykEnTx); + + aCh2LedTx <= lTxCh2(kCh1TxLed); + aCh2TxPaEn <= lTxCh2(kCh1TxPaEn); + aCh2TxAmpEn <= lTxCh2(kCh1TxAmpEn); + aCh2TxMixerEn <= lTxCh2(kCh1TxMixerEn); + aCh2TxSw1 <= lTxCh2(kCh1TxSw1Msb downto kCh1TxSw1); + aCh2TxSw2 <= Tx2Switch2Mod(lTxCh2(kCh1TxSw2Msb downto kCh1TxSw2)); + aCh2TxSw3 <= lTxCh2(kCh1TxSw3); + aCh2TxSw4 <= "10" when lTxCh2(kCh1TxLowbandMixerPathSelect) = '1' else "01"; + aCh2TxSw5 <= "01" when lTxCh2(kCh1TxLowbandMixerPathSelect) = '1' else "10"; + aCh2SwTrx <= Tx2TrxMod(lTxCh2(kCh1SwTrxMsb downto kCh1SwTrx)); + aMkTx2En <= lTxCh2(kCh1MykEnTx); + + aCh1RxSw1 <= lRxCh1_0(kCh1RxSw1Msb downto kCh1RxSw1); + aCh1RxSw2 <= lRxCh1_0(kCh1RxSw2Msb downto kCh1RxSw2); + aCh1RxSw3 <= lRxCh1_0(kCh1RxSw3Msb downto kCh1RxSw3); + aCh1RxSw4 <= lRxCh1_0(kCh1RxSw4Msb downto kCh1RxSw4); + aCh1RxSw5 <= lRxCh1_0(kCh1RxSw5Msb downto kCh1RxSw5); + aCh1RxSw6 <= lRxCh1_1(kCh1RxSw6Msb downto kCh1RxSw6); + aCh1RxSw7 <= "01" when lRxCh1_1(kCh1RxLowbandMixerPathSelect) = '1' else "10"; + aCh1RxSw8 <= "01" when lRxCh1_1(kCh1RxLowbandMixerPathSelect) = '1' else "10"; + aCh1LedRx <= lRxCh1_1(kCh1RxLed) and not lTxCh1(kCh1TxLed); + aCh1LedRx2 <= lRxCh1_1(kCh1Rx2Led); + aCh1RxAmpEn <= lRxCh1_1(kCh1RxAmpEn); + aCh1RxMixerEn <= lRxCh1_1(kCh1RxMixerEn); + aCh1RxLna1En <= lRxCh1_1(kCh1RxLna1En); + aCh1RxLna2En <= lRxCh1_1(kCh1RxLna2En); + aMkRx1En <= lRxCh1_1(kCh1MykEnRx); + + aCh2RxSw1 <= Rx2Switch1Mod(lRxCh2_0(kCh1RxSw1Msb downto kCh1RxSw1)); + aCh2RxSw2 <= Rx2Switch2Mod(lRxCh2_0(kCh1RxSw2Msb downto kCh1RxSw2)); + aCh2RxSw3 <= Rx2Switch3Mod(lRxCh2_0(kCh1RxSw3Msb downto kCh1RxSw3)); + aCh2RxSw4 <= Rx2Switch4Mod(lRxCh2_0(kCh1RxSw4Msb downto kCh1RxSw4)); + aCh2RxSw5 <= Rx2Switch5Mod(lRxCh2_0(kCh1RxSw5Msb downto kCh1RxSw5)); + aCh2RxSw6 <= Rx2Switch6Mod(lRxCh2_1(kCh1RxSw6Msb downto kCh1RxSw6)); + aCh2RxSw7 <= "10" when lRxCh2_1(kCh1RxLowbandMixerPathSelect) = '1' else "01"; + aCh2RxSw8 <= "10" when lRxCh2_1(kCh1RxLowbandMixerPathSelect) = '1' else "01"; + aCh2LedRx <= lRxCh2_1(kCh1RxLed) and not lTxCh2(kCh1TxLed); + aCh2LedRx2 <= lRxCh2_1(kCh1Rx2Led); + aCh2RxAmpEn <= lRxCh2_1(kCh1RxAmpEn); + aCh2RxMixerEn <= lRxCh2_1(kCh1RxMixerEn); + aCh2RxLna1En <= lRxCh2_1(kCh1RxLna1En); + aCh2RxLna2En <= lRxCh2_1(kCh1RxLna2En); + aMkRx2En <= lRxCh2_1(kCh1MykEnRx); + + +end RTL; + + + + +--XmlParse xml_on +--<top name="MgCpld"></top> +--<regmap name="MgCpld"> +-- <group name="PsSpi_CpldRegisters" order="1"> +-- +-- <info> +-- These registers are accessed via the PS SPI interface to the CPLD. They are all +-- internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) +-- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before +-- and after the transaction. CPOL=CPHA=0. To access these registers, use the chip +-- select line named "CPLD-PS-SPI-SLE-33" as an active-low select. +-- </info> +-- +-- <register name="SignatureReg" size="16" offset="0x00" attributes="Readable"> +-- <info> +-- This register contains the device signature. +-- </info> +-- <bitfield name="ProductSignature" range="15..0"> +-- <info> +-- Represents the product family name/number. This field reads back as +-- 0xCAFE. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="MinorRevReg" size="16" offset="0x01" attributes="Readable"> +-- <info> +-- This register contains the device revision numeric code. +-- </info> +-- <bitfield name="CpldMinorRevision" range="15..0"> +-- <info> +-- Contains minor revision code (0,1,2,...). +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="MajorRevReg" size="16" offset="0x02" attributes="Readable"> +-- <info> +-- This register contains the major revision value. +-- </info> +-- <bitfield name="CpldMajorRevision" range="15..0"> +-- <info> +-- Contains major revision code. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="BuildCodeLSB" size="16" offset="0x03" attributes="Readable"> +-- <info> +-- Build code... right now it's the date it was built. LSB in this register. +-- </info> +-- <bitfield name="BuildCodeHH" range="7..0"> +-- <info> +-- Contains build code hour code. +-- </info> +-- </bitfield> +-- <bitfield name="BuildCodeDD" range="15..8"> +-- <info> +-- Contains build code day code. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="BuildCodeMSB" size="16" offset="0x04" attributes="Readable"> +-- <info> +-- Build code... right now it's the date it was built. MSB in this register. +-- </info> +-- <bitfield name="BuildCodeMM" range="7..0"> +-- <info> +-- Contains build code month code. +-- </info> +-- </bitfield> +-- <bitfield name="BuildCodeYY" range="15..8"> +-- <info> +-- Contains build code revision year code. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="Scratch" size="16" offset="0x05" attributes="Readable|Writable"> +-- <info> +-- </info> +-- <bitfield name="ScratchVal" range="15..0"> +-- <info> +-- Contains scratch value for testing. The state of this register has +-- no effect on any other operation in the CPLD. +-- </info> +-- </bitfield> +-- </register> +-- +-- +-- <register name="CpldControl" size="16" offset="0x10" attributes="Writable"> +-- <info> +-- </info> +-- <bitfield name="CpldReset" range="0"> +-- <info> +-- Asserting this bit resets all the CPLD logic. +-- This reset will return all registers on the PS SPI interface to their default +-- state! To use this reset correctly, first write CpldReset to '1', then write +-- it to '0'. Registers will be reset on the _falling_ edge of CpldReset. +-- </info> +-- </bitfield> +-- </register> +-- +-- +-- <register name="LmkControl" size="16" offset="0x11" attributes="Readable|Writable"> +-- <info> +-- </info> +-- <bitfield name="VcxoControl" range="4"> +-- <info> +-- Setting this bit to '0' will allow the Phase DAC to exclusively control the +-- VCXO voltage. Defaults to '1', which allows the Phase DAC to adjust the +-- voltage (but the LMK still has control as well). +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="LoStatus" size="16" offset="0x12" attributes="Readable"> +-- <info> +-- </info> +-- <bitfield name="RxLoLockDetect" range="0" attributes="Readable"> +-- <info> +-- Live lock detect status from the RX LO. +-- </info> +-- </bitfield> +-- <bitfield name="TxLoLockDetect" range="4" attributes="Readable"> +-- <info> +-- Live lock detect status from the TX LO. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="MykonosControl" size="16" offset="0x13" attributes="Readable|Writable"> +-- <info> +-- </info> +-- <bitfield name="MykonosReset" range="0"> +-- <info> +-- Drives the Mykonos hard reset line. Defaults to de-asserted. Write a '1' to +-- assert the reset, and a '0' to de-assert. +-- </info> +-- </bitfield> +-- </register> +-- +-- </group> +-- +-- +-- +-- <group name="PlSpi_FrontEndControl" order="2"> +-- +-- <info> +-- These registers are accessed via the PL SPI interface to the CPLD. They are all +-- internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) +-- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before +-- and after the transaction. CPOL=CPHA=0. To access these registers, use the chip +-- select line named "CPLD-PL-SPI-LE-25" as an active-low select. {br}{br} +-- +-- The ATR bits ultimately control which of these registers actually control +-- the RF front end. +-- </info> +-- +-- <register name="PlScratch" size="16" offset="0x40" attributes="Readable|Writable"> +-- <bitfield name="PlScratchVal" range="15..0"> +-- <info> +-- Contains scratch value for testing. The state of this register has no effect +-- on any other operation in the CPLD. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="PlCpldControl" size="16" offset="0x41" attributes="Writable"> +-- <info> +-- </info> +-- <bitfield name="PlCpldReset" range="0"> +-- <info> +-- Asserting this bit resets all the CPLD logic on the PL SPI interface. +-- This reset will return all registers to their default state! To use this +-- reset correctly, first write PlCpldReset to '1', then write it to '0'. +-- Registers will be reset on the _falling_ edge of PlCpldReset. +-- </info> +-- </bitfield> +-- </register> +-- +-- +-- +-- <enumeratedtype name="TrxSwitch"> +-- <value name="FromLowerFilterBankTxSw1" integer="0"/> +-- <value name="FromTxUpperFilterBankLp6400MHz" integer="1"/> +-- <value name="RxChannelPath" integer="2"/> +-- <value name="BypassPathToTxSw3" integer="3"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="TxSwitch1"> +-- <value name="ShutdownTxSw1" integer="0"/> +-- <value name="FromTxFilterLp1700MHz" integer="1"/> +-- <value name="FromTxFilterLp3400MHz" integer="2"/> +-- <value name="FromTxFilterLp0800MHz" integer="3"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="TxSwitch2"> +-- <value name="ToTxFilterLp3400MHz" integer="1"/> +-- <value name="ToTxFilterLp1700MHz" integer="2"/> +-- <value name="ToTxFilterLp0800MHz" integer="4"/> +-- <value name="ToTxFilterLp6400MHz" integer="8"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="TxSwitch3"> +-- <value name="ToTxFilterBanks" integer="0"/> +-- <value name="BypassPathToTrxSw" integer="1"/> +-- </enumeratedtype> +-- +-- +-- <register name="TxCh1_Idle" size="16" offset="0x50" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel TX 1 when the +-- ATR bits are configured: TX = 0, RX = don't-care. +-- </info> +-- <bitfield name="Ch1TxSw1" type="TxSwitch1" range="1..0"> +-- <info> +-- Controls Switch 1. Filter bank receive switch. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1TxSw2" type="TxSwitch2" range="5..2"> +-- <info> +-- Controls Switch 2. Filter bank distribution switch. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1TxSw3" type="TxSwitch3" range="6"> +-- <info> +-- Controls Switch 3. Bypasses the filter bank and PA, or doesn't. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1TxLowbandMixerPathSelect" range="7"> +-- <info> +-- Controls Switches 4 and 5. Write a '1' to select the Lowband Mixer path. +-- Writing '0' will select the bypass path around the mixer. Default is '0'. Note: +-- Individual control over these switches was removed as an optimization to +-- allow all TX controls to fit in one 16 bit register. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1TxMixerEn" range="8"> +-- <info> +-- Write a '1' to enable the lowband mixer. Note that Ch1TxLowbandMixerPathSelect +-- must be properly configured to select the mixer path. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1TxAmpEn" range="9"> +-- <info> +-- Write a '1' to enable the TX path Amp in between TX switches 3 and 4. The path +-- (from Mykonos) is: TxSw4 -> Amp -> DSA -> TxSw3. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1TxPaEn" range="10"> +-- <info> +-- Write a '1' to enable the TX path PA in between TX switches 2 and 3. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1SwTrx" type="TrxSwitch" range="12..11"> +-- <info> +-- TRX switch control. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1TxLed" range="13"> +-- <info> +-- Red/Green combo LED for the TRX channel. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1MykEnTx" range="14"> +-- <info> +-- Drives the Mykonos input port TX1_ENABLE. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="TxCh1_TxOn" size="16" offset="0x53" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel TX 1 when the +-- ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- </info> +-- </register> +-- +-- <register name="TxCh2_Idle" size="16" offset="0x60" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel TX 2 when the +-- ATR bits are configured: TX = 0, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- </info> +-- </register> +-- +-- <register name="TxCh2_TxOn" size="16" offset="0x63" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel TX 2 when the +-- ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- </info> +-- </register> +-- +-- +-- <enumeratedtype name="Rx1Switch1"> +-- <value name="TxRxInput" integer="0"/> +-- <value name="RxLoCalInput" integer="1"/> +-- <value name="TrxSwitchOutput" integer="2"/> +-- <value name="Rx2Input" integer="3"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="Rx1Switch2"> +-- <value name="ShutdownSw2" integer="0"/> +-- <value name="LowerFilterBankToSwitch3" integer="1"/> +-- <value name="BypassPathToSwitch6" integer="2"/> +-- <value name="UpperFilterBankToSwitch4" integer="3"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="Rx1Switch3"> +-- <value name="Filter2100x2850MHz" integer="0"/> +-- <value name="Filter0490LpMHz" integer="1"/> +-- <value name="Filter1600x2250MHz" integer="2"/> +-- <value name="Filter0440x0530MHz" integer="4"/> +-- <value name="Filter0650x1000MHz" integer="5"/> +-- <value name="Filter1100x1575MHz" integer="6"/> +-- <value name="ShutdownSw3" integer="7"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="Rx1Switch4"> +-- <value name="Filter2100x2850MHzFrom" integer="1"/> +-- <value name="Filter1600x2250MHzFrom" integer="2"/> +-- <value name="Filter2700HpMHz" integer="4"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="Rx1Switch5"> +-- <value name="Filter0440x0530MHzFrom" integer="1"/> +-- <value name="Filter1100x1575MHzFrom" integer="2"/> +-- <value name="Filter0490LpMHzFrom" integer="4"/> +-- <value name="Filter0650x1000MHzFrom" integer="8"/> +-- </enumeratedtype> +-- +-- <enumeratedtype name="Rx1Switch6"> +-- <value name="LowerFilterBankFromSwitch5" integer="1"/> +-- <value name="UpperFilterBankFromSwitch4" integer="2"/> +-- <value name="BypassPathFromSwitch2" integer="4"/> +-- </enumeratedtype> +-- +-- +-- +-- <register name="RxCh1_0_Idle" size="16" offset="0x51" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 0. +-- </info> +-- <bitfield name="Ch1RxSw1" type="Rx1Switch1" range="1..0"> +-- <info> +-- Controls Switch 1. Selects between the cal, bypass, RX2, and TRX paths. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxSw2" type="Rx1Switch2" range="3..2"> +-- <info> +-- Controls Switch 2. First filter switch. Selects between bypass path and +-- the upper/lower filter banks. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxSw3" type="Rx1Switch3" range="6..4"> +-- <info> +-- Controls Switch 3. Lower filter bank transmit switch. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxSw4" type="Rx1Switch4" range="9..7"> +-- <info> +-- Controls Switch 4. Upper filter bank receive switch. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxSw5" type="Rx1Switch5" range="13..10"> +-- <info> +-- Controls Switch 5. Lower filter bank receive switch. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="RxCh1_1_Idle" size="16" offset="0x52" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 0. +-- </info> +-- <bitfield name="Ch1RxSw6" type="Rx1Switch6" range="2..0"> +-- <info> +-- Controls Switch 6. Selects between the upper and lower filter banks and +-- bypass path. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxLowbandMixerPathSelect" range="3"> +-- <info> +-- Controls Switches 7 and 8. Write a '1' to select the Lowband Mixer path. +-- Writing '0' will select the bypass path around the mixer. Default is '0'. Note: +-- Individual control over these switches was removed as an optimization to +-- allow all TX controls to fit in one 16 bit register... so the same was done +-- for the RX path for continuity. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxMixerEn" range="4"> +-- <info> +-- Write a '1' to enable the lowband mixer. Note that Ch1RxLowbandMixerPathSelect +-- must be properly configured to select the mixer path. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxAmpEn" range="5"> +-- <info> +-- Write a '1' to enable the RX path Amp directly before the Mykonos inputs. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxLna1En" range="6"> +-- <info> +-- Write a '1' to enable the RX path LNA1 between RxSw4 and RxSw6. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxLna2En" range="7"> +-- <info> +-- Write a '1' to enable the RX path LNA2 between RxSw5 and RxSw6. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1Rx2Led" range="8"> +-- <info> +-- Green LED for RX2 channel. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1RxLed" range="9"> +-- <info> +-- Red/Green combo LED for the TRX channel. +-- </info> +-- </bitfield> +-- <bitfield name="Ch1MykEnRx" range="10"> +-- <info> +-- Drives the Mykonos input port RX1_ENABLE. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="RxCh1_0_RxOn" size="16" offset="0x54" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- </info> +-- </register> +-- +-- <register name="RxCh1_1_RxOn" size="16" offset="0x55" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- </info> +-- </register> +-- +-- <register name="RxCh2_0_Idle" size="16" offset="0x61" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- </info> +-- </register> +-- +-- <register name="RxCh2_1_Idle" size="16" offset="0x62" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- </info> +-- </register> +-- +-- <register name="RxCh2_0_RxOn" size="16" offset="0x64" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- </info> +-- </register> +-- +-- <register name="RxCh2_1_RxOn" size="16" offset="0x65" attributes="Readable|Writable"> +-- <info> +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- </info> +-- </register> +-- +-- </group> +-- +--</regmap> +--XmlParse xml_off + + + diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc new file mode 100644 index 000000000..b89183a2e --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc @@ -0,0 +1,156 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Daughterboard Pin Definitions for the N310. +# + +## TDC : ################################################################################ +## Bank 10, 2.5V (DB A) +######################################################################################### + +set_property PACKAGE_PIN AB15 [get_ports {UNUSED_PIN_TDCA_0}] +set_property PACKAGE_PIN AB14 [get_ports {UNUSED_PIN_TDCA_1}] +set_property PACKAGE_PIN AB16 [get_ports {UNUSED_PIN_TDCA_2}] +set_property PACKAGE_PIN AB17 [get_ports {UNUSED_PIN_TDCA_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCA_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCA_*}] + +## USRP IO A : ########################################################################## +## Banks 10/33 +######################################################################################### + +## HP GPIO, Bank 33, 1.8V + +set_property PACKAGE_PIN G1 [get_ports {DBA_CPLD_PS_SPI_LE}] +set_property PACKAGE_PIN H2 [get_ports {DBA_CPLD_PS_SPI_SCLK}] +set_property PACKAGE_PIN D1 [get_ports {DBA_CH1_TX_DSA_DATA[5]}] +# set_property PACKAGE_PIN E1 [get_ports {nc}] +set_property PACKAGE_PIN H1 [get_ports {DBA_CPLD_PS_SPI_ADDR[0]}] +set_property PACKAGE_PIN J1 [get_ports {DBA_CPLD_PS_SPI_ADDR[1]}] +set_property PACKAGE_PIN A5 [get_ports {DBA_CH1_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN A4 [get_ports {DBA_CH1_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN F5 [get_ports {DBA_CPLD_PS_SPI_SDO}] +set_property PACKAGE_PIN E5 [get_ports {DBA_CPLD_PS_SPI_SDI}] +set_property PACKAGE_PIN E3 [get_ports {DBA_CH1_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN E2 [get_ports {DBA_CH1_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN A3 [get_ports {DBA_CH1_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN A2 [get_ports {DBA_CH1_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN K1 [get_ports {DBA_ATR_RX_1}] +set_property PACKAGE_PIN L1 [get_ports {DBA_ATR_TX_2}] +set_property PACKAGE_PIN C4 [get_ports {DBA_CH1_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN C3 [get_ports {DBA_CH1_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN F4 [get_ports {DBA_ATR_TX_1}] +set_property PACKAGE_PIN F3 [get_ports {DBA_ATR_RX_2}] +# set_property PACKAGE_PIN B1 [get_ports {nc}] +set_property PACKAGE_PIN B2 [get_ports {DBA_CH1_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN C1 [get_ports {DBA_CH1_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN C2 [get_ports {DBA_CH1_RX_DSA_DATA[2]}] + +## HR GPIO, Bank 10, 2.5V + +set_property PACKAGE_PIN AG12 [get_ports {DBA_MYK_SYNC_IN_n}] +set_property PACKAGE_PIN AH12 [get_ports {DBA_CPLD_PL_SPI_ADDR[0]}] +set_property PACKAGE_PIN AJ13 [get_ports {DBA_MYK_SPI_SDO}] +set_property PACKAGE_PIN AJ14 [get_ports {DBA_MYK_SPI_SDIO}] +set_property PACKAGE_PIN AG15 [get_ports {DBA_CPLD_PL_SPI_ADDR[1]}] +set_property PACKAGE_PIN AF15 [get_ports {DBA_CH2_TX_DSA_DATA[5]}] +set_property PACKAGE_PIN AH13 [get_ports {DBA_CPLD_JTAG_TDI}] +set_property PACKAGE_PIN AH14 [get_ports {DBA_CPLD_JTAG_TDO}] +set_property PACKAGE_PIN AK15 [get_ports {DBA_MYK_GPIO_1}] +set_property PACKAGE_PIN AJ15 [get_ports {DBA_MYK_GPIO_4}] +set_property PACKAGE_PIN AH16 [get_ports {DBA_CH2_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN AH17 [get_ports {DBA_CH2_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN AE12 [get_ports {DBA_MYK_SYNC_OUT_n}] +set_property PACKAGE_PIN AF12 [get_ports {DBA_CPLD_PL_SPI_SDO}] +set_property PACKAGE_PIN AK12 [get_ports {DBA_MYK_GPIO_13}] +set_property PACKAGE_PIN AK13 [get_ports {DBA_MYK_GPIO_0}] +set_property PACKAGE_PIN AK16 [get_ports {DBA_MYK_INTRQ}] +set_property PACKAGE_PIN AJ16 [get_ports {DBA_CH2_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN AH18 [get_ports {DBA_CH2_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN AJ18 [get_ports {DBA_CH2_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN AF14 [get_ports {DBA_FPGA_CLK_P}] +set_property PACKAGE_PIN AG14 [get_ports {DBA_FPGA_CLK_N}] +set_property PACKAGE_PIN AG17 [get_ports {DBA_FPGA_SYSREF_P}] +set_property PACKAGE_PIN AG16 [get_ports {DBA_FPGA_SYSREF_N}] +set_property PACKAGE_PIN AD15 [get_ports {DBA_CH2_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN AD16 [get_ports {DBA_CH2_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN AE13 [get_ports {DBA_CPLD_JTAG_TMS}] +set_property PACKAGE_PIN AF13 [get_ports {DBA_CPLD_JTAG_TCK}] +set_property PACKAGE_PIN AE15 [get_ports {DBA_MYK_GPIO_15}] +set_property PACKAGE_PIN AE16 [get_ports {DBA_MYK_SPI_CS_n}] +set_property PACKAGE_PIN AF17 [get_ports {DBA_CH2_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN AF18 [get_ports {DBA_CH2_RX_DSA_DATA[2]}] +set_property PACKAGE_PIN AC16 [get_ports {DBA_CPLD_PL_SPI_LE}] +set_property PACKAGE_PIN AC17 [get_ports {DBA_CPLD_PL_SPI_SDI}] +set_property PACKAGE_PIN AD13 [get_ports {DBA_MYK_GPIO_12}] +set_property PACKAGE_PIN AD14 [get_ports {DBA_MYK_GPIO_14}] +set_property PACKAGE_PIN AE17 [get_ports {DBA_MYK_SPI_SCLK}] +set_property PACKAGE_PIN AE18 [get_ports {DBA_MYK_GPIO_3}] +set_property PACKAGE_PIN AB12 [get_ports {DBA_CH2_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN AC12 [get_ports {DBA_CH2_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN AC13 [get_ports {DBA_CPLD_PL_SPI_ADDR[2]}] +set_property PACKAGE_PIN AC14 [get_ports {DBA_CPLD_PL_SPI_SCLK}] + +# set_property PACKAGE_PIN AB25 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property IOSTANDARD LVCMOS33 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property DRIVE 4 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property SLEW SLOW [get_ports {DBA_SWITCHER_CLOCK}] + +# During SI measurements with default drive strength, many of the FPGA-driven lines to +# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs +# we are decreasing the drive strength to the minimum value (4mA) and explicitly +# declaring the (default) slew rate as SLOW. + +set UsrpIoAHpPinsSe [get_ports {DBA_CPLD_PS_* \ + DBA_CH1_* \ + DBA_ATR*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoAHpPinsSe +set_property DRIVE 4 $UsrpIoAHpPinsSe +set_property SLEW SLOW $UsrpIoAHpPinsSe + +set UsrpIoAHrPinsSe [get_ports {DBA_MYK_SPI_* \ + DBA_MYK_INTRQ \ + DBA_MYK_SYNC* \ + DBA_MYK_GPIO* \ + DBA_CPLD_PL_* \ + DBA_CPLD_JTAG_* \ + DBA_CH2*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSe +set_property DRIVE 4 $UsrpIoAHrPinsSe +set_property SLEW SLOW $UsrpIoAHrPinsSe + +set UsrpIoAHrPinsDiff [get_ports {DBA_FPGA_CLK_* \ + DBA_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoAHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoAHrPinsDiff + +# Do not allow the DSA lines to float... give them a weak pull if undriven. +set_property PULLUP TRUE [get_ports {DBA_CH*_*X_DSA_DATA[*]}] + + +### MGTs, Bank 112 + +set_property PACKAGE_PIN N8 [get_ports {USRPIO_A_MGTCLK_P}] +set_property PACKAGE_PIN N7 [get_ports {USRPIO_A_MGTCLK_N}] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the Mykonos lane crossbar settings. +set_property PACKAGE_PIN V6 [get_ports {USRPIO_A_RX_P[0]}] +set_property PACKAGE_PIN V5 [get_ports {USRPIO_A_RX_N[0]}] +set_property PACKAGE_PIN U4 [get_ports {USRPIO_A_RX_P[1]}] +set_property PACKAGE_PIN U3 [get_ports {USRPIO_A_RX_N[1]}] +set_property PACKAGE_PIN T6 [get_ports {USRPIO_A_RX_P[2]}] +set_property PACKAGE_PIN T5 [get_ports {USRPIO_A_RX_N[2]}] +set_property PACKAGE_PIN P6 [get_ports {USRPIO_A_RX_P[3]}] +set_property PACKAGE_PIN P5 [get_ports {USRPIO_A_RX_N[3]}] + +set_property PACKAGE_PIN T2 [get_ports {USRPIO_A_TX_P[0]}] +set_property PACKAGE_PIN T1 [get_ports {USRPIO_A_TX_N[0]}] +set_property PACKAGE_PIN R4 [get_ports {USRPIO_A_TX_P[1]}] +set_property PACKAGE_PIN R3 [get_ports {USRPIO_A_TX_N[1]}] +set_property PACKAGE_PIN P2 [get_ports {USRPIO_A_TX_P[2]}] +set_property PACKAGE_PIN P1 [get_ports {USRPIO_A_TX_N[2]}] +set_property PACKAGE_PIN N4 [get_ports {USRPIO_A_TX_P[3]}] +set_property PACKAGE_PIN N3 [get_ports {USRPIO_A_TX_N[3]}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc new file mode 100644 index 000000000..f95051ba7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc @@ -0,0 +1,156 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Daughterboard Pin Definitions for the N310. +# + +## TDC : ################################################################################ +## Bank 11, 2.5V (DB B) +######################################################################################### + +set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}] +set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}] +set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}] +set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}] + +### USRP IO B : ######################################################################### +## Bank 11/33 +######################################################################################### + +## HP GPIO, Bank 33, 1.8V + +set_property PACKAGE_PIN J4 [get_ports {DBB_CPLD_PS_SPI_LE}] +set_property PACKAGE_PIN J3 [get_ports {DBB_CPLD_PS_SPI_SCLK}] +set_property PACKAGE_PIN D4 [get_ports {DBB_CH1_TX_DSA_DATA[5]}] +# set_property PACKAGE_PIN D3 [get_ports {nc}] +set_property PACKAGE_PIN K2 [get_ports {DBB_CPLD_PS_SPI_ADDR[0]}] +set_property PACKAGE_PIN K3 [get_ports {DBB_CPLD_PS_SPI_ADDR[1]}] +set_property PACKAGE_PIN B5 [get_ports {DBB_CH1_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN B4 [get_ports {DBB_CH1_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN G5 [get_ports {DBB_CPLD_PS_SPI_SDO}] +set_property PACKAGE_PIN G4 [get_ports {DBB_CPLD_PS_SPI_SDI}] +set_property PACKAGE_PIN J5 [get_ports {DBB_CH1_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN K5 [get_ports {DBB_CH1_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN D5 [get_ports {DBB_CH1_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN E6 [get_ports {DBB_CH1_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN L3 [get_ports {DBB_ATR_RX_1}] +set_property PACKAGE_PIN L2 [get_ports {DBB_ATR_TX_2}] +set_property PACKAGE_PIN G6 [get_ports {DBB_CH1_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN H6 [get_ports {DBB_CH1_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN H4 [get_ports {DBB_ATR_TX_1}] +set_property PACKAGE_PIN H3 [get_ports {DBB_ATR_RX_2}] +# set_property PACKAGE_PIN F2 [get_ports {nc}] +set_property PACKAGE_PIN G2 [get_ports {DBB_CH1_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN J6 [get_ports {DBB_CH1_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN K6 [get_ports {DBB_CH1_RX_DSA_DATA[2]}] + +## HR GPIO, Bank 10, 2.5V + +set_property PACKAGE_PIN AK17 [get_ports {DBB_MYK_SYNC_IN_n}] +set_property PACKAGE_PIN AK18 [get_ports {DBB_CPLD_PL_SPI_ADDR[0]}] +set_property PACKAGE_PIN AK21 [get_ports {DBB_MYK_SPI_SDO}] +set_property PACKAGE_PIN AJ21 [get_ports {DBB_MYK_SPI_SDIO}] +set_property PACKAGE_PIN AF19 [get_ports {DBB_CPLD_PL_SPI_ADDR[1]}] +set_property PACKAGE_PIN AG19 [get_ports {DBB_CH2_TX_DSA_DATA[5]}] +set_property PACKAGE_PIN AH19 [get_ports {DBB_CPLD_JTAG_TDI}] +set_property PACKAGE_PIN AJ19 [get_ports {DBB_CPLD_JTAG_TDO}] +set_property PACKAGE_PIN AK22 [get_ports {DBB_MYK_GPIO_1}] +set_property PACKAGE_PIN AK23 [get_ports {DBB_MYK_GPIO_4}] +set_property PACKAGE_PIN AF20 [get_ports {DBB_CH2_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN AG20 [get_ports {DBB_CH2_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN AF23 [get_ports {DBB_MYK_SYNC_OUT_n}] +set_property PACKAGE_PIN AF24 [get_ports {DBB_CPLD_PL_SPI_SDO}] +set_property PACKAGE_PIN AK20 [get_ports {DBB_MYK_GPIO_13}] +set_property PACKAGE_PIN AJ20 [get_ports {DBB_MYK_GPIO_0}] +set_property PACKAGE_PIN AJ23 [get_ports {DBB_MYK_INTRQ}] +set_property PACKAGE_PIN AJ24 [get_ports {DBB_CH2_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN AG24 [get_ports {DBB_CH2_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN AG25 [get_ports {DBB_CH2_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN AG21 [get_ports {DBB_FPGA_CLK_P}] +set_property PACKAGE_PIN AH21 [get_ports {DBB_FPGA_CLK_N}] +set_property PACKAGE_PIN AE22 [get_ports {DBB_FPGA_SYSREF_P}] +set_property PACKAGE_PIN AF22 [get_ports {DBB_FPGA_SYSREF_N}] +set_property PACKAGE_PIN AJ25 [get_ports {DBB_CH2_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN AK25 [get_ports {DBB_CH2_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN AB21 [get_ports {DBB_CPLD_JTAG_TMS}] +set_property PACKAGE_PIN AB22 [get_ports {DBB_CPLD_JTAG_TCK}] +set_property PACKAGE_PIN AD23 [get_ports {DBB_MYK_GPIO_15}] +set_property PACKAGE_PIN AE23 [get_ports {DBB_MYK_SPI_CS_n}] +set_property PACKAGE_PIN AB24 [get_ports {DBB_CH2_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN AA24 [get_ports {DBB_CH2_RX_DSA_DATA[2]}] +set_property PACKAGE_PIN AG22 [get_ports {DBB_CPLD_PL_SPI_LE}] +set_property PACKAGE_PIN AH22 [get_ports {DBB_CPLD_PL_SPI_SDI}] +set_property PACKAGE_PIN AD21 [get_ports {DBB_MYK_GPIO_12}] +set_property PACKAGE_PIN AE21 [get_ports {DBB_MYK_GPIO_14}] +set_property PACKAGE_PIN AC22 [get_ports {DBB_MYK_SPI_SCLK}] +set_property PACKAGE_PIN AC23 [get_ports {DBB_MYK_GPIO_3}] +set_property PACKAGE_PIN AC24 [get_ports {DBB_CH2_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN AD24 [get_ports {DBB_CH2_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN AH23 [get_ports {DBB_CPLD_PL_SPI_ADDR[2]}] +set_property PACKAGE_PIN AH24 [get_ports {DBB_CPLD_PL_SPI_SCLK}] + +# set_property PACKAGE_PIN AA25 [get_ports DBB_SWITCHER_CLOCK] +# set_property IOSTANDARD LVCMOS33 [get_ports DBB_SWITCHER_CLOCK] +# set_property DRIVE 4 [get_ports DBB_SWITCHER_CLOCK] +# set_property SLEW SLOW [get_ports DBB_SWITCHER_CLOCK] + +# During SI measurements with default drive strength, many of the FPGA-driven lines to +# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs +# we are decreasing the drive strength to the minimum value (4mA) and explicitly +# declaring the (default) slew rate as SLOW. + +set UsrpIoBHpPinsSe [get_ports {DBB_CPLD_PS_* \ + DBB_CH1_* \ + DBB_ATR*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe +set_property DRIVE 4 $UsrpIoBHpPinsSe +set_property SLEW SLOW $UsrpIoBHpPinsSe + +set UsrpIoBHrPinsSe [get_ports {DBB_MYK_SPI_* \ + DBB_MYK_INTRQ \ + DBB_MYK_SYNC* \ + DBB_MYK_GPIO* \ + DBB_CPLD_PL_* \ + DBB_CPLD_JTAG_* \ + DBB_CH2*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSe +set_property DRIVE 4 $UsrpIoBHrPinsSe +set_property SLEW SLOW $UsrpIoBHrPinsSe + +set UsrpIoBHrPinsDiff [get_ports {DBB_FPGA_CLK_* \ + DBB_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff + +# Do not allow the DSA lines to float... give them a weak pull if undriven. +set_property PULLUP TRUE [get_ports {DBB_CH*_*X_DSA_DATA[*]}] + + +### MGTs, Bank 112 + +set_property PACKAGE_PIN W8 [get_ports {USRPIO_B_MGTCLK_P}] +set_property PACKAGE_PIN W7 [get_ports {USRPIO_B_MGTCLK_N}] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the Mykonos lane crossbar settings. +set_property PACKAGE_PIN AC4 [get_ports {USRPIO_B_RX_P[0]}] +set_property PACKAGE_PIN AC3 [get_ports {USRPIO_B_RX_N[0]}] +set_property PACKAGE_PIN AB6 [get_ports {USRPIO_B_RX_P[1]}] +set_property PACKAGE_PIN AB5 [get_ports {USRPIO_B_RX_N[1]}] +set_property PACKAGE_PIN Y6 [get_ports {USRPIO_B_RX_P[2]}] +set_property PACKAGE_PIN Y5 [get_ports {USRPIO_B_RX_N[2]}] +set_property PACKAGE_PIN AA4 [get_ports {USRPIO_B_RX_P[3]}] +set_property PACKAGE_PIN AA3 [get_ports {USRPIO_B_RX_N[3]}] + +set_property PACKAGE_PIN AB2 [get_ports {USRPIO_B_TX_P[0]}] +set_property PACKAGE_PIN AB1 [get_ports {USRPIO_B_TX_N[0]}] +set_property PACKAGE_PIN Y2 [get_ports {USRPIO_B_TX_P[1]}] +set_property PACKAGE_PIN Y1 [get_ports {USRPIO_B_TX_N[1]}] +set_property PACKAGE_PIN W4 [get_ports {USRPIO_B_TX_P[2]}] +set_property PACKAGE_PIN W3 [get_ports {USRPIO_B_TX_N[2]}] +set_property PACKAGE_PIN V2 [get_ports {USRPIO_B_TX_P[3]}] +set_property PACKAGE_PIN V1 [get_ports {USRPIO_B_TX_N[3]}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd new file mode 100644 index 000000000..ffaa64f68 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd @@ -0,0 +1,345 @@ +------------------------------------------------------------------------------- +-- +-- File: ClockingRegs.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 17 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register access to the control/status bits and interfaces for the +-- RadioClocking module. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgClockingRegMap.all; + use work.PkgRegs.all; + + +entity ClockingRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + -- Register Bus Clock -- this module connects the BusClk to PsClk, so it's limited + -- to 200 MHz! + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Phase shift interface to the RadioClkMmcm. + -- There is a reset crossing here between the MMCM reset and aReset. The outgoing + -- crossing is safe because (a) the enable signal driven to the MMCM is a strobe-only + -- signal and (b) this interface should only be used when the MMCM is not in reset + -- (SW waits for the MMCM to be out of reset and locked before using this interface). + -- The only input signal, pPsDone, is double-synced in this file before being used. + -- This is OK (even though it is a strobe signal) because there is only a reset + -- crossing and not a clock domain crossing. + pPsInc : out std_logic; + pPsEn : out std_logic; + pPsDone : in std_logic; + + -- PsClk is driven directly by BusClk, so p = b in the logic below! + PsClk : out std_logic; + + -- Sync reset strobes from the register bus to the RadioClkMmcm. + bRadioClkMmcmReset : out std_logic; + -- Status of RadioClk MMCM lock to register bus. + aRadioClksValid : in std_logic; + + bRadioClk1xEnabled : out std_logic; + bRadioClk2xEnabled : out std_logic; + bRadioClk3xEnabled : out std_logic; + + bJesdRefClkPresent : in std_logic + ); +end ClockingRegs; + + +architecture RTL of ClockingRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRadioClkMmcmResetInt : std_logic := '1'; + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + + signal bPsDone, + bPsEn, + bPsInc, + pPsDoneDs_ms, + pPsDoneDs : std_logic := '0'; + + signal bRadioClk1xEnabledInt, + bRadioClk2xEnabledInt, + bRadioClk3xEnabledInt, + bRadioClksValid_ms, + bRadioClksValid : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClksValid_ms : signal is "true"; + attribute ASYNC_REG of bRadioClksValid : signal is "true"; + attribute ASYNC_REG of pPsDoneDs_ms : signal is "true"; + attribute ASYNC_REG of pPsDoneDs : signal is "true"; + +begin + + -- Locals to outputs. + PsClk <= BusClk; + pPsInc <= bPsInc; + pPsEn <= bPsEn; + + bRadioClkMmcmReset <= bRadioClkMmcmResetInt; + + bRadioClk1xEnabled <= bRadioClk1xEnabledInt; + bRadioClk2xEnabled <= bRadioClk2xEnabledInt; + bRadioClk3xEnabled <= bRadioClk3xEnabledInt; + + + -- Write Registers : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + WriteRegisters: process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + else + -- Clear strobe + bPsEn <= '0'; + + if RegWrite(kPhaseShiftControl, bRegPortIn) then + if bRegPortIn.Data(kPsInc) = '1' then + bPsInc <= '1'; + bPsEn <= '1'; + elsif bRegPortIn.Data(kPsDec) = '1' then + bPsInc <= '0'; + bPsEn <= '1'; + end if; + end if; + + if RegWrite(kRadioClkMmcm, bRegPortIn) then + -- Set/Clear pair + if bRegPortIn.Data(kRadioClkMmcmResetSet) = '1' then + bRadioClkMmcmResetInt <= '1'; + elsif bRegPortIn.Data(kRadioClkMmcmResetClear) = '1' then + bRadioClkMmcmResetInt <= '0'; + end if; + end if; + + if RegWrite(kRadioClkEnables, bRegPortIn) then + bRadioClk1xEnabledInt <= bRegPortIn.Data(kRadioClk1xEnabled); + bRadioClk2xEnabledInt <= bRegPortIn.Data(kRadioClk2xEnabled); + bRadioClk3xEnabledInt <= bRegPortIn.Data(kRadioClk3xEnabled); + end if; + + end if; + end if; + end process WriteRegisters; + + + DoubleSyncs : process (aReset, BusClk) + begin + if aReset then + bRadioClksValid_ms <= '0'; + bRadioClksValid <= '0'; + pPsDoneDs_ms <= '0'; + pPsDoneDs <= '0'; + elsif rising_edge(BusClk) then + -- No sync reset on double-syncs (however there are default assignments above)! + bRadioClksValid_ms <= aRadioClksValid; + bRadioClksValid <= bRadioClksValid_ms; + pPsDoneDs_ms <= pPsDone; + pPsDoneDs <= pPsDoneDs_ms; + end if; + end process; + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + else + -- Deassert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + -- Process the returned data from the phase shifter in the MMCM. Note that even + -- though the prefixes are different (p and b), we drive the PsClk from the BusClk + -- so this "crossing" is actually safe. Whenever the Done signal asserts (pPsDone - + -- pay attention to the prefix!) from the MMCM, we set a sticky bit to tell SW + -- that the shift operation is complete. + -- + -- However, if pPsDone asserts at the same time that SW tries to read the register, + -- we should accurately report that the operation is indeed complete and then NOT + -- store the sticky (since it has already been read by SW). If a read does not come + -- through at the same time pPsDone is asserted, then we store the done state as a + -- sticky, bPsDone, which is only cleared by a read to this register. + if RegRead(kPhaseShiftControl, bRegPortIn) then + -- The phase shift is always enabled for the feedback clock in RadioClocking.vhd + bRegPortOutLcl.Data(kPsEnabledForFdbClk) <= '1'; + bRegPortOutLcl.Data(kPsDone) <= bPsDone or pPsDoneDs; + bPsDone <= '0'; + elsif pPsDoneDs = '1' then + bPsDone <= '1'; + end if; + + if RegRead(kRadioClkMmcm, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClkMmcmLocked) <= bRadioClksValid; + end if; + + if RegRead(kRadioClkEnables, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClk1xEnabled) <= bRadioClk1xEnabledInt; + bRegPortOutLcl.Data(kRadioClk2xEnabled) <= bRadioClk2xEnabledInt; + bRegPortOutLcl.Data(kRadioClk3xEnabled) <= bRadioClk3xEnabledInt; + end if; + + if RegRead(kMgtRefClkStatus, bRegPortIn) then + bRegPortOutLcl.Data(kJesdRefClkPresent) <= bJesdRefClkPresent; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +--<regmap name="ClockingRegMap"> +-- <group name="ClockingRegs"> +-- +-- <register name="RadioClkMmcm" size="32" offset="0x20" attributes="Readable|Writable"> +-- <info> +-- </info> +-- <bitfield name="RadioClkMmcmLocked" range="4"> +-- <info> +-- Reflects the locked status of the MMCM. '1' = locked. This bit is only valid +-- when the MMCM reset is de-asserted. Read-only. +-- </info> +-- </bitfield> +-- <bitfield name="RadioClkMmcmResetClear" range="1" attributes="Strobe"> +-- <info> +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to de-assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- </info> +-- </bitfield> +-- <bitfield name="RadioClkMmcmResetSet" range="0" attributes="Strobe"> +-- <info> +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="PhaseShiftControl" size="32" offset="0x24" attributes="Readable|Writable"> +-- <info> +-- Phase Shift for RadioClkMmcm. +-- </info> +-- <bitfield name="PsDone" range="28"> +-- <info> +-- This bit should set after a shift operation successfully completes. +-- Reading this register will clear this bit. Read-only. +-- </info> +-- </bitfield> +-- <bitfield name="PsInc" range="0" attributes="Strobe"> +-- <info> +-- Strobe this bit to increment the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- </info> +-- </bitfield> +-- <bitfield name="PsDec" range="4" attributes="Strobe"> +-- <info> +-- Strobe this bit to decrement the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- </info> +-- </bitfield> +-- <bitfield name="PsEnabledForFdbClk" range="16"> +-- <info> +-- Read-only. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="RadioClkEnables" size="32" offset="0x28" attributes="Readable|Writable"> +-- <info> +-- </info> +-- <bitfield name="RadioClk3xEnabled" range="8"> +-- <info> +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- </info> +-- </bitfield> +-- <bitfield name="RadioClk2xEnabled" range="4"> +-- <info> +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- </info> +-- </bitfield> +-- <bitfield name="RadioClk1xEnabled" range="0"> +-- <info> +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="MgtRefClkStatus" size="32" offset="0x30" attributes="Readable"> +-- <info> +-- </info> +-- <bitfield name="JesdRefClkPresent" range="0"> +-- <info> +-- Live indicator of the MGT Reference Clock toggling and within expected +-- frequency limits. If this bit is de-asserted, then the JESD204b core will +-- not function correctly! +-- </info> +-- </bitfield> +-- </register> +-- +-- </group> +-- +--</regmap> +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd new file mode 100644 index 000000000..7f8ef388a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- +-- File: DaughterboardRegs.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 27 April 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register interface to the semi-static control lines for the Mg +-- Daughterboard. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgDaughterboardRegMap.all; + use work.PkgRegs.all; + + +entity DaughterboardRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Slot and DB ID values. These should be tied to constants! + kDbId : in std_logic_vector(15 downto 0); + kSlotId : in std_logic + + ); +end DaughterboardRegs; + + +architecture RTL of DaughterboardRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + +begin + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + elsif rising_edge(BusClk) then + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + else + -- De-assert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + if RegRead(kDaughterboardId, bRegPortIn) then + bRegPortOutLcl.Data(kDbIdValMsb downto kDbIdVal) <= kDbId; + bRegPortOutLcl.Data(kSlotIdVal) <= kSlotId; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +--<regmap name="DaughterboardRegMap"> +-- <group name="StaticControl" order="1"> +-- +-- <register name="DaughterboardId" size="32" offset="0x30" attributes="Readable"> +-- <info> +-- </info> +-- <bitfield name="DbIdVal" range="15..0"> +-- <info> +-- ID for the DB with which this file is designed to communicate. Matches the DB +-- EEPROM ID. +-- </info> +-- </bitfield> +-- <bitfield name="SlotIdVal" range="16"> +-- <info> +-- ID for the Slot this module controls. Options are 0 and 1 for the N310 MB. +-- </info> +-- </bitfield> +-- </register> +-- +-- </group> +-- +-- +--</regmap> +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd new file mode 100644 index 000000000..e1369ec00 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd @@ -0,0 +1,562 @@ +------------------------------------------------------------------------------- +-- +-- File: DbCore.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 12 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for Daughterboard Control. This includes the semi-static control +-- and status registers, clocking, synchronization, and JESD204B cores. +-- +-- There is no version register for the plain-text files here. +-- Version control for the Sync and JESD204B cores is internal to the netlists. +-- +-- The resets for this core are almost entirely local and/or synchronous. +-- bBusReset is a Synchronous reset on the BusClk domain that resets all of the +-- registers connected to the RegPort, as well as any other stray registers +-- connected to the BusClk. All other resets are local to the modules they touch. +-- No other reset drives all modules universally. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgMgPersonality.all; + use work.PkgRegs.all; + use work.PkgJesdConfig.all; + + +entity DbCore is + generic( + -- Set to '1' to include the White Rabbit TDC. + kInclWhiteRabbitTdc : std_logic := '0' + ); + port( + + -- Resets -- + -- Synchronous Reset for the BusClk domain (mainly for the RegPort) + bBusReset : in std_logic; + + -- Clocks -- + -- Register Bus Clock (any frequency) + BusClk : in std_logic; + -- Always-on at 40 MHz + Clk40 : in std_logic; + -- Super secret crazy awesome measurement clock at weird frequencies. + MeasClk : in std_logic; + -- FPGA Sample Clock from DB LMK + FpgaClk_p : in std_logic; + FpgaClk_n : in std_logic; + + -- Sample Clock Sharing. The clocks generated in this module are exported out to the + -- top level so they can be shared amongst daughterboards. Therefore they must be + -- driven back into the SampleClk*x inputs at a higher level in order for this module + -- to work correctly. There are a few isolated cases where SampleClk*xOut is used + -- directly in this module, and those are documented below. + SampleClk1xOut : out std_logic; + SampleClk1x : in std_logic; + SampleClk2xOut : out std_logic; + SampleClk2x : in std_logic; + + + -- Register Ports -- + -- + -- Only synchronous resets can be used for these ports! + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + + -- Slot ID value. This should be tied to a constant! + kSlotId : in std_logic; + + + -- SYSREF -- + -- + -- SYSREF direct from the LMK + sSysRefFpgaLvds_p, + sSysRefFpgaLvds_n : in std_logic; + -- SYNC directly to the LMK + aLmkSync : out std_logic; + + + -- JESD Signals -- + -- + -- GTX Sample Clock Reference Input. Direct connect to FPGA pins. + JesdRefClk_p, + JesdRefClk_n : in std_logic; + + -- ADC JESD PHY Interface. Direct connect to FPGA pins. + aAdcRx_p, + aAdcRx_n : in std_logic_vector(3 downto 0); + aSyncAdcOut_n : out std_logic; + + -- DAC JESD PHY Interface. Direct connect to FPGA pins. + aDacTx_p, + aDacTx_n : out std_logic_vector(3 downto 0); + aSyncDacIn_n : in std_logic; + + + -- Data Pipes to/from the DACs/ADCs -- + -- + -- - Data is presented as one sample per cycle. + -- - sAdcDataValid asserts when ADC data is valid. + -- - sDacReadyForInput asserts when DAC data is ready to be received. + -- + -- Reset Crossings: + -- The ADC data and valid outputs are synchronously cleared before the asynchronous + -- reset is asserted--preventing any reset crossing issues here between the RX + -- (internal to the core) reset and the no-reset domain of RFNoC. + -- + -- The DAC samples should be zeros on reset de-assertion due to RFI being de-asserted + -- in reset. If they are not zeros, then it is still OK because data is ignored until + -- RFI is asserted. DAC RFI is double-synchronized to protect against the reset + -- crossing. This is safe to do because it simply delays the output of RFI by two + -- cycles on the assertion edge, and as long as reset is held for more than two + -- cycles, the de-assertion edge of RFI should come long before the TX module is + -- taken out of reset. + sAdcDataValid : out std_logic; + sAdcDataSamples0I : out std_logic_vector(15 downto 0); + sAdcDataSamples0Q : out std_logic_vector(15 downto 0); + sAdcDataSamples1I : out std_logic_vector(15 downto 0); + sAdcDataSamples1Q : out std_logic_vector(15 downto 0); + sDacReadyForInput : out std_logic; + sDacDataSamples0I : in std_logic_vector(15 downto 0); + sDacDataSamples0Q : in std_logic_vector(15 downto 0); + sDacDataSamples1I : in std_logic_vector(15 downto 0); + sDacDataSamples1Q : in std_logic_vector(15 downto 0); + + + -- RefClk & Timing & Sync -- + RefClk : in std_logic; + rPpsPulse : in std_logic; + rGatedPulseToPin : inout std_logic; -- straight to pin + sGatedPulseToPin : inout std_logic; -- straight to pin + sPps : out std_logic; + sPpsToIob : out std_logic; + + -- White Rabbit Timing & Sync -- + WrRefClk : in std_logic; + rWrPpsPulse : in std_logic; + rWrGatedPulseToPin : inout std_logic; -- straight to pin + sWrGatedPulseToPin : inout std_logic; -- straight to pin + aPpsSfpSel : in std_logic_vector(1 downto 0); + + + -- Debug for JESD + sAdcSync : out std_logic; + sDacSync : out std_logic; + sSysRef : out std_logic; + + -- Debug for Timing & Sync + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + rWrRpTransfer : out std_logic; + sWrSpTransfer : out std_logic + ); + +end DbCore; + + +architecture RTL of DbCore is + + component Jesd204bXcvrCore + port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR(49 downto 0); + bRegPortOutFlat : out STD_LOGIC_VECTOR(33 downto 0); + aLmkSync : out STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + CaptureSysRefClk : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR(3 downto 0); + aAdcRx_n : in STD_LOGIC_VECTOR(3 downto 0); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR(3 downto 0); + aDacTx_n : out STD_LOGIC_VECTOR(3 downto 0); + aSyncDacIn_n : in STD_LOGIC; + fAdc0DataFlat : out STD_LOGIC_VECTOR(31 downto 0); + fAdc1DataFlat : out STD_LOGIC_VECTOR(31 downto 0); + fDac0DataFlat : in STD_LOGIC_VECTOR(31 downto 0); + fDac1DataFlat : in STD_LOGIC_VECTOR(31 downto 0); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC); + end component; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + --vhook_sigstart + signal aAdcSync: STD_LOGIC; + signal aDacSync: STD_LOGIC; + signal bClockingRegPortOut: RegPortOut_t; + signal bDbRegPortOut: RegPortOut_t; + signal bFpgaClksStable: STD_LOGIC; + signal bJesdCoreRegPortInFlat: STD_LOGIC_VECTOR(49 downto 0); + signal bJesdCoreRegPortOutFlat: STD_LOGIC_VECTOR(33 downto 0); + signal bJesdRefClkPresent: STD_LOGIC; + signal bRadioClk1xEnabled: std_logic; + signal bRadioClk2xEnabled: std_logic; + signal bRadioClk3xEnabled: std_logic; + signal bRadioClkMmcmReset: std_logic; + signal bRadioClksValid: std_logic; + signal pPsDone: std_logic; + signal pPsEn: std_logic; + signal pPsInc: std_logic; + signal PsClk: std_logic; + signal sAdc0DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sAdc1DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal SampleClk1xOutLcl: std_logic; + signal sDac0DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sDac1DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sDacReadyForInputAsyncReset: STD_LOGIC; + signal sRegPps: std_logic; + signal sSysRefAsyncReset: STD_LOGIC; + signal sWrPps: std_logic; + --vhook_sigend + + signal bJesdRegPortInGrp, bSyncRegPortIn, bWrSyncRegPortIn, bRegPortIn : RegPortIn_t; + signal bJesdRegPortOut, bSyncRegPortOut, bWrSyncRegPortOut, bRegPortOut : RegPortOut_t; + + signal sDacReadyForInput_ms, sDacReadyForInputLcl, + sDacSync_ms, sDacSyncLcl, + sAdcSync_ms, sAdcSyncLcl, + sSysRef_ms, sSysRefLcl : std_logic := '0'; + + signal sAdc0Data, sAdc1Data : AdcData_t; + signal sDac0Data, sDac1Data : DacData_t; + + signal sPpsSfpSel_ms, sPpsSfpSel : std_logic_vector(1 downto 0) := (others => '0'); + signal sUseWrTdcPps : boolean := false; + signal sPpsInt, sPpsMuxed : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sDacReadyForInput_ms : signal is "true"; + attribute ASYNC_REG of sDacReadyForInputLcl : signal is "true"; + attribute ASYNC_REG of sDacSync_ms : signal is "true"; + attribute ASYNC_REG of sDacSyncLcl : signal is "true"; + attribute ASYNC_REG of sAdcSync_ms : signal is "true"; + attribute ASYNC_REG of sAdcSyncLcl : signal is "true"; + attribute ASYNC_REG of sSysRef_ms : signal is "true"; + attribute ASYNC_REG of sSysRefLcl : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel_ms : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel : signal is "true"; + +begin + + bRegPortOutFlat <= Flatten(bRegPortOut); + bRegPortIn <= Unflatten(bRegPortInFlat); + + + -- Combine return RegPorts. + bRegPortOut <= bJesdRegPortOut + + bClockingRegPortOut + + bSyncRegPortOut + bWrSyncRegPortOut + + bDbRegPortOut; + + + -- Clocking : ------------------------------------------------------------------------- + -- Automatically export the Sample Clocks and only use the incoming clocks in the + -- remainder of the logic. For a single module, the clocks must be looped back + -- in at a higher level! + -- ------------------------------------------------------------------------------------ + + --vhook_e RadioClocking + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a RadioClk1x SampleClk1xOutLcl + --vhook_a RadioClk2x SampleClk2xOut + --vhook_a RadioClk3x open + RadioClockingx: entity work.RadioClocking (rtl) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --in std_logic + bRadioClksValid => bRadioClksValid, --out std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --in std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --in std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --in std_logic + pPsInc => pPsInc, --in std_logic + pPsEn => pPsEn, --in std_logic + PsClk => PsClk, --in std_logic + pPsDone => pPsDone, --out std_logic + FpgaClk_n => FpgaClk_n, --in std_logic + FpgaClk_p => FpgaClk_p, --in std_logic + RadioClk1x => SampleClk1xOutLcl, --out std_logic + RadioClk2x => SampleClk2xOut, --out std_logic + RadioClk3x => open); --out std_logic + + -- We need an internal copy of SampleClk1x for the TDC, since we don't want to try + -- and align the other DB's clock accidentally. + SampleClk1xOut <= SampleClk1xOutLcl; + + --vhook_e ClockingRegs + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bClockingRegPortOut + --vhook_a aRadioClksValid bRadioClksValid + ClockingRegsx: entity work.ClockingRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bClockingRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + pPsInc => pPsInc, --out std_logic + pPsEn => pPsEn, --out std_logic + pPsDone => pPsDone, --in std_logic + PsClk => PsClk, --out std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --out std_logic + aRadioClksValid => bRadioClksValid, --in std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --out std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --out std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --out std_logic + bJesdRefClkPresent => bJesdRefClkPresent); --in std_logic + + + + -- JESD204B : ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + bJesdRegPortInGrp <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kJesdRegGroupInDbRegs); -- 0x2000 to 0x3FFC + + -- Expand/compress the RegPort for moving through the netlist boundary. + bJesdRegPortOut <= Unflatten(bJesdCoreRegPortOutFlat); + bJesdCoreRegPortInFlat <= Flatten(bJesdRegPortInGrp); + + --vhook Jesd204bXcvrCore + --vhook_a bRegPortInFlat bJesdCoreRegPortInFlat + --vhook_a bRegPortOutFlat bJesdCoreRegPortOutFlat + --vhook_a FpgaClk1x SampleClk1x + --vhook_a FpgaClk2x SampleClk2x + --vhook_a ReliableClk40 Clk40 + --vhook_a CaptureSysRefClk SampleClk1xOutLcl + --vhook_a cSysRefFpgaLvds_p sSysRefFpgaLvds_p + --vhook_a cSysRefFpgaLvds_n sSysRefFpgaLvds_n + --vhook_a fSysRef sSysRefAsyncReset + --vhook_a fDacReadyForInput sDacReadyForInputAsyncReset + --vhook_a {^f(.*)} s$1 + Jesd204bXcvrCorex: Jesd204bXcvrCore + port map ( + bBusReset => bBusReset, --in STD_LOGIC + BusClk => BusClk, --in STD_LOGIC + ReliableClk40 => Clk40, --in STD_LOGIC + FpgaClk1x => SampleClk1x, --in STD_LOGIC + FpgaClk2x => SampleClk2x, --in STD_LOGIC + bFpgaClksStable => bFpgaClksStable, --in STD_LOGIC + bRegPortInFlat => bJesdCoreRegPortInFlat, --in STD_LOGIC_VECTOR(49:0) + bRegPortOutFlat => bJesdCoreRegPortOutFlat, --out STD_LOGIC_VECTOR(33:0) + aLmkSync => aLmkSync, --out STD_LOGIC + cSysRefFpgaLvds_p => sSysRefFpgaLvds_p, --in STD_LOGIC + cSysRefFpgaLvds_n => sSysRefFpgaLvds_n, --in STD_LOGIC + fSysRef => sSysRefAsyncReset, --out STD_LOGIC + CaptureSysRefClk => SampleClk1xOutLcl, --in STD_LOGIC + JesdRefClk_p => JesdRefClk_p, --in STD_LOGIC + JesdRefClk_n => JesdRefClk_n, --in STD_LOGIC + bJesdRefClkPresent => bJesdRefClkPresent, --out STD_LOGIC + aAdcRx_p => aAdcRx_p, --in STD_LOGIC_VECTOR(3:0) + aAdcRx_n => aAdcRx_n, --in STD_LOGIC_VECTOR(3:0) + aSyncAdcOut_n => aSyncAdcOut_n, --out STD_LOGIC + aDacTx_p => aDacTx_p, --out STD_LOGIC_VECTOR(3:0) + aDacTx_n => aDacTx_n, --out STD_LOGIC_VECTOR(3:0) + aSyncDacIn_n => aSyncDacIn_n, --in STD_LOGIC + fAdc0DataFlat => sAdc0DataFlat, --out STD_LOGIC_VECTOR(31:0) + fAdc1DataFlat => sAdc1DataFlat, --out STD_LOGIC_VECTOR(31:0) + fDac0DataFlat => sDac0DataFlat, --in STD_LOGIC_VECTOR(31:0) + fDac1DataFlat => sDac1DataFlat, --in STD_LOGIC_VECTOR(31:0) + fAdcDataValid => sAdcDataValid, --out STD_LOGIC + fDacReadyForInput => sDacReadyForInputAsyncReset, --out STD_LOGIC + aDacSync => aDacSync, --out STD_LOGIC + aAdcSync => aAdcSync); --out STD_LOGIC + + JesdDoubleSyncToNoResetSampleClk : process (SampleClk1x) + begin + if rising_edge(SampleClk1x) then + sDacReadyForInput_ms <= sDacReadyForInputAsyncReset; + sDacReadyForInputLcl <= sDacReadyForInput_ms; + -- No clock crossing here -- just reset, although the prefix declares otherwise... + sDacSync_ms <= aDacSync; + sDacSyncLcl <= sDacSync_ms; + sAdcSync_ms <= aAdcSync; + sAdcSyncLcl <= sAdcSync_ms; + sSysRef_ms <= sSysRefAsyncReset; + sSysRefLcl <= sSysRef_ms; + end if; + end process; + + -- Locals to outputs. + sDacReadyForInput <= sDacReadyForInputLcl; + sDacSync <= sDacSyncLcl; + sAdcSync <= sAdcSyncLcl; + sSysRef <= sSysRefLcl; + + -- Just combine the first two enables, since they're the ones that are used for JESD. + -- No reset crossing here, since bFpgaClksStable is only received by a no-reset domain + -- and the MGTs directly. + bFpgaClksStable <= bRadioClksValid and bRadioClk1xEnabled and bRadioClk2xEnabled; + + -- Compress/expand the flat data types from the netlist and route to top level. + sAdc0Data <= Unflatten(sAdc0DataFlat); + sAdc1Data <= Unflatten(sAdc1DataFlat); + sDac0DataFlat <= Flatten(sDac0Data); + sDac1DataFlat <= Flatten(sDac1Data); + + sAdcDataSamples0I <= sAdc0Data.I; + sAdcDataSamples0Q <= sAdc0Data.Q; + sAdcDataSamples1I <= sAdc1Data.I; + sAdcDataSamples1Q <= sAdc1Data.Q; + + sDac0Data.I <= sDacDataSamples0I; + sDac0Data.Q <= sDacDataSamples0Q; + sDac1Data.I <= sDacDataSamples1I; + sDac1Data.Q <= sDacDataSamples1Q; + + + -- Timing and Sync : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + bSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc0OffsetsInEndpoint); -- 0x0200 + + --vhook_e TdcWrapper + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a sPpsPulse sRegPps + TdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sRegPps, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + WrTdcGen: if kInclWhiteRabbitTdc = '1' generate + bWrSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc1OffsetsInEndpoint); -- 0x0400 + + --vhook_e TdcWrapper WrTdcWrapperx + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a bSyncRegPortIn bWrSyncRegPortIn + --vhook_a bSyncRegPortOut bWrSyncRegPortOut + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a RefClk WrRefClk + --vhook_a rPpsPulse rWrPpsPulse + --vhook_a sPpsPulse sWrPps + --vhook_a rRpTransfer rWrRpTransfer + --vhook_a sSpTransfer sWrSpTransfer + --vhook_a rGatedPulseToPin rWrGatedPulseToPin + --vhook_a sGatedPulseToPin sWrGatedPulseToPin + WrTdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => WrRefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bWrSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bWrSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rWrPpsPulse, --in std_logic + sPpsPulse => sWrPps, --out std_logic + rRpTransfer => rWrRpTransfer, --out std_logic + sSpTransfer => sWrSpTransfer, --out std_logic + rGatedPulseToPin => rWrGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sWrGatedPulseToPin); --inout std_logic + end generate WrTdcGen; + + WrTdcNotGen: if kInclWhiteRabbitTdc = '0' generate + bWrSyncRegPortOut <= kRegPortOutZero; + sWrPps <= '0'; + rWrRpTransfer <= '0'; + sWrSpTransfer <= '0'; + rWrGatedPulseToPin <= '0'; + sWrGatedPulseToPin <= '0'; + end generate WrTdcNotGen; + + -- Mux the output PPS based on the SFP selection bits. Encoding is one-hot, with zero + -- also a valid state. Regardless of whether the user selects SFP0 or SFP1 as the time + -- source, there is only one White Rabbit TDC, so '01' and '10' are equivalent. + -- '00': Use the PPS output from the "regular" TDC. + -- '01': Use the PPS output from the "white rabbit" TDC. + -- '10': Use the PPS output from the "white rabbit" TDC. + PpsOutputMux : process (SampleClk1xOutLcl) + begin + if rising_edge(SampleClk1xOutLcl) then + -- Double-sync the control bits to the Sample Clock domain. + sPpsSfpSel_ms <= aPpsSfpSel; + sPpsSfpSel <= sPpsSfpSel_ms; + + -- OR the control bits together to produce a single override enable for the WR TDC. + sUseWrTdcPps <= to_boolean(sPpsSfpSel(0) or sPpsSfpSel(1)); + + -- Flop the outputs. One flop for the PPS output IOB, the other for use internally. + sPpsInt <= sPpsMuxed; + end if; + end process PpsOutputMux; + + sPpsMuxed <= sWrPps when sUseWrTdcPps else sRegPps; + sPps <= sPpsInt; + sPpsToIob <= sPpsMuxed; -- No added flop here since there's an IOB outside this module. + + -- Daughterboard Control : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + --vhook_e DaughterboardRegs + --vhook_# Tying this low is safe because the sync reset is used inside DaughterboardRegs. + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bDbRegPortOut + --vhook_a kDbId std_logic_vector(to_unsigned(16#150#,16)) + DaughterboardRegsx: entity work.DaughterboardRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bDbRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + kDbId => std_logic_vector(to_unsigned(16#150#,16)), --in std_logic_vector(15:0) + kSlotId => kSlotId); --in std_logic + + +end RTL; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf Binary files differnew file mode 100644 index 000000000..27619d2a0 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd new file mode 100644 index 000000000..84c461d26 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd @@ -0,0 +1,56 @@ +-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016 +-- Date : Wed Jan 10 10:53:33 2018 +-- Host : djepson-lt running 64-bit major release (build 9200) +-- Command : write_vhdl -mode synth_stub -force -file ./Jesd204bXcvrCore_stub.vhd +-- Design : Jesd204bXcvrCore +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Jesd204bXcvrCore is + Port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR ( 49 downto 0 ); + bRegPortOutFlat : out STD_LOGIC_VECTOR ( 33 downto 0 ); + aLmkSync : out STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + CaptureSysRefClk : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aAdcRx_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aDacTx_n : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncDacIn_n : in STD_LOGIC; + fAdc0DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 ); + fAdc1DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 ); + fDac0DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 ); + fDac1DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 ); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC + ); + +end Jesd204bXcvrCore; + +architecture stub of Jesd204bXcvrCore is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "bBusReset,BusClk,ReliableClk40,FpgaClk1x,FpgaClk2x,bFpgaClksStable,bRegPortInFlat[49:0],bRegPortOutFlat[33:0],aLmkSync,cSysRefFpgaLvds_p,cSysRefFpgaLvds_n,fSysRef,CaptureSysRefClk,JesdRefClk_p,JesdRefClk_n,bJesdRefClkPresent,aAdcRx_p[3:0],aAdcRx_n[3:0],aSyncAdcOut_n,aDacTx_p[3:0],aDacTx_n[3:0],aSyncDacIn_n,fAdc0DataFlat[31:0],fAdc1DataFlat[31:0],fDac0DataFlat[31:0],fDac1DataFlat[31:0],fAdcDataValid,fDacReadyForInput,aDacSync,aAdcSync"; +begin +end; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd new file mode 100644 index 000000000..03b95c100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgClockingRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgClockingRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- RadioClkMmcm : 0x20 (ClockingRegs.vhd) + -- PhaseShiftControl : 0x24 (ClockingRegs.vhd) + -- RadioClkEnables : 0x28 (ClockingRegs.vhd) + -- MgtRefClkStatus : 0x30 (ClockingRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group ClockingRegs +--=============================================================================== + + -- RadioClkMmcm Register (from ClockingRegs.vhd) + constant kRadioClkMmcm : integer := 16#20#; -- Register Offset + constant kRadioClkMmcmSize: integer := 32; -- register width in bits + constant kRadioClkMmcmMask : std_logic_vector(31 downto 0) := X"00000013"; + constant kRadioClkMmcmResetSetSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSetMsb : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSet : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetClearSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClearMsb : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClear : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmLockedSize : integer := 1; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLockedMsb : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLocked : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + + -- PhaseShiftControl Register (from ClockingRegs.vhd) + constant kPhaseShiftControl : integer := 16#24#; -- Register Offset + constant kPhaseShiftControlSize: integer := 32; -- register width in bits + constant kPhaseShiftControlMask : std_logic_vector(31 downto 0) := X"10010011"; + constant kPsIncSize : integer := 1; --PhaseShiftControl:PsInc + constant kPsIncMsb : integer := 0; --PhaseShiftControl:PsInc + constant kPsInc : integer := 0; --PhaseShiftControl:PsInc + constant kPsDecSize : integer := 1; --PhaseShiftControl:PsDec + constant kPsDecMsb : integer := 4; --PhaseShiftControl:PsDec + constant kPsDec : integer := 4; --PhaseShiftControl:PsDec + constant kPsEnabledForFdbClkSize : integer := 1; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClkMsb : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClk : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsDoneSize : integer := 1; --PhaseShiftControl:PsDone + constant kPsDoneMsb : integer := 28; --PhaseShiftControl:PsDone + constant kPsDone : integer := 28; --PhaseShiftControl:PsDone + + -- RadioClkEnables Register (from ClockingRegs.vhd) + constant kRadioClkEnables : integer := 16#28#; -- Register Offset + constant kRadioClkEnablesSize: integer := 32; -- register width in bits + constant kRadioClkEnablesMask : std_logic_vector(31 downto 0) := X"00000111"; + constant kRadioClk1xEnabledSize : integer := 1; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabledMsb : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabled : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk2xEnabledSize : integer := 1; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabledMsb : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabled : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk3xEnabledSize : integer := 1; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabledMsb : integer := 8; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabled : integer := 8; --RadioClkEnables:RadioClk3xEnabled + + -- MgtRefClkStatus Register (from ClockingRegs.vhd) + constant kMgtRefClkStatus : integer := 16#30#; -- Register Offset + constant kMgtRefClkStatusSize: integer := 32; -- register width in bits + constant kMgtRefClkStatusMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kJesdRefClkPresentSize : integer := 1; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresentMsb : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresent : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + +end package; + +package body PkgClockingRegMap is + + -- function kRadioClkMmcmRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPhaseShiftControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRadioClkEnablesRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMgtRefClkStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd new file mode 100644 index 000000000..06708cde3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd @@ -0,0 +1,56 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgDaughterboardRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgDaughterboardRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- DaughterboardId : 0x630 (DaughterboardRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group StaticControl +--=============================================================================== + + -- DaughterboardId Register (from DaughterboardRegs.vhd) + constant kDaughterboardId : integer := 16#630#; -- Register Offset + constant kDaughterboardIdSize: integer := 32; -- register width in bits + constant kDaughterboardIdMask : std_logic_vector(31 downto 0) := X"0001ffff"; + constant kDbIdValSize : integer := 16; --DaughterboardId:DbIdVal + constant kDbIdValMsb : integer := 15; --DaughterboardId:DbIdVal + constant kDbIdVal : integer := 0; --DaughterboardId:DbIdVal + constant kSlotIdValSize : integer := 1; --DaughterboardId:SlotIdVal + constant kSlotIdValMsb : integer := 16; --DaughterboardId:SlotIdVal + constant kSlotIdVal : integer := 16; --DaughterboardId:SlotIdVal + +end package; + +package body PkgDaughterboardRegMap is + + -- function kDaughterboardIdRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd new file mode 100644 index 000000000..c0f5244b5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd @@ -0,0 +1,234 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgJesdConfig.vhd +-- Author: National Instruments +-- Original Project: NI 5840 +-- Date: 11 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: JESD204B setup constants and functions. These constants are shared +-- between RX and TX JESD cores. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgJesdConfig is + + -- "JESD" in ASCII - with the core number 0 or 1 on the LSb. + constant kJesdSignature : std_logic_vector(31 downto 0) := x"4a455344"; + + -- Register endpoints + constant kJesdDrpRegsInEndpoint : RegOffset_t := (kOffset => 16#0800#, -- 0x2800 to + kWidth => 16#0800#); -- 0x2FFF + + -- Selects the UsrClk2 for the transceivers. For 64-bit wide transceivers, the + -- UsrClk = 2*UserClk2 frequency. For 32-bit wide transceivers, UsrClk = UserClk2 + -- frequency. This is a generalization, the clock ratio should be confirmed based on + -- the transceiver configuration. + -- The N310 transceivers use the single rate reference, hence = false. + constant kDoubleRateUsrClk : boolean := false; + + -- For the N310, all lanes are in one quad and we use the QPLL. + constant kJesdUseQpll : boolean := true; + + constant kAdcDataWidth : integer := 16; -- ADC data width in bits + constant kDacDataWidth : integer := 16; -- DAC data width in bits + constant kSamplesPerCycle : integer := 1; -- Number of samples per SampleClk1x + + constant kGtxDrpAddrWidth : natural := 9; + constant kQpllDrpAddrWidth : natural := 8; + -- Max supported number of lanes + constant kMaxNumLanes : natural := 4; + -- Max supported number of quads (normally there is 1 quad per 4 lanes but disconnect + -- the definitions to allow quad sharing) + constant kMaxNumQuads : natural := 1; + + + -- JESD shared setup - LMFS = 4421, HD = 0 + constant kNumLanes : natural := 4; -- L + constant kNumConvs : positive := 4; -- M + constant kOctetsPerFrame : natural := 2; -- F + constant kDacJesdSamplesPerCycle : integer := 1; -- S + constant kOctetsPerLane : natural := 2; -- MGT data is kOctetsPerLane*8 = 16 bits wide + constant kNumQuads : natural := kNumLanes/4; -- 4 lanes per quad + constant kHighDensity : boolean := false; -- HD + constant kConvResBits : positive := kDacDataWidth-2; -- Converter resolution in bits + constant kConvSampleBits : positive := kDacDataWidth; -- Sample Length in bits + constant kInitLaneAlignCnt : positive := 4; + constant kFramesPerMulti : natural := 20; -- K + + -- In the N310 case we are one SPC, so this value is simply the number of frames + -- (samples) per multiframe. + constant kUserClksPerMulti : integer := kFramesPerMulti; + + + type NaturalVector is array ( natural range <>) of natural; + + -- The PCB connections are as follows: + -- + -- Transceiver MGT Channel ADC Lane DAC Lane + -- *********** *********** ******** ******** + -- GT0: X0Y8 0 0 0 + -- GT1: X0Y9 1 1 1 + -- GT2: X0Y10 2 2 2 + -- GT3: X0Y11 3 3 3 + constant kRxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => ADC (in above table) + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kTxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => DAC lane + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kLaneToQuadMap : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- All lanes are in one quad + 0 => 0, + 1 => 0, + 2 => 0, + 3 => 0 + ); + + + -- The master transceiver channel for channel bonding. E(kMasterBondingChannel) + -- must have the highest value decrementing to b"000" for that last channels to bond. + constant kMasterBondingChannel : integer := 1; + + -- Channel bonding occurs when a master detects a K-char sequence and aligns its + -- internal FIFO to the start of this sequence. A signal is then generated to other + -- slave transceivers that cause them to bond to the sequence - this bonding signal is + -- cascaded from master to slave to slave to slave, etc where each slave must know how + -- many levels to the master there are. The last slave to bond must be at level b"000" + -- and the master is at the highest level; the number of levels in the sequence is + -- governed by the size of the transceiver FIFO (see the Xilinx user guides for more + -- information). + type BondLevels_t is array(0 to kNumLanes - 1) of std_logic_vector(2 downto 0); + constant kBondLevel : BondLevels_t := ( + 0 => b"000", -- Control from 1 + 1 => b"001", -- Master + 2 => b"000", -- Control from 1 + 3 => b"000" -- Control from 1 + ); + + -- Option to pipeline stages to improve timing, if needed + constant kPipelineDetectCharsStage : boolean := false; + constant kPipelineCharReplStage : boolean := false; + + + -- ADC & DAC Data Types + -- + + -- ADC Words from JESD204B RX Core. The array is 4 elements wide to accommodate the + -- I & Q elements from both RX channels. + subtype AdcWord_t is std_logic_vector(kAdcDataWidth - 1 downto 0); + type AdcWordArray_t is array(4 - 1 downto 0) of AdcWord_t; + + -- Data types for manipulation and presentation to outside world. + type AdcData_t is record + I : std_logic_vector(kAdcDataWidth - 1 downto 0); + Q : std_logic_vector(kAdcDataWidth - 1 downto 0); + end record; + + type DacData_t is record + I : std_logic_vector(kDacDataWidth - 1 downto 0); + Q : std_logic_vector(kDacDataWidth - 1 downto 0); + end record; + + + -- Flattened data types for passing into and out of pre-synthesized components. + subtype AdcDataFlat_t is std_logic_vector(2*kAdcDataWidth - 1 downto 0); + subtype DacDataFlat_t is std_logic_vector(2*kDacDataWidth - 1 downto 0); + + -- Functions to convert to/from types defined above. + function Flatten (AdcData : AdcData_t) return AdcDataFlat_t; + function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t; + + function Flatten (DacData : DacData_t) return DacDataFlat_t; + function Unflatten(DacData : DacDataFlat_t) return DacData_t; + + +end package; + + +package body PkgJesdConfig is + + + + + + -- Flattens AdcData_t to AdcDataFlat_t + function Flatten (AdcData : AdcData_t) return AdcDataFlat_t + is + variable ReturnVar : AdcDataFlat_t; + begin + ReturnVar := (others => '0'); + -- MSB is I + ReturnVar := AdcData.I & AdcData.Q; + return ReturnVar; + end function Flatten; + + + -- UnFlattens AdcDataFlat_t to AdcData_t + function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t + is + variable ReturnVar : AdcData_t; + begin + ReturnVar := (others => (others => '0')); + -- MSB is I + ReturnVar.I := AdcData(2*kAdcDataWidth - 1 downto kAdcDataWidth); + ReturnVar.Q := AdcData( kAdcDataWidth - 1 downto 0); + return ReturnVar; + end function Unflatten; + + + + -- Flattens DacData_t to DacDataFlat_t + function Flatten (DacData : DacData_t) return DacDataFlat_t + is + variable ReturnVar : DacDataFlat_t; + begin + ReturnVar := (others => '0'); + -- MSB is I + ReturnVar := DacData.I & DacData.Q; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataFlat_t to DacData_t + function Unflatten(DacData : DacDataFlat_t) return DacData_t + is + variable ReturnVar : DacData_t; + begin + ReturnVar := (others => (others => '0')); + -- MSB is I + ReturnVar.I := DacData(2*kDacDataWidth - 1 downto kDacDataWidth); + ReturnVar.Q := DacData( kDacDataWidth - 1 downto 0); + return ReturnVar; + end function Unflatten; + + + + + +end package body;
\ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd new file mode 100644 index 000000000..904653a8e --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgMgPersonality.vhd +-- Author: National Instruments +-- Original Project: N310 +-- Date: 13 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: This package contains constants and helpful functions that enable +-- the FPGA to be compiled with different features. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgMgPersonality is + + + -- RegPort Address Definitions : ------------------------------------------------------ + -- + -- DB Regs ... + -- + -- Clocking Offset: 0x 000 Width: 0x 200 + -- Tdco0 Offset: 0x 200 Width: 0x 200 + -- Tdco1 Offset: 0x 400 Width: 0x 200 + -- Daughterboard Ctrl Offset: 0x 600 Width: 0x 200 + -- Total: 0x2000 + -- JESD 2x - A Offset: 0x2000 Width: 0x1000 + -- JESD 2x - B Offset: 0x3000 Width: 0x1000 + -- Total: 0x4000 + -- Total: 0x8000 for two DBs + -- ------------------------------------------------------------------------------------ + + -- A single RegPort runs to the JESD204B Core. + constant kJesdRegGroupInDbRegs : RegOffset_t := (kOffset => 16#2000#, -- 0x2000 to + kWidth => 16#1000#); -- 0x2FFF + + -- DB Regs : -------------------------------------------------------------------------- + constant kClockingOffsetInEndpoint : RegOffset_t := (kOffset => 16#0000#, -- 0x0000 to + kWidth => 16#0200#); -- 0x01FF + constant kTdc0OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0200#, -- 0x0200 to + kWidth => 16#0200#); -- 0x03FF + constant kTdc1OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0400#, -- 0x0400 to + kWidth => 16#0200#); -- 0x05FF + constant kDaughterboardOffsetInEndpoint : RegOffset_t := (kOffset => 16#0600#, -- 0x0600 to + kWidth => 16#0200#); -- 0x07FF + + + + +end package PkgMgPersonality; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd new file mode 100644 index 000000000..ee0da9f84 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd @@ -0,0 +1,304 @@ +------------------------------------------------------------------------------- +-- +-- File: RadioClocking.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 February 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Instantiates a MMCM to produce 1x, 2x, and 3x versions of the Radio Clock +-- coming from the FPGA input pin. Handles all the buffering for the input clock. +-- Additionally allows the clocks to be turned on and off, and phase shifted. +-- +-- NOTE: This module hard-codes the MMCM settings for a SPECIFIC clock rate! +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library unisim; + use unisim.vcomponents.all; + + +entity RadioClocking is + port ( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + + -- Should be a always-on clock + BusClk : in std_logic; + + -- Sync reset to the RadioClkMmcm. + bRadioClkMmcmReset : in std_logic; + + -- Locked indication from the RadioClkMmcm in BusClk and aReset domains. + bRadioClksValid : out std_logic; + + bRadioClk1xEnabled : in std_logic; + bRadioClk2xEnabled : in std_logic; + bRadioClk3xEnabled : in std_logic; + + -- Phase shift interface for the RadioClkMmcm. PsClk must be <= 200 MHz. + pPsInc : in std_logic; + pPsEn : in std_logic; + PsClk : in std_logic; + pPsDone : out std_logic; + + -- Straight from pins. Buffer included in here. + FpgaClk_n : in std_logic; + FpgaClk_p : in std_logic; + + RadioClk1x : out std_logic; + RadioClk2x : out std_logic; + RadioClk3x : out std_logic + + ); +end RadioClocking; + + +architecture rtl of RadioClocking is + + --vhook_sigstart + signal RadioClk1xLcl: std_logic; + signal RadioClk1xPll: std_logic; + signal RadioClk2xLcl: std_logic; + signal RadioClk2xPll: std_logic; + signal RadioClk3xLcl: std_logic; + signal RadioClk3xPll: std_logic; + --vhook_sigend + + signal RadioClkMmcmFeedbackIn, + RadioClkMmcmFeedbackOut, + FpgaClkSE, + aRadioClkMmcmLocked : std_logic; + + signal bRadioClkMmcmLocked_ms, + bRadioClkMmcmLocked, + bEnableRadioClkBufgOutputs, + bEnableRadioClk1xBufgOutput, + bEnableRadioClk2xBufgOutput, + bEnableRadioClk3xBufgOutput : std_logic := '0'; + + signal aRadioClkMmcmResetInternal : std_logic := '1'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClkMmcmLocked_ms : signal is "true"; + attribute ASYNC_REG of bRadioClkMmcmLocked : signal is "true"; + +begin + + -- Radio Clock Buffering : ------------------------------------------------------------ + -- + -- ------------------------------------------------------------------------------------ + --vhook_i IBUFDS FpgaClkIbufg hidegeneric=true + --vhook_a I FpgaClk_p + --vhook_a IB FpgaClk_n + --vhook_a O FpgaClkSE + FpgaClkIbufg: IBUFDS + port map ( + O => FpgaClkSE, --out std_ulogic + I => FpgaClk_p, --in std_ulogic + IB => FpgaClk_n); --in std_ulogic + + ResetDelay : process(aReset, BusClk) + begin + if aReset then + aRadioClkMmcmResetInternal <= '1'; + elsif rising_edge(BusClk) then + if bReset then + aRadioClkMmcmResetInternal <= '1'; + else + -- Delay by 1 to allow the BUFGs to turn off before the MMCM is reset. + aRadioClkMmcmResetInternal <= bRadioClkMmcmReset; + end if; + end if; + end process ResetDelay; + + + RadioClkMmcm: MMCME2_ADV + generic map( + COMPENSATION => "ZHOLD", + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 6.000, -- Feedback + CLKOUT0_DIVIDE_F => 6.000, -- Data Clock 1x, RadioClk1xPll + CLKOUT1_DIVIDE => 3, -- Data Clock 2x, RadioClk2xPll + CLKOUT2_DIVIDE => 2, -- Data Clock 3x, RadioClk3xPll + CLKOUT3_DIVIDE => 1, -- unused + CLKOUT4_DIVIDE => 1, -- unused + CLKOUT5_DIVIDE => 1, -- unused + CLKOUT6_DIVIDE => 1, -- unused + CLKFBOUT_PHASE => 0.000, -- Feedback + CLKOUT0_PHASE => 0.000, -- Data Clock 1x + CLKOUT1_PHASE => 0.000, -- Data Clock 2x + CLKOUT2_PHASE => 0.000, -- Data Clock 3x + CLKOUT3_PHASE => 0.000, -- unused + CLKOUT4_PHASE => 0.000, -- unused + CLKOUT5_PHASE => 0.000, -- unused + CLKOUT6_PHASE => 0.000, -- unused + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT4_DUTY_CYCLE => 0.500, + CLKOUT5_DUTY_CYCLE => 0.500, + CLKOUT6_DUTY_CYCLE => 0.500, + DIVCLK_DIVIDE => 1, + REF_JITTER1 => 0.010, + CLKIN1_PERIOD => 6.510, -- 153.6 MHz max + CLKFBOUT_USE_FINE_PS => true, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_USE_FINE_PS => false, + STARTUP_WAIT => false, + CLKOUT4_CASCADE => false) + port map ( + CLKINSEL => '1', + CLKIN1 => FpgaClkSE, + CLKIN2 => '0', + CLKFBIN => RadioClkMmcmFeedbackIn, + RST => aRadioClkMmcmResetInternal, + PWRDWN => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DWE => '0', + DEN => '0', + DCLK => '0', + DO => open, + DRDY => open, + PSINCDEC => pPsInc, + PSEN => pPsEn, + PSCLK => PsClk, + PSDONE => pPsDone, + CLKOUT0 => RadioClk1xPll, + CLKOUT0B => open, + CLKOUT1 => RadioClk2xPll, + CLKOUT1B => open, + CLKOUT2 => RadioClk3xPll, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBOUT => RadioClkMmcmFeedbackOut, + CLKFBOUTB => open, + LOCKED => aRadioClkMmcmLocked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open); + + RadioClkMmcmFeedbackBufg: BUFG + port map ( + I => RadioClkMmcmFeedbackOut, + O => RadioClkMmcmFeedbackIn + ); + + + -- Only enable the WRAPBUFGs when the MMCM is locked. If the MMCM is ever placed in + -- reset, we turn off the clocks one cycle before the asynchronous version + -- (aRadioClkMmcmResetInternal) reaches the MMCM inputs in order to prevent + -- output glitches. + CombineEnablesForBuffers : process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + elsif rising_edge(BusClk) then + if bReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + else + bRadioClkMmcmLocked_ms <= aRadioClkMmcmLocked; + bRadioClkMmcmLocked <= bRadioClkMmcmLocked_ms; + + bEnableRadioClkBufgOutputs <= bRadioClkMmcmLocked and + not bRadioClkMmcmReset; + bEnableRadioClk1xBufgOutput <= bRadioClk1xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk2xBufgOutput <= bRadioClk2xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk3xBufgOutput <= bRadioClk3xEnabled and bEnableRadioClkBufgOutputs; + end if; + end if; + end process CombineEnablesForBuffers; + + bRadioClksValid <= bEnableRadioClkBufgOutputs; + + --vhook_e WrapBufg RadioClk1xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk1xPll + --vhook_a aCe bEnableRadioClk1xBufgOutput + --vhook_a ClkOut RadioClk1xLcl + RadioClk1xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk1xPll, --in std_logic + aCe => bEnableRadioClk1xBufgOutput, --in std_logic + ClkOut => RadioClk1xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk2xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk2xPll + --vhook_a aCe bEnableRadioClk2xBufgOutput + --vhook_a ClkOut RadioClk2xLcl + RadioClk2xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk2xPll, --in std_logic + aCe => bEnableRadioClk2xBufgOutput, --in std_logic + ClkOut => RadioClk2xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk3xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk3xPll + --vhook_a aCe bEnableRadioClk3xBufgOutput + --vhook_a ClkOut RadioClk3xLcl + RadioClk3xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk3xPll, --in std_logic + aCe => bEnableRadioClk3xBufgOutput, --in std_logic + ClkOut => RadioClk3xLcl); --out std_logic + + + -- Assign outputs from locals. + RadioClk1x <= RadioClk1xLcl; + RadioClk2x <= RadioClk2xLcl; + RadioClk3x <= RadioClk3xLcl; + + + +end rtl; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc new file mode 100644 index 000000000..142ba9ab4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc @@ -0,0 +1,347 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "/n3xx/dboards/mg/doc/mg_timing.xlsx". See +# the spreadsheet for more details and explanations. + +#******************************************************************************* +## Daughterboard Clocks + +# 122.88, 125, and 153.6 MHz Sample Clocks are allowable. Constrain the paths to the max +# rate in order to support all rates in a single FPGA image. +set SAMPLE_CLK_PERIOD 6.510 +create_clock -name fpga_clk_a -period $SAMPLE_CLK_PERIOD [get_ports DBA_FPGA_CLK_P] +create_clock -name fpga_clk_b -period $SAMPLE_CLK_PERIOD [get_ports DBB_FPGA_CLK_P] +create_clock -name mgt_clk_dba -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_A_MGTCLK_P] +create_clock -name mgt_clk_dbb -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_B_MGTCLK_P] + +# The Radio Clocks coming from the DBs are synchronized together (at the ADCs) to a +# typical value of less than 100ps. To give ourselves and Vivado some margin, we claim +# here that the DB-B Radio Clock can arrive 500ps before or after the DB-A clock at +# the FPGA (note that the trace lengths of the Radio Clocks coming from the DBs to the +# FPGA are about 0.5" different, thereby incurring ~80ps of additional skew at the FPGA). +# There is one spot in the FPGA where we cross domains between the DB-A and +# DB-B clock, so we must ensure that Vivado can analyze that path safely. +set FPGA_CLK_EARLY -0.5 +set FPGA_CLK_LATE 0.5 +set_clock_latency -source -early $FPGA_CLK_EARLY [get_clocks fpga_clk_b] +set_clock_latency -source -late $FPGA_CLK_LATE [get_clocks fpga_clk_b] + +# Virtual clocks for constraining I/O (used below) +create_clock -name fpga_clk_a_v -period $SAMPLE_CLK_PERIOD +create_clock -name fpga_clk_b_v -period $SAMPLE_CLK_PERIOD + +# The set_clock_latency constraints set on fpga_clk_b are problematic when used with +# I/O timing, since the analyzer gives us a double-hit on the latency. One workaround +# (used here) is to simply swap the early and late times for the virtual clock so that +# it cancels out the source latency during analysis. I tested this by setting the +# early and late numbers to zero and then their actual value, running timing reports +# on each. The slack report matches for both cases, showing that the reversed early/late +# numbers on the virtual clock zero out the latency effects on the actual clock. +# +# Note this is not a problem for the fpga_clk_a, since no latency is added. So only apply +# it to fpga_clk_b_v. +set_clock_latency -source -early $FPGA_CLK_LATE [get_clocks fpga_clk_b_v] +set_clock_latency -source -late $FPGA_CLK_EARLY [get_clocks fpga_clk_b_v] + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + +create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + + + +#******************************************************************************* +## Generated clocks for output busses to the daughterboard +# +# These clock definitions need to come above the set_clock_groups commands below to work! + +# Define clocks on the PL SPI clock output pins for both DBs. Actual divider values are +# set by SW at run-time. Divider values are 123, 125, or 154 based on what radio clock +# rate is set. To be ultra-conservative (which still provides 10s of ns of slack), we +# set an over-constrained divider value of 50. +set PL_SPI_DIVIDE_VAL 50 +set PL_SPI_CLK_A [get_ports DBA_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_a \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_A +set PL_SPI_CLK_B [get_ports DBB_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_b \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_B + +# Define one of the outputs of each bus as a clock (even though it isn't a clock). This +# allows us to constrain the overall bus skew with respect to one of the bus outputs. +# See the remainder of this constraint below for more details. +set DSA_CLK [get_ports {DBA_CH1_RX_DSA_DATA[0]}] +create_generated_clock -name dsa_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $DSA_CLK]/C] \ + -divide_by 2 $DSA_CLK + +set ATR_CLK [get_ports DBA_ATR_RX_1] +create_generated_clock -name atr_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $ATR_CLK]/C] \ + -divide_by 2 $ATR_CLK + +# Interface Unused +# set MGPIO_CLK [get_ports DBA_MYK_GPIO_0] +# create_generated_clock -name myk_gpio_bus_clk \ + # -source [get_pins [all_fanin -flat -only_cells -startpoints_only [get_ports $MGPIO_CLK]]/C] \ + # -divide_by 2 [get_ports $MGPIO_CLK] + + + +#******************************************************************************* +## Asynchronous clock groups + +# MGT reference clocks are also async to everything. +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dba -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dbb -include_generated_clocks] + +# fpga_clk_a and fpga_clk_b are related to one another after synchronization. +# However, we do need to declare that these clocks (both a and b) and their children +# are async to the remainder of the design. Use the wildcard at the end to grab the +# virtual clock as well as the real ones. +set_clock_groups -asynchronous -group [get_clocks {fpga_clk_a* fpga_clk_b*} -include_generated_clocks] + + + +#******************************************************************************* +## PS SPI: since these lines all come from the PS and I don't have access to the +# driving clock (or anything for that matter), I'm left with constraining the maximum +# and minimum delay on these lines, per a Xilinx AR: +# https://www.xilinx.com/support/answers/62122.html +set CPLD_SPI_OUTS [get_ports {DB*_CPLD_PS_SPI_SCLK \ + DB*_CPLD_PS_SPI_SDI \ + DB*_CPLD_PS_SPI_LE \ + DB*_CPLD_PS_SPI_ADDR[0] \ + DB*_CPLD_PS_SPI_ADDR[1]}] + +set_max_delay 12.0 -to $CPLD_SPI_OUTS +set_min_delay 3.0 -to $CPLD_SPI_OUTS + +set MYK_SPI_OUTS [get_ports {DB*_MYK_SPI_SCLK \ + DB*_MYK_SPI_SDIO \ + DB*_MYK_SPI_CS_n}] + +set_max_delay 14.0 -to $MYK_SPI_OUTS +set_min_delay 3.0 -to $MYK_SPI_OUTS + +# report_timing -to $CPLD_SPI_OUTS -max_paths 20 -delay_type min_max -name CpldSpiOutTiming +# report_timing -to $MYK_SPI_OUTS -max_paths 20 -delay_type min_max -name MykSpiOutTiming + +set MIN_IN_DELAY 2.0 +set MAX_IN_DELAY 10.0 + +set PS_SPI_INPUTS_0 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI0MI"}] +set PS_SPI_INPUTS_1 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI1MI"}] + +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_0 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_0 +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_1 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_1 + +# report_timing -to $PS_SPI_INPUTS_0 -max_paths 30 -delay_type min_max -nworst 30 -name Spi0InTiming +# report_timing -to $PS_SPI_INPUTS_1 -max_paths 30 -delay_type min_max -nworst 30 -name Spi1InTiming + + + +#******************************************************************************* +## PL SPI to the CPLD +# +# All of these lines are driven or received from flops in simple_spi_core. The CPLD +# calculations assume the FPGA has less than 20 ns of skew between the SCK and +# SDI/CS_n. Pretty easy constraint to write! See above for the clock definition. +# Do this for DBA and DBB independently. +set MAX_SKEW 20.0 +set SETUP_SKEW [expr {$MAX_SKEW / 2}] +set HOLD_SKEW [expr {$MAX_SKEW / 2}] +# Do not set the output delay constraint on the clock line! +set PORT_LIST_A [get_ports {DBA_CPLD_PL_SPI_LE \ + DBA_CPLD_PL_SPI_SDI \ + DBA_CPLD_PL_SPI_ADDR[0] \ + DBA_CPLD_PL_SPI_ADDR[1]}] +set PORT_LIST_B [get_ports {DBB_CPLD_PL_SPI_LE \ + DBB_CPLD_PL_SPI_SDI \ + DBB_CPLD_PL_SPI_ADDR[0] \ + DBB_CPLD_PL_SPI_ADDR[1]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -1 +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -1 + +# For SDO input timing (MISO), we need to look at the CPLD's constraints on turnaround +# time plus any board propagation delay. +set MISO_INPUT_A [get_ports DBA_CPLD_PL_SPI_SDO] +set MISO_INPUT_B [get_ports DBB_CPLD_PL_SPI_SDO] +set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -max 68.041 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -min 12.218 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -max 68.041 $MISO_INPUT_B +set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -min 12.218 $MISO_INPUT_B +# Since the input delay span is clearly more than a period of the radio_clk, we need to +# add a multicycle path here as well to define the clock divider ratio. The MISO data +# is driven on the falling edge of the SPI clock and captured on the rising edge, so we +# only have one half of a SPI clock cycle for our setup. Hold is left alone and is OK +# as-is due to the delays in the CPLD and board. +set SETUP_CYCLES [expr {$PL_SPI_DIVIDE_VAL / 2}] +set HOLD_CYCLES 0 +set_multicycle_path -setup -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] +set_multicycle_path -setup -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] + +# One of the PL_SPI_ADDR lines is used instead for the LMK SYNC strobe. This line is +# driven asynchronously. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_CPLD_PL_SPI_ADDR[2]] +set_max_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 50.000 +set_min_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 0.000 + + + +#******************************************************************************* +## DSA Bus +# The DSA controls are driven from the DB-A radio clock. Although they are received async +# at the DSAs, they should be tightly constrained in the FPGA to arrive as closely as +# possible. The best way to do this is a skew constraint across all the bits. +set MAX_SKEW 2.5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set PORT_LIST [get_ports {DB*_CH*_*X_DSA_DATA[*]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +# The clock, which is essentially one of the data lines, should arrive at the pin +# +/- MAX_DELAY compared to the other data lines, so setup and hold checks need to be +# relative to the SAME edges for both the clock and the data. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $DSA_CLK +set_max_delay -to $DSA_CLK 50.000 +set_min_delay -to $DSA_CLK 0.000 + + + +#******************************************************************************* +## ATR Bus +# The ATR bits are driven from the DB-A radio clock. Although they are received async in +# the CPLD, they should be tightly constrained in the FPGA to avoid any race conditions. +# The best way to do this is a skew constraint across all the bits. +set MAX_SKEW 2.5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set PORT_LIST [get_ports DB*_ATR_*X_*] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -to [get_clocks atr_bus_clk] -start 0 +set_multicycle_path -hold -to [get_clocks atr_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $ATR_CLK +set_max_delay -to $ATR_CLK 50.000 +set_min_delay -to $ATR_CLK 0.000 + + + +#******************************************************************************* +## Mykonos Ports +# Mykonos GPIO is driven from the DB-A radio clock. Although they are received async in +# Mykonos, they should be tightly constrained in the FPGA to avoid any race conditions. +# The best way to do this is a skew constraint across all the bits. +# set MAX_SKEW 2.5 +# set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +# set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +# set PORT_LIST [get_ports DB*_ATR_*X_*] +# # Then add the output delay on each of the ports. +# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# # Finally, make both the setup and hold checks use the same launching and latching edges. +# set_multicycle_path -setup -to [get_clocks myk_gpio_bus_clk] -start 0 +# set_multicycle_path -hold -to [get_clocks myk_gpio_bus_clk] -1 +# # Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# # they aren't supported in XDC files... so we do it the old fashioned way. +# set_output_delay -clock [get_clocks async_out_clk] 0.000 $MGPIO_CLK +# set_max_delay -to $MGPIO_CLK 50.000 +# set_min_delay -to $MGPIO_CLK 0.000 + +# Mykonos Interrupt is received asynchronously, and driven directly to the PS. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_INTRQ] +set_max_delay -from [get_ports DB*_MYK_INTRQ] 50.000 +set_min_delay -from [get_ports DB*_MYK_INTRQ] 0.000 + + + +#******************************************************************************* +## SYSREF/SYNC JESD Timing +# +# SYNC is async, SYSREF is tightly timed. + +# The SYNC output for both DBs is governed by the JESD cores, which are solely driven by +# DB-A clock... but it is an asynchronous signal so we use the async_out_clk. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_MYK_SYNC_IN_n] +set_max_delay -to [get_ports DB*_MYK_SYNC_IN_n] 50.000 +set_min_delay -to [get_ports DB*_MYK_SYNC_IN_n] 0.000 + +# The SYNC input for both DBs is received by the DB-A clock inside the JESD cores... but +# again, it is asynchronous and therefore uses the async_in_clk. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_SYNC_OUT_n] +set_max_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 50.000 +set_min_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 0.000 + +# SYSREF is driven by the LMK directly to the FPGA. Timing analysis was performed once +# for the worst-case numbers across both DBs to produce one set of numbers for both DBs. +# Since we easily meet setup and hold in Vivado, then this is an acceptable approach. +# SYSREF is captured by the local clock from each DB, so we have two sets of constraints. +set_input_delay -clock fpga_clk_a_v -min -0.906 [get_ports DBA_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_a_v -max 0.646 [get_ports DBA_FPGA_SYSREF_*] + +set_input_delay -clock fpga_clk_b_v -min -0.906 [get_ports DBB_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_b_v -max 0.646 [get_ports DBB_FPGA_SYSREF_*] + + + +#******************************************************************************* +## PPS Timing + +# Due to the N3xx synchronization and clocking structure, the PPS output is driven from +# the Sample Clock domain instead of the input Reference Clock. Constrain the output as +# tightly as possible to accurately mimic the internal Sample Clock timing. +set SETUP_SKEW 2.0 +set HOLD_SKEW -0.5 +set_output_delay -clock [get_clocks fpga_clk_a_v] -max -$SETUP_SKEW [get_ports REF_1PPS_OUT] +set_output_delay -clock [get_clocks fpga_clk_a_v] -min $HOLD_SKEW [get_ports REF_1PPS_OUT] +set_multicycle_path -setup -to [get_ports REF_1PPS_OUT] -start 0 +set_multicycle_path -hold -to [get_ports REF_1PPS_OUT] -1 diff --git a/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md b/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md new file mode 100644 index 000000000..2071c46ba --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md @@ -0,0 +1,2 @@ +Timing closure of the CPLD design relies on the pre-set seed value. The build +requires Quartus 16.1.2. diff --git a/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx b/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx Binary files differnew file mode 100644 index 000000000..c4ad8ac5c --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx diff --git a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v new file mode 100644 index 000000000..32fa84153 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v @@ -0,0 +1,3915 @@ +/////////////////////////////////////////////////////////////////// +/// +// Copyright 2016-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx +// Description: +// Top Level for N3xx devices +// +////////////////////////////////////////////////////////////////////// + +module n3xx ( + inout [11:0] FPGA_GPIO, + + input FPGA_REFCLK_P, + input FPGA_REFCLK_N, + input REF_1PPS_IN, + input NETCLK_REF_P, + input NETCLK_REF_N, + //input REF_1PPS_IN_MGMT, + output REF_1PPS_OUT, + + //TDC + inout UNUSED_PIN_TDCA_0, + inout UNUSED_PIN_TDCA_1, + inout UNUSED_PIN_TDCA_2, + inout UNUSED_PIN_TDCA_3, + inout UNUSED_PIN_TDCB_0, + inout UNUSED_PIN_TDCB_1, + inout UNUSED_PIN_TDCB_2, + inout UNUSED_PIN_TDCB_3, + +`ifdef NPIO_LANES + input NPIO_RX0_P, + input NPIO_RX0_N, + output NPIO_TX0_P, + output NPIO_TX0_N, + input NPIO_RX1_P, + input NPIO_RX1_N, + output NPIO_TX1_P, + output NPIO_TX1_N, +`endif +`ifdef QSFP_LANES + input [`QSFP_LANES-1:0] QSFP_RX_P, + input [`QSFP_LANES-1:0] QSFP_RX_N, + output [`QSFP_LANES-1:0] QSFP_TX_P, + output [`QSFP_LANES-1:0] QSFP_TX_N, + output QSFP_RESET_B, + output QSFP_LED, + output QSFP_MODSEL_B, + output QSFP_LPMODE, + input QSFP_PRESENT_B, + input QSFP_INT_B, + inout QSFP_I2C_SCL, + inout QSFP_I2C_SDA, +`endif + //TODO: Uncomment when connected here + //input NPIO_0_RXSYNC_0_P, NPIO_0_RXSYNC_1_P, + //input NPIO_0_RXSYNC_0_N, NPIO_0_RXSYNC_1_N, + //output NPIO_0_TXSYNC_0_P, NPIO_0_TXSYNC_1_P, + //output NPIO_0_TXSYNC_0_N, NPIO_0_TXSYNC_1_N, + //input NPIO_1_RXSYNC_0_P, NPIO_1_RXSYNC_1_P, + //input NPIO_1_RXSYNC_0_N, NPIO_1_RXSYNC_1_N, + //output NPIO_1_TXSYNC_0_P, NPIO_1_TXSYNC_1_P, + //output NPIO_1_TXSYNC_0_N, NPIO_1_TXSYNC_1_N, + //input NPIO_2_RXSYNC_0_P, NPIO_2_RXSYNC_1_P, + //input NPIO_2_RXSYNC_0_N, NPIO_2_RXSYNC_1_N, + //output NPIO_2_TXSYNC_0_P, NPIO_2_TXSYNC_1_P, + //output NPIO_2_TXSYNC_0_N, NPIO_2_TXSYNC_1_N, + + //GPS + input GPS_1PPS, + //input GPS_1PPS_RAW, + + //Misc + input ENET0_CLK125, + //inout ENET0_PTP, + //output ENET0_PTP_DIR, + //inout ATSHA204_SDA, + input FPGA_PL_RESETN, // TODO: Add to reset logic + // output reg [1:0] FPGA_TEST, + //input PWR_CLK_FPGA, // TODO: check direction + input FPGA_PUDC_B, + + //White Rabbit + input WB_20MHZ_P, + input WB_20MHZ_N, + output WB_DAC_DIN, + output WB_DAC_NCLR, + output WB_DAC_NLDAC, + output WB_DAC_NSYNC, + output WB_DAC_SCLK, + + //LEDS + output PANEL_LED_GPS, + output PANEL_LED_LINK, + output PANEL_LED_PPS, + output PANEL_LED_REF, + + // ARM Connections (PS) + inout [53:0] MIO, + inout PS_SRSTB, + inout PS_CLK, + inout PS_PORB, + inout DDR_Clk, + inout DDR_Clk_n, + inout DDR_CKE, + inout DDR_CS_n, + inout DDR_RAS_n, + inout DDR_CAS_n, + inout DDR_WEB, + inout [2:0] DDR_BankAddr, + inout [14:0] DDR_Addr, + inout DDR_ODT, + inout DDR_DRSTB, + inout [31:0] DDR_DQ, + inout [3:0] DDR_DM, + inout [3:0] DDR_DQS, + inout [3:0] DDR_DQS_n, + inout DDR_VRP, + inout DDR_VRN, + + + /////////////////////////////////// + // + // High Speed SPF+ signals and clocking + // + /////////////////////////////////// + + // These clock inputs must always be enabled with a buffer regardless of the build + // target to avoid damage to the FPGA. + input NETCLK_P, + input NETCLK_N, + input MGT156MHZ_CLK1_P, + input MGT156MHZ_CLK1_N, + + input SFP_0_RX_P, input SFP_0_RX_N, + output SFP_0_TX_P, output SFP_0_TX_N, + input SFP_1_RX_P, input SFP_1_RX_N, + output SFP_1_TX_P, output SFP_1_TX_N, + + + /////////////////////////////////// + // + // DRAM Interface + // + /////////////////////////////////// + inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_p, + // + output [15:0] ddr3_addr, // Address + output [2:0] ddr3_ba, // Bank Address + output ddr3_ras_n, // Row Address Strobe. + output ddr3_cas_n, // Column address select + output ddr3_we_n, // Write Enable + output ddr3_reset_n, // SDRAM reset pin. + output [0:0] ddr3_ck_p, // Differential clock + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, // Clock Enable + output [0:0] ddr3_cs_n, // Chip Select + output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... + output [0:0] ddr3_odt, // On-Die termination enable. + // + input sys_clk_p, // Differential + input sys_clk_n, // 100MHz clock source to generate DDR3 clocking. + + + /////////////////////////////////// + // + // Supporting I/O for SPF+ interfaces + // (non high speed stuff) + // + /////////////////////////////////// + + //SFP+ 0, Slow Speed, Bank 13 3.3V + input SFP_0_I2C_NPRESENT, + output SFP_0_LED_A, + output SFP_0_LED_B, + input SFP_0_LOS, + output SFP_0_RS0, + output SFP_0_RS1, + output SFP_0_TXDISABLE, + input SFP_0_TXFAULT, + + //SFP+ 1, Slow Speed, Bank 13 3.3V + //input SFP_1_I2C_NPRESENT, + output SFP_1_LED_A, + output SFP_1_LED_B, + input SFP_1_LOS, + output SFP_1_RS0, + output SFP_1_RS1, + output SFP_1_TXDISABLE, + input SFP_1_TXFAULT, + + //USRP IO A + output DBA_CPLD_PS_SPI_SCLK, + output DBA_CPLD_PS_SPI_LE, + output DBA_CPLD_PS_SPI_SDI, + input DBA_CPLD_PS_SPI_SDO, + output [1:0] DBA_CPLD_PS_SPI_ADDR, + + output DBA_ATR_RX_1, + output DBA_ATR_RX_2, + output DBA_ATR_TX_1, + output DBA_ATR_TX_2, + + output [5:0] DBA_CH1_TX_DSA_DATA, + output [5:0] DBA_CH1_RX_DSA_DATA, + output [5:0] DBA_CH2_TX_DSA_DATA, + output [5:0] DBA_CH2_RX_DSA_DATA, + + output DBA_CPLD_PL_SPI_SCLK, + output DBA_CPLD_PL_SPI_LE, + output DBA_CPLD_PL_SPI_SDI, + input DBA_CPLD_PL_SPI_SDO, + output [2:0] DBA_CPLD_PL_SPI_ADDR, + + output DBA_MYK_SPI_SCLK, + output DBA_MYK_SPI_CS_n, + input DBA_MYK_SPI_SDO, + output DBA_MYK_SPI_SDIO, + input DBA_MYK_INTRQ, + + output DBA_MYK_SYNC_IN_n, + input DBA_MYK_SYNC_OUT_n, + + inout DBA_CPLD_JTAG_TCK, + inout DBA_CPLD_JTAG_TMS, + inout DBA_CPLD_JTAG_TDI, + input DBA_CPLD_JTAG_TDO, + + output DBA_MYK_GPIO_0, + output DBA_MYK_GPIO_1, + output DBA_MYK_GPIO_3, + output DBA_MYK_GPIO_4, + output DBA_MYK_GPIO_12, + output DBA_MYK_GPIO_13, + output DBA_MYK_GPIO_14, + output DBA_MYK_GPIO_15, + + input DBA_FPGA_CLK_P, + input DBA_FPGA_CLK_N, + input DBA_FPGA_SYSREF_P, + input DBA_FPGA_SYSREF_N, + + input USRPIO_A_MGTCLK_P, + input USRPIO_A_MGTCLK_N, + + input [3:0] USRPIO_A_RX_P, + input [3:0] USRPIO_A_RX_N, + output [3:0] USRPIO_A_TX_P, + output [3:0] USRPIO_A_TX_N + +`ifndef N300 + //USRP IO B + ,output DBB_CPLD_PS_SPI_SCLK, + output DBB_CPLD_PS_SPI_LE, + output DBB_CPLD_PS_SPI_SDI, + input DBB_CPLD_PS_SPI_SDO, + output [1:0] DBB_CPLD_PS_SPI_ADDR, + + output DBB_ATR_RX_1, + output DBB_ATR_RX_2, + output DBB_ATR_TX_1, + output DBB_ATR_TX_2, + + output [5:0] DBB_CH1_TX_DSA_DATA, + output [5:0] DBB_CH1_RX_DSA_DATA, + output [5:0] DBB_CH2_TX_DSA_DATA, + output [5:0] DBB_CH2_RX_DSA_DATA, + + output DBB_CPLD_PL_SPI_SCLK, + output DBB_CPLD_PL_SPI_LE, + output DBB_CPLD_PL_SPI_SDI, + input DBB_CPLD_PL_SPI_SDO, + output [2:0] DBB_CPLD_PL_SPI_ADDR, + + output DBB_MYK_SPI_SCLK, + output DBB_MYK_SPI_CS_n, + input DBB_MYK_SPI_SDO, + output DBB_MYK_SPI_SDIO, + input DBB_MYK_INTRQ, + + output DBB_MYK_SYNC_IN_n, + input DBB_MYK_SYNC_OUT_n, + + inout DBB_CPLD_JTAG_TCK, + inout DBB_CPLD_JTAG_TMS, + inout DBB_CPLD_JTAG_TDI, + input DBB_CPLD_JTAG_TDO, + + output DBB_MYK_GPIO_0, + output DBB_MYK_GPIO_1, + output DBB_MYK_GPIO_3, + output DBB_MYK_GPIO_4, + output DBB_MYK_GPIO_12, + output DBB_MYK_GPIO_13, + output DBB_MYK_GPIO_14, + output DBB_MYK_GPIO_15, + + input DBB_FPGA_CLK_P, + input DBB_FPGA_CLK_N, + input DBB_FPGA_SYSREF_P, + input DBB_FPGA_SYSREF_N, + + input USRPIO_B_MGTCLK_P, + input USRPIO_B_MGTCLK_N, + + input [3:0] USRPIO_B_RX_P, + input [3:0] USRPIO_B_RX_N, + output [3:0] USRPIO_B_TX_P, + output [3:0] USRPIO_B_TX_N +`endif +); + + localparam N_AXILITE_SLAVES = 4; + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam QSFP_REG_AWIDTH = 17; // log2(0x20000) + localparam REG_DWIDTH = 32; + localparam FP_GPIO_OFFSET = 32; + localparam FP_GPIO_WIDTH = 12; + +`ifdef N310 + localparam NUM_RADIOS = 2; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 2; +`elsif N300 + localparam NUM_RADIOS = 1; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 1; +`endif + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}; + + // Internal connections to PS + // HP0 -- High Performance port 0, FPGA is the master + wire [5:0] S_AXI_HP0_AWID; + wire [31:0] S_AXI_HP0_AWADDR; + wire [2:0] S_AXI_HP0_AWPROT; + wire S_AXI_HP0_AWVALID; + wire S_AXI_HP0_AWREADY; + wire [63:0] S_AXI_HP0_WDATA; + wire [7:0] S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP0_WREADY; + wire [1:0] S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire S_AXI_HP0_BREADY; + wire [5:0] S_AXI_HP0_ARID; + wire [31:0] S_AXI_HP0_ARADDR; + wire [2:0] S_AXI_HP0_ARPROT; + wire S_AXI_HP0_ARVALID; + wire S_AXI_HP0_ARREADY; + wire [63:0] S_AXI_HP0_RDATA; + wire [1:0] S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire S_AXI_HP0_RREADY; + wire S_AXI_HP0_RLAST; + wire [3:0] S_AXI_HP0_ARCACHE; + wire [7:0] S_AXI_HP0_AWLEN; + wire [2:0] S_AXI_HP0_AWSIZE; + wire [1:0] S_AXI_HP0_AWBURST; + wire [3:0] S_AXI_HP0_AWCACHE; + wire S_AXI_HP0_WLAST; + wire [7:0] S_AXI_HP0_ARLEN; + wire [1:0] S_AXI_HP0_ARBURST; + wire [2:0] S_AXI_HP0_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the master + wire [4:0] S_AXI_GP0_AWID; + wire [31:0] S_AXI_GP0_AWADDR; + wire [2:0] S_AXI_GP0_AWPROT; + wire S_AXI_GP0_AWVALID; + wire S_AXI_GP0_AWREADY; + wire [31:0] S_AXI_GP0_WDATA; + wire [3:0] S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP0_WREADY; + wire [1:0] S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire S_AXI_GP0_BREADY; + wire [4:0] S_AXI_GP0_ARID; + wire [31:0] S_AXI_GP0_ARADDR; + wire [2:0] S_AXI_GP0_ARPROT; + wire S_AXI_GP0_ARVALID; + wire S_AXI_GP0_ARREADY; + wire [31:0] S_AXI_GP0_RDATA; + wire [1:0] S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire S_AXI_GP0_RREADY; + wire S_AXI_GP0_RLAST; + wire [3:0] S_AXI_GP0_ARCACHE; + wire [7:0] S_AXI_GP0_AWLEN; + wire [2:0] S_AXI_GP0_AWSIZE; + wire [1:0] S_AXI_GP0_AWBURST; + wire [3:0] S_AXI_GP0_AWCACHE; + wire S_AXI_GP0_WLAST; + wire [7:0] S_AXI_GP0_ARLEN; + wire [1:0] S_AXI_GP0_ARBURST; + wire [2:0] S_AXI_GP0_ARSIZE; + + // HP1 -- High Performance port 1, FPGA is the master + wire [5:0] S_AXI_HP1_AWID; + wire [31:0] S_AXI_HP1_AWADDR; + wire [2:0] S_AXI_HP1_AWPROT; + wire S_AXI_HP1_AWVALID; + wire S_AXI_HP1_AWREADY; + wire [63:0] S_AXI_HP1_WDATA; + wire [7:0] S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP1_WREADY; + wire [1:0] S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire S_AXI_HP1_BREADY; + wire [5:0] S_AXI_HP1_ARID; + wire [31:0] S_AXI_HP1_ARADDR; + wire [2:0] S_AXI_HP1_ARPROT; + wire S_AXI_HP1_ARVALID; + wire S_AXI_HP1_ARREADY; + wire [63:0] S_AXI_HP1_RDATA; + wire [1:0] S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire S_AXI_HP1_RREADY; + wire S_AXI_HP1_RLAST; + wire [3:0] S_AXI_HP1_ARCACHE; + wire [7:0] S_AXI_HP1_AWLEN; + wire [2:0] S_AXI_HP1_AWSIZE; + wire [1:0] S_AXI_HP1_AWBURST; + wire [3:0] S_AXI_HP1_AWCACHE; + wire S_AXI_HP1_WLAST; + wire [7:0] S_AXI_HP1_ARLEN; + wire [1:0] S_AXI_HP1_ARBURST; + wire [2:0] S_AXI_HP1_ARSIZE; + + // GP1 -- General Purpose port 1, FPGA is the master + wire [4:0] S_AXI_GP1_AWID; + wire [31:0] S_AXI_GP1_AWADDR; + wire [2:0] S_AXI_GP1_AWPROT; + wire S_AXI_GP1_AWVALID; + wire S_AXI_GP1_AWREADY; + wire [31:0] S_AXI_GP1_WDATA; + wire [3:0] S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_GP1_WREADY; + wire [1:0] S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire S_AXI_GP1_BREADY; + wire [4:0] S_AXI_GP1_ARID; + wire [31:0] S_AXI_GP1_ARADDR; + wire [2:0] S_AXI_GP1_ARPROT; + wire S_AXI_GP1_ARVALID; + wire S_AXI_GP1_ARREADY; + wire [31:0] S_AXI_GP1_RDATA; + wire [1:0] S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire S_AXI_GP1_RREADY; + wire S_AXI_GP1_RLAST; + wire [3:0] S_AXI_GP1_ARCACHE; + wire [7:0] S_AXI_GP1_AWLEN; + wire [2:0] S_AXI_GP1_AWSIZE; + wire [1:0] S_AXI_GP1_AWBURST; + wire [3:0] S_AXI_GP1_AWCACHE; + wire S_AXI_GP1_WLAST; + wire [7:0] S_AXI_GP1_ARLEN; + wire [1:0] S_AXI_GP1_ARBURST; + wire [2:0] S_AXI_GP1_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the slave + wire M_AXI_GP0_ARVALID; + wire M_AXI_GP0_AWVALID; + wire M_AXI_GP0_BREADY; + wire M_AXI_GP0_RREADY; + wire M_AXI_GP0_WVALID; + wire [11:0] M_AXI_GP0_ARID; + wire [11:0] M_AXI_GP0_AWID; + wire [11:0] M_AXI_GP0_WID; + wire [31:0] M_AXI_GP0_ARADDR; + wire [31:0] M_AXI_GP0_AWADDR; + wire [31:0] M_AXI_GP0_WDATA; + wire [3:0] M_AXI_GP0_WSTRB; + wire M_AXI_GP0_ARREADY; + wire M_AXI_GP0_AWREADY; + wire M_AXI_GP0_BVALID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RVALID; + wire M_AXI_GP0_WREADY; + wire [1:0] M_AXI_GP0_BRESP; + wire [1:0] M_AXI_GP0_RRESP; + wire [31:0] M_AXI_GP0_RDATA; + + wire M_AXI_ETH_DMA0_ARVALID; + wire M_AXI_ETH_DMA0_AWVALID; + wire M_AXI_ETH_DMA0_BREADY; + wire M_AXI_ETH_DMA0_RREADY; + wire M_AXI_ETH_DMA0_WVALID; + wire [11:0] M_AXI_ETH_DMA0_ARID; + wire [11:0] M_AXI_ETH_DMA0_AWID; + wire [11:0] M_AXI_ETH_DMA0_WID; + wire [31:0] M_AXI_ETH_DMA0_ARADDR; + wire [31:0] M_AXI_ETH_DMA0_AWADDR; + wire [31:0] M_AXI_ETH_DMA0_WDATA; + wire [3:0] M_AXI_ETH_DMA0_WSTRB; + wire M_AXI_ETH_DMA0_ARREADY; + wire M_AXI_ETH_DMA0_AWREADY; + wire M_AXI_ETH_DMA0_BVALID; + wire M_AXI_ETH_DMA0_RLAST; + wire M_AXI_ETH_DMA0_RVALID; + wire M_AXI_ETH_DMA0_WREADY; + wire [1:0] M_AXI_ETH_DMA0_BRESP; + wire [1:0] M_AXI_ETH_DMA0_RRESP; + wire [31:0] M_AXI_ETH_DMA0_RDATA; + + wire M_AXI_NET0_ARVALID; + wire M_AXI_NET0_AWVALID; + wire M_AXI_NET0_BREADY; + wire M_AXI_NET0_RREADY; + wire M_AXI_NET0_WVALID; + wire [11:0] M_AXI_NET0_ARID; + wire [11:0] M_AXI_NET0_AWID; + wire [11:0] M_AXI_NET0_WID; + wire [31:0] M_AXI_NET0_ARADDR; + wire [31:0] M_AXI_NET0_AWADDR; + wire [31:0] M_AXI_NET0_WDATA; + wire [3:0] M_AXI_NET0_WSTRB; + wire M_AXI_NET0_ARREADY; + wire M_AXI_NET0_AWREADY; + wire M_AXI_NET0_BVALID; + wire M_AXI_NET0_RLAST; + wire M_AXI_NET0_RVALID; + wire M_AXI_NET0_WREADY; + wire [1:0] M_AXI_NET0_BRESP; + wire [1:0] M_AXI_NET0_RRESP; + wire [31:0] M_AXI_NET0_RDATA; + + wire M_AXI_ETH_DMA1_ARVALID; + wire M_AXI_ETH_DMA1_AWVALID; + wire M_AXI_ETH_DMA1_BREADY; + wire M_AXI_ETH_DMA1_RREADY; + wire M_AXI_ETH_DMA1_WVALID; + wire [11:0] M_AXI_ETH_DMA1_ARID; + wire [11:0] M_AXI_ETH_DMA1_AWID; + wire [11:0] M_AXI_ETH_DMA1_WID; + wire [31:0] M_AXI_ETH_DMA1_ARADDR; + wire [31:0] M_AXI_ETH_DMA1_AWADDR; + wire [31:0] M_AXI_ETH_DMA1_WDATA; + wire [3:0] M_AXI_ETH_DMA1_WSTRB; + wire M_AXI_ETH_DMA1_ARREADY; + wire M_AXI_ETH_DMA1_AWREADY; + wire M_AXI_ETH_DMA1_BVALID; + wire M_AXI_ETH_DMA1_RLAST; + wire M_AXI_ETH_DMA1_RVALID; + wire M_AXI_ETH_DMA1_WREADY; + wire [1:0] M_AXI_ETH_DMA1_BRESP; + wire [1:0] M_AXI_ETH_DMA1_RRESP; + wire [31:0] M_AXI_ETH_DMA1_RDATA; + + wire M_AXI_NET1_ARVALID; + wire M_AXI_NET1_AWVALID; + wire M_AXI_NET1_BREADY; + wire M_AXI_NET1_RREADY; + wire M_AXI_NET1_WVALID; + wire [11:0] M_AXI_NET1_ARID; + wire [11:0] M_AXI_NET1_AWID; + wire [11:0] M_AXI_NET1_WID; + wire [31:0] M_AXI_NET1_ARADDR; + wire [31:0] M_AXI_NET1_AWADDR; + wire [31:0] M_AXI_NET1_WDATA; + wire [3:0] M_AXI_NET1_WSTRB; + wire M_AXI_NET1_ARREADY; + wire M_AXI_NET1_AWREADY; + wire M_AXI_NET1_BVALID; + wire M_AXI_NET1_RLAST; + wire M_AXI_NET1_RVALID; + wire M_AXI_NET1_WREADY; + wire [1:0] M_AXI_NET1_BRESP; + wire [1:0] M_AXI_NET1_RRESP; + wire [31:0] M_AXI_NET1_RDATA; + + wire M_AXI_NET2_ARVALID; + wire M_AXI_NET2_AWVALID; + wire M_AXI_NET2_BREADY; + wire M_AXI_NET2_RREADY; + wire M_AXI_NET2_WVALID; + wire [11:0] M_AXI_NET2_ARID; + wire [11:0] M_AXI_NET2_AWID; + wire [11:0] M_AXI_NET2_WID; + wire [31:0] M_AXI_NET2_ARADDR; + wire [31:0] M_AXI_NET2_AWADDR; + wire [31:0] M_AXI_NET2_WDATA; + wire [3:0] M_AXI_NET2_WSTRB; + wire M_AXI_NET2_ARREADY; + wire M_AXI_NET2_AWREADY; + wire M_AXI_NET2_BVALID; + wire M_AXI_NET2_RLAST; + wire M_AXI_NET2_RVALID; + wire M_AXI_NET2_WREADY; + wire [1:0] M_AXI_NET2_BRESP; + wire [1:0] M_AXI_NET2_RRESP; + wire [31:0] M_AXI_NET2_RDATA; + + wire M_AXI_XBAR_ARVALID; + wire M_AXI_XBAR_AWVALID; + wire M_AXI_XBAR_BREADY; + wire M_AXI_XBAR_RREADY; + wire M_AXI_XBAR_WVALID; + wire [11:0] M_AXI_XBAR_ARID; + wire [11:0] M_AXI_XBAR_AWID; + wire [11:0] M_AXI_XBAR_WID; + wire [31:0] M_AXI_XBAR_ARADDR; + wire [31:0] M_AXI_XBAR_AWADDR; + wire [31:0] M_AXI_XBAR_WDATA; + wire [3:0] M_AXI_XBAR_WSTRB; + wire M_AXI_XBAR_ARREADY; + wire M_AXI_XBAR_AWREADY; + wire M_AXI_XBAR_BVALID; + wire M_AXI_XBAR_RLAST; + wire M_AXI_XBAR_RVALID; + wire M_AXI_XBAR_WREADY; + wire [1:0] M_AXI_XBAR_BRESP; + wire [1:0] M_AXI_XBAR_RRESP; + wire [31:0] M_AXI_XBAR_RDATA; + + wire M_AXI_JESD0_ARVALID; + wire M_AXI_JESD0_AWVALID; + wire M_AXI_JESD0_BREADY; + wire M_AXI_JESD0_RREADY; + wire M_AXI_JESD0_WVALID; + wire [11:0] M_AXI_JESD0_ARID; + wire [11:0] M_AXI_JESD0_AWID; + wire [11:0] M_AXI_JESD0_WID; + wire [31:0] M_AXI_JESD0_ARADDR; + wire [31:0] M_AXI_JESD0_AWADDR; + wire [31:0] M_AXI_JESD0_WDATA; + wire [3:0] M_AXI_JESD0_WSTRB; + wire M_AXI_JESD0_ARREADY; + wire M_AXI_JESD0_AWREADY; + wire M_AXI_JESD0_BVALID; + wire M_AXI_JESD0_RLAST; + wire M_AXI_JESD0_RVALID; + wire M_AXI_JESD0_WREADY; + wire [1:0] M_AXI_JESD0_BRESP; + wire [1:0] M_AXI_JESD0_RRESP; + wire [31:0] M_AXI_JESD0_RDATA; + + wire M_AXI_JESD1_ARVALID; + wire M_AXI_JESD1_AWVALID; + wire M_AXI_JESD1_BREADY; + wire M_AXI_JESD1_RREADY; + wire M_AXI_JESD1_WVALID; + wire [11:0] M_AXI_JESD1_ARID; + wire [11:0] M_AXI_JESD1_AWID; + wire [11:0] M_AXI_JESD1_WID; + wire [31:0] M_AXI_JESD1_ARADDR; + wire [31:0] M_AXI_JESD1_AWADDR; + wire [31:0] M_AXI_JESD1_WDATA; + wire [3:0] M_AXI_JESD1_WSTRB; + wire M_AXI_JESD1_ARREADY; + wire M_AXI_JESD1_AWREADY; + wire M_AXI_JESD1_BVALID; + wire M_AXI_JESD1_RLAST; + wire M_AXI_JESD1_RVALID; + wire M_AXI_JESD1_WREADY; + wire [1:0] M_AXI_JESD1_BRESP; + wire [1:0] M_AXI_JESD1_RRESP; + wire [31:0] M_AXI_JESD1_RDATA; + + // White Rabbit + wire wr_uart_txd; + wire wr_uart_rxd; + wire pps_wr_refclk; + wire wr_ref_clk; + + // AXI bus from PS to WR Core + wire m_axi_wr_clk; + wire [31:0] m_axi_wr_araddr; + wire [0:0] m_axi_wr_arready; + wire [0:0] m_axi_wr_arvalid; + wire [31:0] m_axi_wr_awaddr; + wire [0:0] m_axi_wr_awready; + wire [0:0] m_axi_wr_awvalid; + wire [0:0] m_axi_wr_bready; + wire [1:0] m_axi_wr_bresp; + wire [0:0] m_axi_wr_bvalid; + wire [31:0] m_axi_wr_rdata; + wire [0:0] m_axi_wr_rready; + wire [1:0] m_axi_wr_rresp; + wire [0:0] m_axi_wr_rvalid; + wire [31:0] m_axi_wr_wdata; + wire [0:0] m_axi_wr_wready; + wire [3:0] m_axi_wr_wstrb; + wire [0:0] m_axi_wr_wvalid; + + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_tri; + + wire [15:0] IRQ_F2P; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire clk100; + wire clk40; + wire meas_clk_ref; + wire bus_clk; + wire gige_refclk; + wire gige_refclk_bufg; + wire xgige_refclk; + wire xgige_clk156; + wire xgige_dclk; + + wire global_rst; + wire radio_rst; + wire bus_rst; + wire FCLK_RESET0_N; + wire clk40_rst; + wire clk40_rstn; + + wire [1:0] USB0_PORT_INDCTL; + wire USB0_VBUS_PWRSELECT; + wire USB0_VBUS_PWRFAULT; + + wire ref_clk; + wire wr_refclk_buf; + wire netclk_buf; + wire meas_clk; + wire ddr3_dma_clk; + wire meas_clk_reset; + wire meas_clk_locked; + wire enable_ref_clk_async; + wire pps_radioclk1x_iob; + wire pps_radioclk1x; + wire [3:0] pps_select; + wire pps_out_enb; + wire [1:0] pps_select_sfp; + wire pps_refclk; + wire export_pps_radioclk; + wire radio_clk; + wire radio_clk_2x; + + wire qsfp_sda_i; + wire qsfp_sda_o; + wire qsfp_sda_t; + wire qsfp_scl_i; + wire qsfp_scl_o; + wire qsfp_scl_t; + + ///////////////////////////////////////////////////////////////////// + // + // Resets + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); + + // Synchronous reset for the radio_clk domain, based on the global_rst. + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(global_rst), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain, based on the global_rst. + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(global_rst), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + + + ///////////////////////////////////////////////////////////////////// + // + // Timing + // + ////////////////////////////////////////////////////////////////////// + + // Clocks from the PS + // + // These clocks appear to have BUFGs already instantiated by the ip generator. + // Simply rename them here for clarity. + // FCLK_CLK0 : 100 MHz + // FCLK_CLK1 : 40 MHz + // FCLK_CLK2 : 166.6667 MHz + // FCLK_CLK3 : 200 MHz + assign clk100 = FCLK_CLK0; + assign clk40 = FCLK_CLK1; + assign meas_clk_ref = FCLK_CLK2; + assign bus_clk = FCLK_CLK3; + + //If bus_clk freq ever changes, update this paramter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + + n3xx_clocking n3xx_clocking_i ( + .enable_ref_clk_async(enable_ref_clk_async), + .FPGA_REFCLK_P(FPGA_REFCLK_P), + .FPGA_REFCLK_N(FPGA_REFCLK_N), + .ref_clk(ref_clk), + .WB_20MHz_P(WB_20MHZ_P), + .WB_20MHz_N(WB_20MHZ_N), + .wr_refclk_buf(wr_refclk_buf), + .NETCLK_REF_P(NETCLK_REF_P), + .NETCLK_REF_N(NETCLK_REF_N), + .netclk_buf(netclk_buf), + .NETCLK_P(NETCLK_P), + .NETCLK_N(NETCLK_N), + .gige_refclk_buf(gige_refclk), + .MGT156MHZ_CLK1_P(MGT156MHZ_CLK1_P), + .MGT156MHZ_CLK1_N(MGT156MHZ_CLK1_N), + .xgige_refclk_buf(xgige_refclk), + .misc_clks_ref(meas_clk_ref), + .meas_clk(meas_clk), + .ddr3_dma_clk(ddr3_dma_clk), + .misc_clks_reset(meas_clk_reset), + .misc_clks_locked(meas_clk_locked), + .ext_pps_from_pin(REF_1PPS_IN), + .gps_pps_from_pin(GPS_1PPS), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + // Drive the rear panel connector with another controllable copy of the post-TDC PPS + // that SW can enable/disable. The user is free to hack this to be whatever + // they desire. Flop the PPS signal one more time in order that it can be packed into + // an IOB. This extra flop stage matches the additional flop inside DbCore to allow + // pps_radioclk1x and pps_out_radioclk to be in sync with one another. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) pps_export_dsync ( + .clk(radio_clk), .rst(1'b0), .in(pps_out_enb), .out(export_pps_radioclk) + ); + + // The radio_clk rate is between [122.88M, 250M] for all known N3xx variants, + // resulting in approximately [8ns, 4ns] periods. To pulse-extend the PPS output, + // we create a 25 bit-wide counter, creating ~[.262s, .131s] long output high pulses, + // variable depending on our radio_clk rate. Create two of the same output signal + // in order that the PPS_OUT gets packed into an IOB for tight timing. + reg [24:0] pps_out_count = 'b0; + reg pps_out_radioclk = 1'b0; + reg pps_led_radioclk = 1'b0; + + always @(posedge radio_clk) begin + if (export_pps_radioclk) begin + if (pps_radioclk1x_iob) begin + pps_out_radioclk <= 1'b1; + pps_led_radioclk <= 1'b1; + pps_out_count <= {25{1'b1}}; + end else begin + if (pps_out_count > 0) begin + pps_out_count <= pps_out_count - 1'b1; + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + // Local to output. + assign REF_1PPS_OUT = pps_out_radioclk; + assign PANEL_LED_PPS = pps_led_radioclk; + + ///////////////////////////////////////////////////////////////////// + // + // SFP, QSFP and NPIO MGT Connections + // + ////////////////////////////////////////////////////////////////////// + wire reg_wr_req_npio; + wire [REG_AWIDTH-1:0] reg_wr_addr_npio; + wire [REG_DWIDTH-1:0] reg_wr_data_npio; + wire reg_rd_req_npio; + wire [REG_AWIDTH-1:0] reg_rd_addr_npio; + wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; + wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; + + localparam NPIO_REG_BASE = 14'h0200; + + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) npio_resp_mux_i( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio0, reg_rd_resp_npio1}), + .sla_rd_data({reg_rd_data_npio0, reg_rd_data_npio1}), + .mst_rd_resp(reg_rd_resp_npio), .mst_rd_data(reg_rd_data_npio) + ); + + //-------------------------------------------------------------- + // SFP/MGT Reference Clocks + //-------------------------------------------------------------- + + // We support the HG, XG, XA, AA targets, all of which require + // the 156.25MHz reference clock. Instantiate it here. + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + wire qpllreset; + wire qpllreset_sfp0, qpllreset_sfp1, qpllreset_npio0, qpllreset_npio1; + wire qplllock; + wire qplloutclk; + wire qplloutrefclk; + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), //from 2nd sfp + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b101 /*GTSOUTHREFCLK0*/) + ); + + // The quad's QPLL should reset if any of the channels request it + // This should never really happen because we are not changing the reference clock + // source for the QPLL. + assign qpllreset = qpllreset_sfp0 | qpllreset_sfp1 | qpllreset_npio0 | qpllreset_npio1; + + // Use the 156.25MHz reference clock for Aurora + wire aurora_refclk = xgige_refclk; + wire aurora_clk156 = xgige_clk156; + wire aurora_init_clk = xgige_dclk; + + // White Rabbit and 1GbE both use the same clocking +`ifdef SFP0_1GBE + `define SFP0_WR_1GBE +`endif +`ifdef SFP0_WR + `define SFP0_WR_1GBE +`endif + +`ifdef SFP0_WR_1GBE + // HG and WX targets require the 1GbE clock support + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + assign SFP_0_RS0 = 1'b0; + assign SFP_0_RS1 = 1'b0; +`else + assign SFP_0_RS0 = 1'b1; + assign SFP_0_RS1 = 1'b1; +`endif + + // SFP 1 is always set to run at ~10Gbps rates. + assign SFP_1_RS0 = 1'b1; + assign SFP_1_RS1 = 1'b1; + + // SFP port specific reference clocks + wire sfp0_gt_refclk, sfp1_gt_refclk; + wire sfp0_gb_refclk, sfp1_gb_refclk; + wire sfp0_misc_clk, sfp1_misc_clk; + +`ifdef SFP0_10GBE + assign sfp0_gt_refclk = xgige_refclk; + assign sfp0_gb_refclk = xgige_clk156; + assign sfp0_misc_clk = xgige_dclk; +`endif +`ifdef SFP0_WR_1GBE + assign sfp0_gt_refclk = gige_refclk; + assign sfp0_gb_refclk = gige_refclk_bufg; + assign sfp0_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP0_AURORA + assign sfp0_gt_refclk = aurora_refclk; + assign sfp0_gb_refclk = aurora_clk156; + assign sfp0_misc_clk = aurora_init_clk; +`endif + +`ifdef SFP1_10GBE + assign sfp1_gt_refclk = xgige_refclk; + assign sfp1_gb_refclk = xgige_clk156; + assign sfp1_misc_clk = xgige_dclk; +`endif +`ifdef SFP1_1GBE + assign sfp1_gt_refclk = gige_refclk; + assign sfp1_gb_refclk = gige_refclk_bufg; + assign sfp1_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP1_AURORA + assign sfp1_gt_refclk = aurora_refclk; + assign sfp1_gb_refclk = aurora_clk156; + assign sfp1_misc_clk = aurora_init_clk; +`endif + + // Instantiate Aurora MMCM if either of the SFPs + // or NPIOs are Aurora + wire au_tx_clk; + wire au_mmcm_reset; + wire au_user_clk; + wire au_sync_clk; + wire au_mmcm_locked; + wire sfp0_tx_out_clk, sfp1_tx_out_clk; + wire sfp0_gt_pll_lock, sfp1_gt_pll_lock; + wire npio0_tx_out_clk, npio1_tx_out_clk; + wire npio0_gt_pll_lock, npio1_gt_pll_lock; + + //NOTE: need to declare one of these defines in order to enable Aurora on + //any SFP or NPIO lane. +`ifdef SFP1_AURORA + `define SFP_AU_MMCM + assign au_tx_clk = sfp1_tx_out_clk; + assign au_mmcm_reset = ~sfp1_gt_pll_lock; +`elsif NPIO0 + `define SFP_AU_MMCM + assign au_tx_clk = npio0_tx_out_clk; + assign au_mmcm_reset = ~npio0_gt_pll_lock; +`elsif NPIO1 + `define SFP_AU_MMCM + assign au_tx_clk = npio1_tx_out_clk; + assign au_mmcm_reset = ~npio1_gt_pll_lock; +`endif + + +`ifdef SFP_AU_MMCM + aurora_phy_mmcm au_phy_mmcm_i ( + .aurora_tx_clk_unbuf(au_tx_clk), + .mmcm_reset(au_mmcm_reset), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); +`else + assign au_user_clk = 1'b0; + assign au_sync_clk = 1'b0; + assign au_mmcm_locked = 1'b0; +`endif + + //-------------------------------------------------------------- + // NPIO-QSFP MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef QSFP_LANES + localparam NUM_QSFP_LANES = `QSFP_LANES; + + // QSFP wires to the ARM core and the crossbar + // These will only be connected if QSFP is 2x10 GbE + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_tx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_tx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_tx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_rx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_rx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_rx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] v2e_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tready; + + wire [NUM_QSFP_LANES*64-1:0] e2v_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tready; + + wire [NUM_QSFP_LANES-1:0] qsfp_link_up; + + // QSFP quad's specific reference clocks + wire qsfp_gt_refclk; + wire qsfp_gb_refclk; + wire qsfp_misc_clk; + + wire qsfp_qplloutclk; + wire qsfp_qplloutrefclk; + wire qsfp_qplllock; + wire qsfp_qpllreset; + + wire qsfp_gt_tx_out_clk; + wire qsfp_gt_pll_lock; + + wire qsfp_au_user_clk; + wire qsfp_au_sync_clk; + wire qsfp_au_mmcm_locked; + + +`ifdef QSFP_10GBE + assign qsfp_gt_refclk = xgige_refclk; + assign qsfp_gb_refclk = xgige_clk156; + assign qsfp_misc_clk = xgige_dclk; +`endif +`ifdef QSFP_AURORA + assign qsfp_gt_refclk = aurora_refclk; + assign qsfp_gb_refclk = aurora_clk156; + assign qsfp_misc_clk = aurora_init_clk; +`endif + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) qsfp_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qsfp_qpllreset), + .qplllock(qsfp_qplllock), + .qplloutclk(qsfp_qplloutclk), + .qplloutrefclk(qsfp_qplloutrefclk), + .qpllrefclksel(3'b001 /*GTREFCLK0*/) + ); + + `ifdef QSFP_AURORA + aurora_phy_mmcm aurora_phy_mmcm ( + .aurora_tx_clk_unbuf(qsfp_gt_tx_out_clk), + .mmcm_reset(~qsfp_gt_pll_lock), + .user_clk(qsfp_au_user_clk), + .sync_clk(qsfp_au_sync_clk), + .mmcm_locked(qsfp_au_mmcm_locked) + ); + `else + assign qsfp_au_user_clk = 1'b0; + assign qsfp_au_sync_clk = 1'b0; + assign qsfp_au_mmcm_locked = 1'b0; + `endif + + n3xx_mgt_channel_wrapper #( + `ifdef QSFP_10GBE + .PROTOCOL ("10GbE"), + .MDIO_EN (1'b1), + .MDIO_PHYADDR (5'd4), + `elsif QSFP_AURORA + .PROTOCOL ("Aurora"), + .MDIO_EN (1'b0), + `endif + .LANES (NUM_QSFP_LANES), + .PORTNUM_BASE (4), + .REG_DWIDTH (REG_DWIDTH), + .REG_AWIDTH (QSFP_REG_AWIDTH) + ) qsfp_wrapper_i ( + .areset (global_rst), + .gt_refclk (qsfp_gt_refclk), + .gb_refclk (qsfp_gb_refclk), + .misc_clk (qsfp_misc_clk), + .user_clk (qsfp_au_user_clk), + .sync_clk (qsfp_au_sync_clk), + .gt_tx_out_clk_unbuf(qsfp_gt_tx_out_clk), + + .bus_clk (bus_clk), + .bus_rst (bus_rst), + + // GT Common + .qpllrefclklost (), + .qplllock (qsfp_qplllock), + .qplloutclk (qsfp_qplloutclk), + .qplloutrefclk (qsfp_qplloutrefclk), + .qpllreset (qsfp_qpllreset), + + // Aurora MMCM + .mmcm_locked (qsfp_au_mmcm_locked), + .gt_pll_lock (qsfp_gt_pll_lock), + + .txp (QSFP_TX_P), + .txn (QSFP_TX_N), + .rxp (QSFP_RX_P), + .rxn (QSFP_RX_N), + + .mod_present_n (QSFP_PRESENT_B), + .mod_rxlos (1'b0), + .mod_tx_fault (1'b0), + .mod_tx_disable (), + .mod_int_n (QSFP_INT_B), + .mod_reset_n (QSFP_RESET_B), + .mod_lpmode (QSFP_LPMODE), + .mod_sel_n (QSFP_MODSEL_B), + + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_aresetn (clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (M_AXI_NET2_AWADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_awvalid (M_AXI_NET2_AWVALID), + .s_axi_awready (M_AXI_NET2_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (M_AXI_NET2_WDATA), + .s_axi_wstrb (M_AXI_NET2_WSTRB), + .s_axi_wvalid (M_AXI_NET2_WVALID), + .s_axi_wready (M_AXI_NET2_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (M_AXI_NET2_BRESP), + .s_axi_bvalid (M_AXI_NET2_BVALID), + .s_axi_bready (M_AXI_NET2_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (M_AXI_NET2_ARADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_arvalid (M_AXI_NET2_ARVALID), + .s_axi_arready (M_AXI_NET2_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_NET2_RDATA), + .s_axi_rresp (M_AXI_NET2_RRESP), + .s_axi_rvalid (M_AXI_NET2_RVALID), + .s_axi_rready (M_AXI_NET2_RREADY), + + // Ethernet to Vita + .e2v_tdata (e2v_qsfp_tdata), + .e2v_tlast (e2v_qsfp_tlast), + .e2v_tvalid (e2v_qsfp_tvalid), + .e2v_tready (e2v_qsfp_tready), + + // Vita to Ethernet + .v2e_tdata (v2e_qsfp_tdata), + .v2e_tlast (v2e_qsfp_tlast), + .v2e_tvalid (v2e_qsfp_tvalid), + .v2e_tready (v2e_qsfp_tready), + + // Ethernet to CPU + .e2c_tdata (arm_eth_qsfp_rx_tdata_b), + .e2c_tkeep (arm_eth_qsfp_rx_tkeep_b), + .e2c_tlast (arm_eth_qsfp_rx_tlast_b), + .e2c_tvalid (arm_eth_qsfp_rx_tvalid_b), + .e2c_tready (arm_eth_qsfp_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata (arm_eth_qsfp_tx_tdata_b), + .c2e_tkeep (arm_eth_qsfp_tx_tkeep_b), + .c2e_tlast (arm_eth_qsfp_tx_tlast_b), + .c2e_tvalid (arm_eth_qsfp_tx_tvalid_b), + .c2e_tready (arm_eth_qsfp_tx_tready_b), + + // Sideband White Rabbit Control + .wr_reset_n (1'b1), + .wr_refclk (1'b0), + + .wr_dac_sclk (), + .wr_dac_din (), + .wr_dac_clr_n (), + .wr_dac_cs_n (), + .wr_dac_ldac_n (), + + .wr_eeprom_scl_o(), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), + + .wr_uart_rx (1'b0), + .wr_uart_tx (), + + .mod_pps (), + .mod_refclk (), + + // WR AXI Control + .wr_axi_aclk (), + .wr_axi_aresetn (1'b1), + .wr_axi_awaddr (), + .wr_axi_awvalid (), + .wr_axi_awready (), + .wr_axi_wdata (), + .wr_axi_wstrb (), + .wr_axi_wvalid (), + .wr_axi_wready (), + .wr_axi_bresp (), + .wr_axi_bvalid (), + .wr_axi_bready (), + .wr_axi_araddr (), + .wr_axi_arvalid (), + .wr_axi_arready (), + .wr_axi_rdata (), + .wr_axi_rresp (), + .wr_axi_rvalid (), + .wr_axi_rready (), + .wr_axi_rlast (), + + .port_info (), + .device_id (device_id), + + .link_up (qsfp_link_up), + .activity () + ); + + assign QSFP_I2C_SCL = qsfp_scl_t ? 1'bz : qsfp_scl_o; + assign qsfp_scl_i = QSFP_I2C_SCL; + assign QSFP_I2C_SDA = qsfp_sda_t ? 1'bz : qsfp_sda_o; + assign qsfp_sda_i = QSFP_I2C_SDA; + + assign QSFP_LED = |qsfp_link_up; +`else + + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_qsfp ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_NET2_AWADDR), + .s_axi_awvalid(M_AXI_NET2_AWVALID), + .s_axi_awready(M_AXI_NET2_AWREADY), + + .s_axi_wdata(M_AXI_NET2_WDATA), + .s_axi_wvalid(M_AXI_NET2_WVALID), + .s_axi_wready(M_AXI_NET2_WREADY), + + .s_axi_bresp(M_AXI_NET2_BRESP), + .s_axi_bvalid(M_AXI_NET2_BVALID), + .s_axi_bready(M_AXI_NET2_BREADY), + + .s_axi_araddr(M_AXI_NET2_ARADDR), + .s_axi_arvalid(M_AXI_NET2_ARVALID), + .s_axi_arready(M_AXI_NET2_ARREADY), + + .s_axi_rdata(M_AXI_NET2_RDATA), + .s_axi_rresp(M_AXI_NET2_RRESP), + .s_axi_rvalid(M_AXI_NET2_RVALID), + .s_axi_rready(M_AXI_NET2_RREADY) + + ); + + assign qsfp_scl_i = qsfp_scl_t ? 1'b1 : qsfp_scl_o; + assign qsfp_sda_i = qsfp_sda_t ? 1'b1 : qsfp_sda_o; + +`endif + + //-------------------------------------------------------------- + // NPIO MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef NPIO_LANES + + wire [127:0] npio_loopback_tdata; + wire [1:0] npio_loopback_tvalid; + wire [1:0] npio_loopback_tready; + wire [1:0] npio_loopback_tlast; + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h00), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd2), + .MDIO_EN (0) + ) npio_ln_0_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio0_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio0), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX0_P), + .rxn (NPIO_RX0_N), + .txp (NPIO_TX0_P), + .txn (NPIO_TX0_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio0), + .reg_rd_data (reg_rd_data_npio0), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[63:0]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[0]), + .s_axis_tlast (npio_loopback_tlast[0]), + .s_axis_tready (npio_loopback_tready[0]), + .m_axis_tdata (npio_loopback_tdata[63:0]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[0]), + .m_axis_tlast (npio_loopback_tlast[0]), + .m_axis_tready (npio_loopback_tready[0]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio0_gt_pll_lock) + ); + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h40), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd3), + .MDIO_EN (0) + ) npio_ln_1_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio1_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio1), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX1_P), + .rxn (NPIO_RX1_N), + .txp (NPIO_TX1_P), + .txn (NPIO_TX1_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio1), + .reg_rd_data (reg_rd_data_npio1), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[127:64]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[1]), + .s_axis_tlast (npio_loopback_tlast[1]), + .s_axis_tready (npio_loopback_tready[1]), + .m_axis_tdata (npio_loopback_tdata[127:64]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[1]), + .m_axis_tlast (npio_loopback_tlast[1]), + .m_axis_tready (npio_loopback_tready[1]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio1_gt_pll_lock) + ); + +`else + + assign reg_rd_resp_npio0 = 1'b0; + assign reg_rd_data_npio0 = 'h0; + assign reg_rd_resp_npio1 = 1'b0; + assign reg_rd_data_npio1 = 'h0; + assign npio0_gt_pll_lock = 1'b1; + assign npio1_gt_pll_lock = 1'b1; + assign qpllreset_npio0 = 1'b0; + assign qpllreset_npio1 = 1'b0; + +`endif + + + // ARM ethernet 0 bridge signals + wire [63:0] arm_eth0_tx_tdata; + wire arm_eth0_tx_tvalid; + wire arm_eth0_tx_tlast; + wire arm_eth0_tx_tready; + wire [3:0] arm_eth0_tx_tuser; + wire [7:0] arm_eth0_tx_tkeep; + + wire [63:0] arm_eth0_tx_tdata_b; + wire arm_eth0_tx_tvalid_b; + wire arm_eth0_tx_tlast_b; + wire arm_eth0_tx_tready_b; + wire [3:0] arm_eth0_tx_tuser_b; + wire [7:0] arm_eth0_tx_tkeep_b; + + wire [63:0] arm_eth_sfp0_tx_tdata_b; + wire arm_eth_sfp0_tx_tvalid_b; + wire arm_eth_sfp0_tx_tlast_b; + wire arm_eth_sfp0_tx_tready_b; + wire [3:0] arm_eth_sfp0_tx_tuser_b; + wire [7:0] arm_eth_sfp0_tx_tkeep_b; + + wire [63:0] arm_eth0_rx_tdata; + wire arm_eth0_rx_tvalid; + wire arm_eth0_rx_tlast; + wire arm_eth0_rx_tready; + wire [3:0] arm_eth0_rx_tuser; + wire [7:0] arm_eth0_rx_tkeep; + + wire [63:0] arm_eth0_rx_tdata_b; + wire arm_eth0_rx_tvalid_b; + wire arm_eth0_rx_tlast_b; + wire arm_eth0_rx_tready_b; + wire [3:0] arm_eth0_rx_tuser_b; + wire [7:0] arm_eth0_rx_tkeep_b; + + wire [63:0] arm_eth_sfp0_rx_tdata_b; + wire arm_eth_sfp0_rx_tvalid_b; + wire arm_eth_sfp0_rx_tlast_b; + wire arm_eth_sfp0_rx_tready_b; + wire [3:0] arm_eth_sfp0_rx_tuser_b; + wire [7:0] arm_eth_sfp0_rx_tkeep_b; + + wire arm_eth0_rx_irq; + wire arm_eth0_tx_irq; + + // ARM ethernet 1 bridge signals + wire [63:0] arm_eth1_tx_tdata; + wire arm_eth1_tx_tvalid; + wire arm_eth1_tx_tlast; + wire arm_eth1_tx_tready; + wire [3:0] arm_eth1_tx_tuser; + wire [7:0] arm_eth1_tx_tkeep; + + wire [63:0] arm_eth1_tx_tdata_b; + wire arm_eth1_tx_tvalid_b; + wire arm_eth1_tx_tlast_b; + wire arm_eth1_tx_tready_b; + wire [3:0] arm_eth1_tx_tuser_b; + wire [7:0] arm_eth1_tx_tkeep_b; + + wire [63:0] arm_eth_sfp1_tx_tdata_b; + wire arm_eth_sfp1_tx_tvalid_b; + wire arm_eth_sfp1_tx_tlast_b; + wire arm_eth_sfp1_tx_tready_b; + wire [3:0] arm_eth_sfp1_tx_tuser_b; + wire [7:0] arm_eth_sfp1_tx_tkeep_b; + + wire [63:0] arm_eth1_rx_tdata; + wire arm_eth1_rx_tvalid; + wire arm_eth1_rx_tlast; + wire arm_eth1_rx_tready; + wire [3:0] arm_eth1_rx_tuser; + wire [7:0] arm_eth1_rx_tkeep; + + wire [63:0] arm_eth1_rx_tdata_b; + wire arm_eth1_rx_tvalid_b; + wire arm_eth1_rx_tlast_b; + wire arm_eth1_rx_tready_b; + wire [3:0] arm_eth1_rx_tuser_b; + wire [7:0] arm_eth1_rx_tkeep_b; + + wire [63:0] arm_eth_sfp1_rx_tdata_b; + wire arm_eth_sfp1_rx_tvalid_b; + wire arm_eth_sfp1_rx_tlast_b; + wire arm_eth_sfp1_rx_tready_b; + wire [3:0] arm_eth_sfp1_rx_tuser_b; + wire [7:0] arm_eth_sfp1_rx_tkeep_b; + + wire arm_eth1_tx_irq; + wire arm_eth1_rx_irq; + + // Vita to Ethernet + wire [63:0] v2e0_tdata; + wire v2e0_tlast; + wire v2e0_tvalid; + wire v2e0_tready; + + wire [63:0] v2e1_tdata; + wire v2e1_tlast; + wire v2e1_tvalid; + wire v2e1_tready; + + wire [63:0] v2e_sfp0_tdata; + wire v2e_sfp0_tlast; + wire v2e_sfp0_tvalid; + wire v2e_sfp0_tready; + + wire [63:0] v2e_sfp1_tdata; + wire v2e_sfp1_tlast; + wire v2e_sfp1_tvalid; + wire v2e_sfp1_tready; + + // Ethernet to Vita + wire [63:0] e2v0_tdata; + wire e2v0_tlast; + wire e2v0_tvalid; + wire e2v0_tready; + + wire [63:0] e2v1_tdata; + wire e2v1_tlast; + wire e2v1_tvalid; + wire e2v1_tready; + + wire [63:0] e2v_sfp0_tdata; + wire e2v_sfp0_tlast; + wire e2v_sfp0_tvalid; + wire e2v_sfp0_tready; + + wire [63:0] e2v_sfp1_tdata; + wire e2v_sfp1_tlast; + wire e2v_sfp1_tvalid; + wire e2v_sfp1_tready; + + // Ethernet crossover + wire [63:0] e01_tdata, e10_tdata; + wire [3:0] e01_tuser, e10_tuser; + wire e01_tlast, e01_tvalid, e01_tready; + wire e10_tlast, e10_tvalid, e10_tready; + + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // Misc + wire [31:0] sfp_port0_info; + wire [31:0] sfp_port1_info; + wire sfp0_link_up, sfp1_link_up; + wire [15:0] device_id; + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 0: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP0_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `elsif SFP0_1GBE + .PROTOCOL("1GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_WR + .PROTOCOL("WhiteRabbit"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM_BASE(8'd0) + ) sfp_wrapper_0 ( + .areset(global_rst), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp0), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp0_gt_pll_lock), + + .txp(SFP_0_TX_P), + .txn(SFP_0_TX_N), + .rxp(SFP_0_RX_P), + .rxn(SFP_0_RX_N), + + .mod_present_n(SFP_0_I2C_NPRESENT), + .mod_rxlos(SFP_0_LOS), + .mod_tx_fault(SFP_0_TXFAULT), + .mod_tx_disable(SFP_0_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET0_AWVALID), + .s_axi_awready(M_AXI_NET0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET0_WDATA), + .s_axi_wstrb(M_AXI_NET0_WSTRB), + .s_axi_wvalid(M_AXI_NET0_WVALID), + .s_axi_wready(M_AXI_NET0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET0_BRESP), + .s_axi_bvalid(M_AXI_NET0_BVALID), + .s_axi_bready(M_AXI_NET0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET0_ARVALID), + .s_axi_arready(M_AXI_NET0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET0_RDATA), + .s_axi_rresp(M_AXI_NET0_RRESP), + .s_axi_rvalid(M_AXI_NET0_RVALID), + .s_axi_rready(M_AXI_NET0_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp0_tdata), + .e2v_tlast(e2v_sfp0_tlast), + .e2v_tvalid(e2v_sfp0_tvalid), + .e2v_tready(e2v_sfp0_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp0_tdata), + .v2e_tlast(v2e_sfp0_tlast), + .v2e_tvalid(v2e_sfp0_tvalid), + .v2e_tready(v2e_sfp0_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp0_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp0_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), + .e2c_tready(arm_eth_sfp0_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp0_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp0_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), + .c2e_tready(arm_eth_sfp0_tx_tready_b), + + // White Rabbit Specific +`ifdef SFP0_WR + .wr_reset_n (~ps_gpio_out[48]), // reset for WR only + .wr_refclk (wr_refclk_buf), + .wr_dac_sclk (WB_DAC_SCLK), + .wr_dac_din (WB_DAC_DIN), + .wr_dac_clr_n (WB_DAC_NCLR), + .wr_dac_cs_n (WB_DAC_NSYNC), + .wr_dac_ldac_n(WB_DAC_NLDAC), + .wr_eeprom_scl_o(), // storage for delay characterization + .wr_eeprom_scl_i(1'b0), // temp + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), // temp + .wr_uart_rx(wr_uart_rxd), // to/from PS + .wr_uart_tx(wr_uart_txd), + .mod_pps(pps_wr_refclk), // out, reference clock and pps + .mod_refclk(wr_ref_clk), + // WR Slave Port to PS + .wr_axi_aclk(m_axi_wr_clk), // out to PS + .wr_axi_aresetn(1'b1), // in + .wr_axi_awaddr(m_axi_wr_awaddr), + .wr_axi_awvalid(m_axi_wr_awvalid), + .wr_axi_awready(m_axi_wr_awready), + .wr_axi_wdata(m_axi_wr_wdata), + .wr_axi_wstrb(m_axi_wr_wstrb), + .wr_axi_wvalid(m_axi_wr_wvalid), + .wr_axi_wready(m_axi_wr_wready), + .wr_axi_bresp(m_axi_wr_bresp), + .wr_axi_bvalid(m_axi_wr_bvalid), + .wr_axi_bready(m_axi_wr_bready), + .wr_axi_araddr(m_axi_wr_araddr), + .wr_axi_arvalid(m_axi_wr_arvalid), + .wr_axi_arready(m_axi_wr_arready), + .wr_axi_rdata(m_axi_wr_rdata), + .wr_axi_rresp(m_axi_wr_rresp), + .wr_axi_rvalid(m_axi_wr_rvalid), + .wr_axi_rready(m_axi_wr_rready), + .wr_axi_rlast(), +`else + .wr_reset_n(1'b1), + .wr_refclk(1'b0), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_i(1'b0), + .wr_uart_rx(1'b0), +`endif + + // Misc + .port_info(sfp_port0_info), + .device_id(device_id), + + // LED + .link_up(sfp0_link_up), + .activity(SFP_0_LED_A) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; + assign SFP_0_LED_B = sfp0_link_up; + +`ifndef SFP0_WR + assign WB_DAC_SCLK = 1'b0; + assign WB_DAC_DIN = 1'b0; + assign WB_DAC_NCLR = 1'b1; + assign WB_DAC_NSYNC = 1'b1; + assign WB_DAC_NLDAC = 1'b1; + assign pps_wr_refclk = 1'b0; + assign wr_ref_clk = 1'b0; +`endif + + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 1: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP1_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP1_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM_BASE(8'd1) + ) sfp_wrapper_1 ( + .areset(global_rst), + + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp1_gt_pll_lock), + + .txp(SFP_1_TX_P), + .txn(SFP_1_TX_N), + .rxp(SFP_1_RX_P), + .rxn(SFP_1_RX_N), + + .mod_rxlos(SFP_1_LOS), + .mod_tx_fault(SFP_1_TXFAULT), + .mod_tx_disable(SFP_1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET1_AWVALID), + .s_axi_awready(M_AXI_NET1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET1_WDATA), + .s_axi_wstrb(M_AXI_NET1_WSTRB), + .s_axi_wvalid(M_AXI_NET1_WVALID), + .s_axi_wready(M_AXI_NET1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET1_BRESP), + .s_axi_bvalid(M_AXI_NET1_BVALID), + .s_axi_bready(M_AXI_NET1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET1_ARVALID), + .s_axi_arready(M_AXI_NET1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET1_RDATA), + .s_axi_rresp(M_AXI_NET1_RRESP), + .s_axi_rvalid(M_AXI_NET1_RVALID), + .s_axi_rready(M_AXI_NET1_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp1_tdata), + .e2v_tlast(e2v_sfp1_tlast), + .e2v_tvalid(e2v_sfp1_tvalid), + .e2v_tready(e2v_sfp1_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp1_tdata), + .v2e_tlast(v2e_sfp1_tlast), + .v2e_tvalid(v2e_sfp1_tvalid), + .v2e_tready(v2e_sfp1_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp1_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp1_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), + .e2c_tready(arm_eth_sfp1_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp1_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp1_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), + .c2e_tready(arm_eth_sfp1_tx_tready_b), + + // Misc + .port_info(sfp_port1_info), + .device_id(device_id), + + // LED + .link_up(sfp1_link_up), + .activity(SFP_1_LED_A) + ); + + assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; + assign SFP_1_LED_B = sfp1_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 0 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth0_rx_irq; + assign IRQ_F2P[1] = arm_eth0_tx_irq; + + assign {S_AXI_HP0_AWID, S_AXI_HP0_ARID} = 12'd0; + assign {S_AXI_GP0_AWID, S_AXI_GP0_ARID} = 10'd0; + +`ifdef QSFP_10GBE + // QSFP+ lanes connect to DMA engines and crossbar + // Connect first QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[0*64 +: 64] = arm_eth0_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[0] = arm_eth0_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[0] = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_qsfp_tx_tready_b[0]; + assign arm_eth_qsfp_tx_tuser_b[0*4 +: 4] = arm_eth0_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[0*8 +: 8] = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[0*64 +: 64]; + assign arm_eth0_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[0]; + assign arm_eth0_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[0]; + assign arm_eth_qsfp_rx_tready_b[0] = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[0*4 +: 4]; + assign arm_eth0_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[0*8 +: 8]; + + // Connect first QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[0*64 +: 64] = v2e0_tdata; + assign v2e_qsfp_tlast[0] = v2e0_tlast; + assign v2e_qsfp_tvalid[0] = v2e0_tvalid; + assign v2e0_tready = v2e_qsfp_tready[0]; + + assign e2v0_tdata = e2v_qsfp_tdata[0*64 +: 64]; + assign e2v0_tlast = e2v_qsfp_tlast[0]; + assign e2v0_tvalid = e2v_qsfp_tvalid[0]; + assign e2v_qsfp_tready[0] = e2v0_tready; + + // Connect second QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[1*64 +: 64] = arm_eth1_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[1] = arm_eth1_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[1] = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_qsfp_tx_tready_b[1]; + assign arm_eth_qsfp_tx_tuser_b[1*4 +: 4] = arm_eth1_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[1*8 +: 8] = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[1*64 +: 64]; + assign arm_eth1_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[1]; + assign arm_eth1_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[1]; + assign arm_eth_qsfp_rx_tready_b[1] = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[1*4 +: 4]; + assign arm_eth1_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[1*8 +: 8]; + + // Connect second QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[1*64 +: 64] = v2e1_tdata; + assign v2e_qsfp_tlast[1] = v2e1_tlast; + assign v2e_qsfp_tvalid[1] = v2e1_tvalid; + assign v2e1_tready = v2e_qsfp_tready[1]; + + assign e2v1_tdata = e2v_qsfp_tdata[1*64 +: 64]; + assign e2v1_tlast = e2v_qsfp_tlast[1]; + assign e2v1_tvalid = e2v_qsfp_tvalid[1]; + assign e2v_qsfp_tready[1] = e2v1_tready; +`else + // SFP+ ports connects to DMA engines and crossbar + // Connect first SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp0_tx_tdata_b = arm_eth0_tx_tdata_b; + assign arm_eth_sfp0_tx_tvalid_b = arm_eth0_tx_tvalid_b; + assign arm_eth_sfp0_tx_tlast_b = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_sfp0_tx_tready_b; + assign arm_eth_sfp0_tx_tuser_b = arm_eth0_tx_tuser_b; + assign arm_eth_sfp0_tx_tkeep_b = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_sfp0_rx_tdata_b; + assign arm_eth0_rx_tvalid_b = arm_eth_sfp0_rx_tvalid_b; + assign arm_eth0_rx_tlast_b = arm_eth_sfp0_rx_tlast_b; + assign arm_eth_sfp0_rx_tready_b = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_sfp0_rx_tuser_b; + assign arm_eth0_rx_tkeep_b = arm_eth_sfp0_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp0_tdata = v2e0_tdata; + assign v2e_sfp0_tlast = v2e0_tlast; + assign v2e_sfp0_tvalid = v2e0_tvalid; + assign v2e0_tready = v2e_sfp0_tready; + + assign e2v0_tdata = e2v_sfp0_tdata; + assign e2v0_tlast = e2v_sfp0_tlast; + assign e2v0_tvalid = e2v_sfp0_tvalid; + assign e2v_sfp0_tready = e2v0_tready; + + // Connect second SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp1_tx_tdata_b = arm_eth1_tx_tdata_b; + assign arm_eth_sfp1_tx_tvalid_b = arm_eth1_tx_tvalid_b; + assign arm_eth_sfp1_tx_tlast_b = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_sfp1_tx_tready_b; + assign arm_eth_sfp1_tx_tuser_b = arm_eth1_tx_tuser_b; + assign arm_eth_sfp1_tx_tkeep_b = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_sfp1_rx_tdata_b; + assign arm_eth1_rx_tvalid_b = arm_eth_sfp1_rx_tvalid_b; + assign arm_eth1_rx_tlast_b = arm_eth_sfp1_rx_tlast_b; + assign arm_eth_sfp1_rx_tready_b = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_sfp1_rx_tuser_b; + assign arm_eth1_rx_tkeep_b = arm_eth_sfp1_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp1_tdata = v2e1_tdata; + assign v2e_sfp1_tlast = v2e1_tlast; + assign v2e_sfp1_tvalid = v2e1_tvalid; + assign v2e1_tready = v2e_sfp1_tready; + + assign e2v1_tdata = e2v_sfp1_tdata; + assign e2v1_tlast = e2v_sfp1_tlast; + assign e2v1_tvalid = e2v_sfp1_tvalid; + assign e2v_sfp1_tready = e2v1_tready; + + // Don't actually instantiate DMA engines if protocols can't use them + `ifdef SFP0_AURORA + `define NO_ETH_DMA_0 + `elsif SFP0_WR + `define NO_ETH_DMA_0 + `endif + + `ifdef SFP1_AURORA + `define NO_ETH_DMA_1 + `endif +`endif + +`ifdef NO_ETH_DMA_0 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_sfp0_eth_dma ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_rready(M_AXI_ETH_DMA0_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP0_AWADDR = 32'h0; + assign S_AXI_GP0_AWLEN = 8'h0; + assign S_AXI_GP0_AWSIZE = 4'h0; + assign S_AXI_GP0_AWBURST = 3'h0; + assign S_AXI_GP0_AWPROT = 3'h0; + assign S_AXI_GP0_AWCACHE = 4'h0; + assign S_AXI_GP0_AWVALID = 1'b0; + //S_AXI_GP0_AWREADY output from PS + assign S_AXI_GP0_WDATA = 32'h0; + assign S_AXI_GP0_WSTRB = 4'h0; + assign S_AXI_GP0_WLAST = 1'b0; + assign S_AXI_GP0_WVALID = 1'b0; + //S_AXI_GP0_WREADY output from PS + //S_AXI_GP0_BRESP + //S_AXI_GP0_BVALID + assign S_AXI_GP0_BREADY = 1'b1; + assign S_AXI_GP0_ARADDR = 32'h0; + assign S_AXI_GP0_ARLEN = 8'h0; + assign S_AXI_GP0_ARSIZE = 3'h0; + assign S_AXI_GP0_ARBURST = 2'h0; + assign S_AXI_GP0_ARPROT = 3'h0; + assign S_AXI_GP0_ARCACHE = 4'h0; + assign S_AXI_GP0_ARVALID = 1'b0; + //S_AXI_GP0_ARREADY + //S_AXI_GP0_RDATA + //S_AXI_GP0_RRESP + //S_AXI_GP0_RLAST + //S_AXI_GP0_RVALID + assign S_AXI_GP0_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP0_ARADDR = 32'h0; + assign S_AXI_HP0_ARLEN = 8'h0; + assign S_AXI_HP0_ARSIZE = 3'h0; + assign S_AXI_HP0_ARBURST = 2'h0; + assign S_AXI_HP0_ARPROT = 3'h0; + assign S_AXI_HP0_ARCACHE = 4'h0; + assign S_AXI_HP0_ARVALID = 1'b0; + //S_AXI_HP0_ARREADY + //S_AXI_HP0_RDATA + //S_AXI_HP0_RRESP + //S_AXI_HP0_RLAST + //S_AXI_HP0_RVALID + assign S_AXI_HP0_RREADY = 1'b1; + assign S_AXI_HP0_AWADDR = 32'h0; + assign S_AXI_HP0_AWLEN = 8'h0; + assign S_AXI_HP0_AWSIZE = 3'h0; + assign S_AXI_HP0_AWBURST = 2'h0; + assign S_AXI_HP0_AWPROT = 3'h0; + assign S_AXI_HP0_AWCACHE = 4'h0; + assign S_AXI_HP0_AWVALID = 1'b0; + //S_AXI_HP0_AWREADY + assign S_AXI_HP0_WDATA = 64'h0; + assign S_AXI_HP0_WSTRB = 8'h0; + assign S_AXI_HP0_WLAST = 1'b0; + assign S_AXI_HP0_WVALID = 1'b0; + //S_AXI_HP0_WREADY + //S_AXI_HP0_BRESP + //S_AXI_HP0_BVALID + assign S_AXI_HP0_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma0 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA0_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP0_AWADDR), + .m_axi_sg_awlen(S_AXI_GP0_AWLEN), + .m_axi_sg_awsize(S_AXI_GP0_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP0_AWBURST), + .m_axi_sg_awprot(S_AXI_GP0_AWPROT), + .m_axi_sg_awcache(S_AXI_GP0_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP0_AWVALID), + .m_axi_sg_awready(S_AXI_GP0_AWREADY), + .m_axi_sg_wdata(S_AXI_GP0_WDATA), + .m_axi_sg_wstrb(S_AXI_GP0_WSTRB), + .m_axi_sg_wlast(S_AXI_GP0_WLAST), + .m_axi_sg_wvalid(S_AXI_GP0_WVALID), + .m_axi_sg_wready(S_AXI_GP0_WREADY), + .m_axi_sg_bresp(S_AXI_GP0_BRESP), + .m_axi_sg_bvalid(S_AXI_GP0_BVALID), + .m_axi_sg_bready(S_AXI_GP0_BREADY), + .m_axi_sg_araddr(S_AXI_GP0_ARADDR), + .m_axi_sg_arlen(S_AXI_GP0_ARLEN), + .m_axi_sg_arsize(S_AXI_GP0_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP0_ARBURST), + .m_axi_sg_arprot(S_AXI_GP0_ARPROT), + .m_axi_sg_arcache(S_AXI_GP0_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP0_ARVALID), + .m_axi_sg_arready(S_AXI_GP0_ARREADY), + .m_axi_sg_rdata(S_AXI_GP0_RDATA), + .m_axi_sg_rresp(S_AXI_GP0_RRESP), + .m_axi_sg_rlast(S_AXI_GP0_RLAST), + .m_axi_sg_rvalid(S_AXI_GP0_RVALID), + .m_axi_sg_rready(S_AXI_GP0_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP0_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP0_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP0_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP0_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP0_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP0_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP0_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP0_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP0_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP0_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP0_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP0_RVALID), + .m_axi_mm2s_rready(S_AXI_HP0_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth0_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth0_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth0_tx_tvalid), + .m_axis_mm2s_tready(arm_eth0_tx_tready), + .m_axis_mm2s_tlast(arm_eth0_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP0_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP0_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP0_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP0_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP0_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP0_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP0_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP0_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP0_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP0_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP0_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP0_WVALID), + .m_axi_s2mm_wready(S_AXI_HP0_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP0_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP0_BVALID), + .m_axi_s2mm_bready(S_AXI_HP0_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth0_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth0_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth0_rx_tvalid), + .s_axis_s2mm_tready(arm_eth0_rx_tready), + .s_axis_s2mm_tlast(arm_eth0_rx_tlast), + + .mm2s_introut(arm_eth0_tx_irq), + .s2mm_introut(arm_eth0_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_0_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth0_tx_tlast, arm_eth0_tx_tkeep, arm_eth0_tx_tdata}), + .i_tvalid(arm_eth0_tx_tvalid), + .i_tready(arm_eth0_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth0_tx_tlast_b, arm_eth0_tx_tkeep_b, arm_eth0_tx_tdata_b}), + .o_tvalid(arm_eth0_tx_tvalid_b), + .o_tready(arm_eth0_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_0_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth0_rx_tlast_b, arm_eth0_rx_tkeep_b, arm_eth0_rx_tdata_b}), + .i_tvalid(arm_eth0_rx_tvalid_b), + .i_tready(arm_eth0_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth0_rx_tlast, arm_eth0_rx_tkeep, arm_eth0_rx_tdata}), + .o_tvalid(arm_eth0_rx_tvalid), + .o_tready(arm_eth0_rx_tready) + ); + +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 1 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[2] = arm_eth1_rx_irq; + assign IRQ_F2P[3] = arm_eth1_tx_irq; + + assign {S_AXI_HP1_AWID, S_AXI_HP1_ARID} = 12'd0; + assign {S_AXI_GP1_AWID, S_AXI_GP1_ARID} = 10'd0; + +`ifdef NO_ETH_DMA_1 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #(.DEC_ERR(1'b0)) inst_axi_dummy_sfp1_eth_dma + ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_rready(M_AXI_ETH_DMA1_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP1_AWADDR = 32'h0; + assign S_AXI_GP1_AWLEN = 8'h0; + assign S_AXI_GP1_AWSIZE = 4'h0; + assign S_AXI_GP1_AWBURST = 3'h0; + assign S_AXI_GP1_AWPROT = 3'h0; + assign S_AXI_GP1_AWCACHE = 4'h0; + assign S_AXI_GP1_AWVALID = 1'b0; + //S_AXI_GP1_AWREADY output from PS + assign S_AXI_GP1_WDATA = 32'h0; + assign S_AXI_GP1_WSTRB = 4'h0; + assign S_AXI_GP1_WLAST = 1'b0; + assign S_AXI_GP1_WVALID = 1'b0; + //S_AXI_GP1_WREADY output from PS + //S_AXI_GP1_BRESP + //S_AXI_GP1_BVALID + assign S_AXI_GP1_BREADY = 1'b1; + assign S_AXI_GP1_ARADDR = 32'h0; + assign S_AXI_GP1_ARLEN = 8'h0; + assign S_AXI_GP1_ARSIZE = 3'h0; + assign S_AXI_GP1_ARBURST = 2'h0; + assign S_AXI_GP1_ARPROT = 3'h0; + assign S_AXI_GP1_ARCACHE = 4'h0; + assign S_AXI_GP1_ARVALID = 1'b0; + //S_AXI_GP1_ARREADY + //S_AXI_GP1_RDATA + //S_AXI_GP1_RRESP + //S_AXI_GP1_RLAST + //S_AXI_GP1_RVALID + assign S_AXI_GP1_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP1_ARADDR = 32'h0; + assign S_AXI_HP1_ARLEN = 8'h0; + assign S_AXI_HP1_ARSIZE = 3'h0; + assign S_AXI_HP1_ARBURST = 2'h0; + assign S_AXI_HP1_ARPROT = 3'h0; + assign S_AXI_HP1_ARCACHE = 4'h0; + assign S_AXI_HP1_ARVALID = 1'b0; + //S_AXI_HP1_ARREADY + //S_AXI_HP1_RDATA + //S_AXI_HP1_RRESP + //S_AXI_HP1_RLAST + //S_AXI_HP1_RVALID + assign S_AXI_HP1_RREADY = 1'b1; + assign S_AXI_HP1_AWADDR = 32'h0; + assign S_AXI_HP1_AWLEN = 8'h0; + assign S_AXI_HP1_AWSIZE = 3'h0; + assign S_AXI_HP1_AWBURST = 2'h0; + assign S_AXI_HP1_AWPROT = 3'h0; + assign S_AXI_HP1_AWCACHE = 4'h0; + assign S_AXI_HP1_AWVALID = 1'b0; + //S_AXI_HP1_AWREADY + assign S_AXI_HP1_WDATA = 64'h0; + assign S_AXI_HP1_WSTRB = 8'h0; + assign S_AXI_HP1_WLAST = 1'b0; + assign S_AXI_HP1_WVALID = 1'b0; + //S_AXI_HP1_WREADY + //S_AXI_HP1_BRESP + //S_AXI_HP1_BVALID + assign S_AXI_HP1_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma1 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA1_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP1_AWADDR), + .m_axi_sg_awlen(S_AXI_GP1_AWLEN), + .m_axi_sg_awsize(S_AXI_GP1_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP1_AWBURST), + .m_axi_sg_awprot(S_AXI_GP1_AWPROT), + .m_axi_sg_awcache(S_AXI_GP1_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP1_AWVALID), + .m_axi_sg_awready(S_AXI_GP1_AWREADY), + .m_axi_sg_wdata(S_AXI_GP1_WDATA), + .m_axi_sg_wstrb(S_AXI_GP1_WSTRB), + .m_axi_sg_wlast(S_AXI_GP1_WLAST), + .m_axi_sg_wvalid(S_AXI_GP1_WVALID), + .m_axi_sg_wready(S_AXI_GP1_WREADY), + .m_axi_sg_bresp(S_AXI_GP1_BRESP), + .m_axi_sg_bvalid(S_AXI_GP1_BVALID), + .m_axi_sg_bready(S_AXI_GP1_BREADY), + .m_axi_sg_araddr(S_AXI_GP1_ARADDR), + .m_axi_sg_arlen(S_AXI_GP1_ARLEN), + .m_axi_sg_arsize(S_AXI_GP1_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP1_ARBURST), + .m_axi_sg_arprot(S_AXI_GP1_ARPROT), + .m_axi_sg_arcache(S_AXI_GP1_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP1_ARVALID), + .m_axi_sg_arready(S_AXI_GP1_ARREADY), + .m_axi_sg_rdata(S_AXI_GP1_RDATA), + .m_axi_sg_rresp(S_AXI_GP1_RRESP), + .m_axi_sg_rlast(S_AXI_GP1_RLAST), + .m_axi_sg_rvalid(S_AXI_GP1_RVALID), + .m_axi_sg_rready(S_AXI_GP1_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP1_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP1_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP1_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP1_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP1_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP1_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP1_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP1_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP1_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP1_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP1_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP1_RVALID), + .m_axi_mm2s_rready(S_AXI_HP1_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth1_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth1_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth1_tx_tvalid), + .m_axis_mm2s_tready(arm_eth1_tx_tready), + .m_axis_mm2s_tlast(arm_eth1_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP1_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP1_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP1_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP1_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP1_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP1_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP1_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP1_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP1_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP1_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP1_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP1_WVALID), + .m_axi_s2mm_wready(S_AXI_HP1_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP1_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP1_BVALID), + .m_axi_s2mm_bready(S_AXI_HP1_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth1_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth1_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth1_rx_tvalid), + .s_axis_s2mm_tready(arm_eth1_rx_tready), + .s_axis_s2mm_tlast(arm_eth1_rx_tlast), + + .mm2s_introut(arm_eth1_tx_irq), + .s2mm_introut(arm_eth1_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_1_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth1_tx_tlast, arm_eth1_tx_tkeep, arm_eth1_tx_tdata}), + .i_tvalid(arm_eth1_tx_tvalid), + .i_tready(arm_eth1_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth1_tx_tlast_b, arm_eth1_tx_tkeep_b, arm_eth1_tx_tdata_b}), + .o_tvalid(arm_eth1_tx_tvalid_b), + .o_tready(arm_eth1_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_1_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth1_rx_tlast_b, arm_eth1_rx_tkeep_b, arm_eth1_rx_tdata_b}), + .i_tvalid(arm_eth1_rx_tvalid_b), + .i_tready(arm_eth1_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth1_rx_tlast, arm_eth1_rx_tkeep, arm_eth1_rx_tdata}), + .o_tvalid(arm_eth1_rx_tvalid), + .o_tready(arm_eth1_rx_tready) + ); +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Processing System + // + ////////////////////////////////////////////////////////////////////// + + wire spi0_sclk; + wire spi0_mosi; + wire spi0_miso; + wire spi0_ss0; + wire spi0_ss1; + wire spi0_ss2; + wire spi1_sclk; + wire spi1_mosi; + wire spi1_miso; + wire spi1_ss0; + wire spi1_ss1; + wire spi1_ss2; + + assign ps_gpio_in[10] = DBA_MYK_INTRQ; +`ifndef N300 + assign ps_gpio_in[11] = DBB_MYK_INTRQ; +`else + assign ps_gpio_in[11] = 1'b0; +`endif + + // Processing System + n310_ps_bd inst_n310_ps ( + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(spi0_sclk), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(spi0_mosi), + .SPI0_MOSI_T(), + .SPI0_MISO_I(spi0_miso), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(spi0_ss0), + .SPI0_SS1_O(spi0_ss1), + .SPI0_SS2_O(spi0_ss2), + .SPI0_SS_T(), + + `ifndef N300 + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(spi1_sclk), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(spi1_mosi), + .SPI1_MOSI_T(), + .SPI1_MISO_I(spi1_miso), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(spi1_ss0), + .SPI1_SS1_O(spi1_ss1), + .SPI1_SS2_O(spi1_ss2), + .SPI1_SS_T(), + `else + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(), + .SPI1_MOSI_T(), + .SPI1_MISO_I(1'b0), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_T(), + `endif + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + + .M_AXI_ETH_DMA0_araddr(M_AXI_ETH_DMA0_ARADDR), + .M_AXI_ETH_DMA0_arprot(), + .M_AXI_ETH_DMA0_arready(M_AXI_ETH_DMA0_ARREADY), + .M_AXI_ETH_DMA0_arvalid(M_AXI_ETH_DMA0_ARVALID), + + .M_AXI_ETH_DMA0_awaddr(M_AXI_ETH_DMA0_AWADDR), + .M_AXI_ETH_DMA0_awprot(), + .M_AXI_ETH_DMA0_awready(M_AXI_ETH_DMA0_AWREADY), + .M_AXI_ETH_DMA0_awvalid(M_AXI_ETH_DMA0_AWVALID), + + .M_AXI_ETH_DMA0_wdata(M_AXI_ETH_DMA0_WDATA), + .M_AXI_ETH_DMA0_wready(M_AXI_ETH_DMA0_WREADY), + .M_AXI_ETH_DMA0_wstrb(M_AXI_ETH_DMA0_WSTRB), + .M_AXI_ETH_DMA0_wvalid(M_AXI_ETH_DMA0_WVALID), + + .M_AXI_ETH_DMA0_rdata(M_AXI_ETH_DMA0_RDATA), + .M_AXI_ETH_DMA0_rready(M_AXI_ETH_DMA0_RREADY), + .M_AXI_ETH_DMA0_rresp(M_AXI_ETH_DMA0_RRESP), + .M_AXI_ETH_DMA0_rvalid(M_AXI_ETH_DMA0_RVALID), + + .M_AXI_ETH_DMA0_bready(M_AXI_ETH_DMA0_BREADY), + .M_AXI_ETH_DMA0_bresp(M_AXI_ETH_DMA0_BRESP), + .M_AXI_ETH_DMA0_bvalid(M_AXI_ETH_DMA0_BVALID), + + .M_AXI_ETH_DMA1_araddr(M_AXI_ETH_DMA1_ARADDR), + .M_AXI_ETH_DMA1_arprot(), + .M_AXI_ETH_DMA1_arready(M_AXI_ETH_DMA1_ARREADY), + .M_AXI_ETH_DMA1_arvalid(M_AXI_ETH_DMA1_ARVALID), + + .M_AXI_ETH_DMA1_awaddr(M_AXI_ETH_DMA1_AWADDR), + .M_AXI_ETH_DMA1_awprot(), + .M_AXI_ETH_DMA1_awready(M_AXI_ETH_DMA1_AWREADY), + .M_AXI_ETH_DMA1_awvalid(M_AXI_ETH_DMA1_AWVALID), + + .M_AXI_ETH_DMA1_bready(M_AXI_ETH_DMA1_BREADY), + .M_AXI_ETH_DMA1_bresp(M_AXI_ETH_DMA1_BRESP), + .M_AXI_ETH_DMA1_bvalid(M_AXI_ETH_DMA1_BVALID), + + .M_AXI_ETH_DMA1_rdata(M_AXI_ETH_DMA1_RDATA), + .M_AXI_ETH_DMA1_rready(M_AXI_ETH_DMA1_RREADY), + .M_AXI_ETH_DMA1_rresp(M_AXI_ETH_DMA1_RRESP), + .M_AXI_ETH_DMA1_rvalid(M_AXI_ETH_DMA1_RVALID), + + .M_AXI_ETH_DMA1_wdata(M_AXI_ETH_DMA1_WDATA), + .M_AXI_ETH_DMA1_wready(M_AXI_ETH_DMA1_WREADY), + .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB), + .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID), + + .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR), + .M_AXI_JESD0_arprot(), + .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY), + .M_AXI_JESD0_arvalid(M_AXI_JESD0_ARVALID), + + .M_AXI_JESD0_awaddr(M_AXI_JESD0_AWADDR), + .M_AXI_JESD0_awprot(), + .M_AXI_JESD0_awready(M_AXI_JESD0_AWREADY), + .M_AXI_JESD0_awvalid(M_AXI_JESD0_AWVALID), + + .M_AXI_JESD0_bready(M_AXI_JESD0_BREADY), + .M_AXI_JESD0_bresp(M_AXI_JESD0_BRESP), + .M_AXI_JESD0_bvalid(M_AXI_JESD0_BVALID), + + .M_AXI_JESD0_rdata(M_AXI_JESD0_RDATA), + .M_AXI_JESD0_rready(M_AXI_JESD0_RREADY), + .M_AXI_JESD0_rresp(M_AXI_JESD0_RRESP), + .M_AXI_JESD0_rvalid(M_AXI_JESD0_RVALID), + + .M_AXI_JESD0_wdata(M_AXI_JESD0_WDATA), + .M_AXI_JESD0_wready(M_AXI_JESD0_WREADY), + .M_AXI_JESD0_wstrb(M_AXI_JESD0_WSTRB), + .M_AXI_JESD0_wvalid(M_AXI_JESD0_WVALID), + + .M_AXI_JESD1_araddr(M_AXI_JESD1_ARADDR), + .M_AXI_JESD1_arprot(), + .M_AXI_JESD1_arready(M_AXI_JESD1_ARREADY), + .M_AXI_JESD1_arvalid(M_AXI_JESD1_ARVALID), + + .M_AXI_JESD1_awaddr(M_AXI_JESD1_AWADDR), + .M_AXI_JESD1_awprot(), + .M_AXI_JESD1_awready(M_AXI_JESD1_AWREADY), + .M_AXI_JESD1_awvalid(M_AXI_JESD1_AWVALID), + + .M_AXI_JESD1_bready(M_AXI_JESD1_BREADY), + .M_AXI_JESD1_bresp(M_AXI_JESD1_BRESP), + .M_AXI_JESD1_bvalid(M_AXI_JESD1_BVALID), + + .M_AXI_JESD1_rdata(M_AXI_JESD1_RDATA), + .M_AXI_JESD1_rready(M_AXI_JESD1_RREADY), + .M_AXI_JESD1_rresp(M_AXI_JESD1_RRESP), + .M_AXI_JESD1_rvalid(M_AXI_JESD1_RVALID), + + .M_AXI_JESD1_wdata(M_AXI_JESD1_WDATA), + .M_AXI_JESD1_wready(M_AXI_JESD1_WREADY), + .M_AXI_JESD1_wstrb(M_AXI_JESD1_WSTRB), + .M_AXI_JESD1_wvalid(M_AXI_JESD1_WVALID), + + .M_AXI_NET0_araddr(M_AXI_NET0_ARADDR), + .M_AXI_NET0_arprot(), + .M_AXI_NET0_arready(M_AXI_NET0_ARREADY), + .M_AXI_NET0_arvalid(M_AXI_NET0_ARVALID), + + .M_AXI_NET0_awaddr(M_AXI_NET0_AWADDR), + .M_AXI_NET0_awprot(), + .M_AXI_NET0_awready(M_AXI_NET0_AWREADY), + .M_AXI_NET0_awvalid(M_AXI_NET0_AWVALID), + + .M_AXI_NET0_bready(M_AXI_NET0_BREADY), + .M_AXI_NET0_bresp(M_AXI_NET0_BRESP), + .M_AXI_NET0_bvalid(M_AXI_NET0_BVALID), + + .M_AXI_NET0_rdata(M_AXI_NET0_RDATA), + .M_AXI_NET0_rready(M_AXI_NET0_RREADY), + .M_AXI_NET0_rresp(M_AXI_NET0_RRESP), + .M_AXI_NET0_rvalid(M_AXI_NET0_RVALID), + + .M_AXI_NET0_wdata(M_AXI_NET0_WDATA), + .M_AXI_NET0_wready(M_AXI_NET0_WREADY), + .M_AXI_NET0_wstrb(M_AXI_NET0_WSTRB), + .M_AXI_NET0_wvalid(M_AXI_NET0_WVALID), + + .M_AXI_NET1_araddr(M_AXI_NET1_ARADDR), + .M_AXI_NET1_arprot(), + .M_AXI_NET1_arready(M_AXI_NET1_ARREADY), + .M_AXI_NET1_arvalid(M_AXI_NET1_ARVALID), + + .M_AXI_NET1_awaddr(M_AXI_NET1_AWADDR), + .M_AXI_NET1_awprot(), + .M_AXI_NET1_awready(M_AXI_NET1_AWREADY), + .M_AXI_NET1_awvalid(M_AXI_NET1_AWVALID), + + .M_AXI_NET1_bready(M_AXI_NET1_BREADY), + .M_AXI_NET1_bresp(M_AXI_NET1_BRESP), + .M_AXI_NET1_bvalid(M_AXI_NET1_BVALID), + + .M_AXI_NET1_rdata(M_AXI_NET1_RDATA), + .M_AXI_NET1_rready(M_AXI_NET1_RREADY), + .M_AXI_NET1_rresp(M_AXI_NET1_RRESP), + .M_AXI_NET1_rvalid(M_AXI_NET1_RVALID), + + .M_AXI_NET1_wdata(M_AXI_NET1_WDATA), + .M_AXI_NET1_wready(M_AXI_NET1_WREADY), + .M_AXI_NET1_wstrb(M_AXI_NET1_WSTRB), + .M_AXI_NET1_wvalid(M_AXI_NET1_WVALID), + + .M_AXI_NET2_araddr(M_AXI_NET2_ARADDR), + .M_AXI_NET2_arprot(), + .M_AXI_NET2_arready(M_AXI_NET2_ARREADY), + .M_AXI_NET2_arvalid(M_AXI_NET2_ARVALID), + + .M_AXI_NET2_awaddr(M_AXI_NET2_AWADDR), + .M_AXI_NET2_awprot(), + .M_AXI_NET2_awready(M_AXI_NET2_AWREADY), + .M_AXI_NET2_awvalid(M_AXI_NET2_AWVALID), + + .M_AXI_NET2_bready(M_AXI_NET2_BREADY), + .M_AXI_NET2_bresp(M_AXI_NET2_BRESP), + .M_AXI_NET2_bvalid(M_AXI_NET2_BVALID), + + .M_AXI_NET2_rdata(M_AXI_NET2_RDATA), + .M_AXI_NET2_rready(M_AXI_NET2_RREADY), + .M_AXI_NET2_rresp(M_AXI_NET2_RRESP), + .M_AXI_NET2_rvalid(M_AXI_NET2_RVALID), + + .M_AXI_NET2_wdata(M_AXI_NET2_WDATA), + .M_AXI_NET2_wready(M_AXI_NET2_WREADY), + .M_AXI_NET2_wstrb(M_AXI_NET2_WSTRB), + .M_AXI_NET2_wvalid(M_AXI_NET2_WVALID), + + .M_AXI_WR_CLK(m_axi_wr_clk), + .M_AXI_WR_RSTn(1'b1), + .M_AXI_WR_araddr(m_axi_wr_araddr), + .M_AXI_WR_arready(m_axi_wr_arready), + .M_AXI_WR_arvalid(m_axi_wr_arvalid), + .M_AXI_WR_awaddr(m_axi_wr_awaddr), + .M_AXI_WR_awready(m_axi_wr_awready), + .M_AXI_WR_awvalid(m_axi_wr_awvalid), + .M_AXI_WR_bready(m_axi_wr_bready), + .M_AXI_WR_bresp(m_axi_wr_bresp), + .M_AXI_WR_bvalid(m_axi_wr_bvalid), + .M_AXI_WR_rdata(m_axi_wr_rdata), + .M_AXI_WR_rready(m_axi_wr_rready), + .M_AXI_WR_rresp(m_axi_wr_rresp), + .M_AXI_WR_rvalid(m_axi_wr_rvalid), + .M_AXI_WR_wdata(m_axi_wr_wdata), + .M_AXI_WR_wready(m_axi_wr_wready), + .M_AXI_WR_wstrb(m_axi_wr_wstrb), + .M_AXI_WR_wvalid(m_axi_wr_wvalid), + + .M_AXI_XBAR_araddr(M_AXI_XBAR_ARADDR), + .M_AXI_XBAR_arprot(), + .M_AXI_XBAR_arready(M_AXI_XBAR_ARREADY), + .M_AXI_XBAR_arvalid(M_AXI_XBAR_ARVALID), + + .M_AXI_XBAR_awaddr(M_AXI_XBAR_AWADDR), + .M_AXI_XBAR_awprot(), + .M_AXI_XBAR_awready(M_AXI_XBAR_AWREADY), + .M_AXI_XBAR_awvalid(M_AXI_XBAR_AWVALID), + + .M_AXI_XBAR_bready(M_AXI_XBAR_BREADY), + .M_AXI_XBAR_bresp(M_AXI_XBAR_BRESP), + .M_AXI_XBAR_bvalid(M_AXI_XBAR_BVALID), + + .M_AXI_XBAR_rdata(M_AXI_XBAR_RDATA), + .M_AXI_XBAR_rready(M_AXI_XBAR_RREADY), + .M_AXI_XBAR_rresp(M_AXI_XBAR_RRESP), + .M_AXI_XBAR_rvalid(M_AXI_XBAR_RVALID), + + .M_AXI_XBAR_wdata(M_AXI_XBAR_WDATA), + .M_AXI_XBAR_wready(M_AXI_XBAR_WREADY), + .M_AXI_XBAR_wstrb(M_AXI_XBAR_WSTRB), + .M_AXI_XBAR_wvalid(M_AXI_XBAR_WVALID), + + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR), + .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST), + .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE), + .S_AXI_GP0_arid(S_AXI_GP0_ARID), + .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN), + .S_AXI_GP0_arlock(1'b0), + .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT), + .S_AXI_GP0_arqos(4'b0000), + .S_AXI_GP0_arready(S_AXI_GP0_ARREADY), + .S_AXI_GP0_arsize(S_AXI_GP0_ARSIZE), + .S_AXI_GP0_arvalid(S_AXI_GP0_ARVALID), + .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR), + .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST), + .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE), + .S_AXI_GP0_awid(S_AXI_GP0_AWID), + .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN), + .S_AXI_GP0_awlock(1'b0), + .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT), + .S_AXI_GP0_awqos(4'b0000), + .S_AXI_GP0_awregion(4'b0000), + .S_AXI_GP0_awready(S_AXI_GP0_AWREADY), + .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE), + .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID), + .S_AXI_GP0_bid(), + .S_AXI_GP0_bready(S_AXI_GP0_BREADY), + .S_AXI_GP0_bresp(S_AXI_GP0_BRESP), + .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID), + .S_AXI_GP0_rdata(S_AXI_GP0_RDATA), + .S_AXI_GP0_rid(), + .S_AXI_GP0_rlast(S_AXI_GP0_RLAST), + .S_AXI_GP0_rready(S_AXI_GP0_RREADY), + .S_AXI_GP0_rresp(S_AXI_GP0_RRESP), + .S_AXI_GP0_rvalid(S_AXI_GP0_RVALID), + .S_AXI_GP0_wdata(S_AXI_GP0_WDATA), + .S_AXI_GP0_wlast(S_AXI_GP0_WLAST), + .S_AXI_GP0_wready(S_AXI_GP0_WREADY), + .S_AXI_GP0_wstrb(S_AXI_GP0_WSTRB), + .S_AXI_GP0_wvalid(S_AXI_GP0_WVALID), + + .S_AXI_GP1_ACLK(clk40), + .S_AXI_GP1_ARESETN(clk40_rstn), + .S_AXI_GP1_araddr(S_AXI_GP1_ARADDR), + .S_AXI_GP1_arburst(S_AXI_GP1_ARBURST), + .S_AXI_GP1_arcache(S_AXI_GP1_ARCACHE), + .S_AXI_GP1_arid(S_AXI_GP1_ARID), + .S_AXI_GP1_arlen(S_AXI_GP1_ARLEN), + .S_AXI_GP1_arlock(1'b0), + .S_AXI_GP1_arprot(S_AXI_GP1_ARPROT), + .S_AXI_GP1_arqos(4'b000), + .S_AXI_GP1_arready(S_AXI_GP1_ARREADY), + .S_AXI_GP1_arsize(S_AXI_GP1_ARSIZE), + .S_AXI_GP1_arvalid(S_AXI_GP1_ARVALID), + .S_AXI_GP1_awaddr(S_AXI_GP1_AWADDR), + .S_AXI_GP1_awburst(S_AXI_GP1_AWBURST), + .S_AXI_GP1_awcache(S_AXI_GP1_AWCACHE), + .S_AXI_GP1_awid(S_AXI_GP1_AWID), + .S_AXI_GP1_awlen(S_AXI_GP1_AWLEN), + .S_AXI_GP1_awlock(1'b0), + .S_AXI_GP1_awprot(S_AXI_GP1_AWPROT), + .S_AXI_GP1_awqos(4'b0000), + .S_AXI_GP1_awregion(4'b0000), + .S_AXI_GP1_awready(S_AXI_GP1_AWREADY), + .S_AXI_GP1_awsize(S_AXI_GP1_AWSIZE), + .S_AXI_GP1_awvalid(S_AXI_GP1_AWVALID), + .S_AXI_GP1_bid(), + .S_AXI_GP1_bready(S_AXI_GP1_BREADY), + .S_AXI_GP1_bresp(S_AXI_GP1_BRESP), + .S_AXI_GP1_bvalid(S_AXI_GP1_BVALID), + .S_AXI_GP1_rdata(S_AXI_GP1_RDATA), + .S_AXI_GP1_rid(), + .S_AXI_GP1_rlast(S_AXI_GP1_RLAST), + .S_AXI_GP1_rready(S_AXI_GP1_RREADY), + .S_AXI_GP1_rresp(S_AXI_GP1_RRESP), + .S_AXI_GP1_rvalid(S_AXI_GP1_RVALID), + .S_AXI_GP1_wdata(S_AXI_GP1_WDATA), + .S_AXI_GP1_wlast(S_AXI_GP1_WLAST), + .S_AXI_GP1_wready(S_AXI_GP1_WREADY), + .S_AXI_GP1_wstrb(S_AXI_GP1_WSTRB), + .S_AXI_GP1_wvalid(S_AXI_GP1_WVALID), + + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR), + .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST), + .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_arid(S_AXI_HP0_ARID), + .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT), + .S_AXI_HP0_arqos(4'b0000), + .S_AXI_HP0_arready(S_AXI_HP0_ARREADY), + .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID), + .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR), + .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST), + .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_awid(S_AXI_HP0_AWID), + .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT), + .S_AXI_HP0_awqos(4'b0000), + .S_AXI_HP0_awready(S_AXI_HP0_AWREADY), + .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(S_AXI_HP0_BREADY), + .S_AXI_HP0_bresp(S_AXI_HP0_BRESP), + .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID), + .S_AXI_HP0_rdata(S_AXI_HP0_RDATA), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(S_AXI_HP0_RLAST), + .S_AXI_HP0_rready(S_AXI_HP0_RREADY), + .S_AXI_HP0_rresp(S_AXI_HP0_RRESP), + .S_AXI_HP0_rvalid(S_AXI_HP0_RVALID), + .S_AXI_HP0_wdata(S_AXI_HP0_WDATA), + .S_AXI_HP0_wlast(S_AXI_HP0_WLAST), + .S_AXI_HP0_wready(S_AXI_HP0_WREADY), + .S_AXI_HP0_wstrb(S_AXI_HP0_WSTRB), + .S_AXI_HP0_wvalid(S_AXI_HP0_WVALID), + + .S_AXI_HP1_ACLK(clk40), + .S_AXI_HP1_ARESETN(clk40_rstn), + .S_AXI_HP1_araddr(S_AXI_HP1_ARADDR), + .S_AXI_HP1_arburst(S_AXI_HP1_ARBURST), + .S_AXI_HP1_arcache(S_AXI_HP1_ARCACHE), + .S_AXI_HP1_arid(S_AXI_HP1_ARID), + .S_AXI_HP1_arlen(S_AXI_HP1_ARLEN), + .S_AXI_HP1_arlock(1'b0), + .S_AXI_HP1_arprot(S_AXI_HP1_ARPROT), + .S_AXI_HP1_arqos(4'b0000), + .S_AXI_HP1_arready(S_AXI_HP1_ARREADY), + .S_AXI_HP1_arsize(S_AXI_HP1_ARSIZE), + .S_AXI_HP1_arvalid(S_AXI_HP1_ARVALID), + .S_AXI_HP1_awaddr(S_AXI_HP1_AWADDR), + .S_AXI_HP1_awburst(S_AXI_HP1_AWBURST), + .S_AXI_HP1_awcache(S_AXI_HP1_AWCACHE), + .S_AXI_HP1_awid(S_AXI_HP1_AWID), + .S_AXI_HP1_awlen(S_AXI_HP1_AWLEN), + .S_AXI_HP1_awlock(1'b0), + .S_AXI_HP1_awprot(S_AXI_HP1_AWPROT), + .S_AXI_HP1_awqos(4'b0000), + .S_AXI_HP1_awready(S_AXI_HP1_AWREADY), + .S_AXI_HP1_awsize(S_AXI_HP1_AWSIZE), + .S_AXI_HP1_awvalid(S_AXI_HP1_AWVALID), + .S_AXI_HP1_bid(), + .S_AXI_HP1_bready(S_AXI_HP1_BREADY), + .S_AXI_HP1_bresp(S_AXI_HP1_BRESP), + .S_AXI_HP1_bvalid(S_AXI_HP1_BVALID), + .S_AXI_HP1_rdata(S_AXI_HP1_RDATA), + .S_AXI_HP1_rid(), + .S_AXI_HP1_rlast(S_AXI_HP1_RLAST), + .S_AXI_HP1_rready(S_AXI_HP1_RREADY), + .S_AXI_HP1_rresp(S_AXI_HP1_RRESP), + .S_AXI_HP1_rvalid(S_AXI_HP1_RVALID), + .S_AXI_HP1_wdata(S_AXI_HP1_WDATA), + .S_AXI_HP1_wlast(S_AXI_HP1_WLAST), + .S_AXI_HP1_wready(S_AXI_HP1_WREADY), + .S_AXI_HP1_wstrb(S_AXI_HP1_WSTRB), + .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID), + + // ARM DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid), + + // Misc Interrupts, GPIO, clk + .IRQ_F2P(IRQ_F2P), + + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + .JTAG0_TCK(DBA_CPLD_JTAG_TCK), + .JTAG0_TMS(DBA_CPLD_JTAG_TMS), + .JTAG0_TDI(DBA_CPLD_JTAG_TDI), + .JTAG0_TDO(DBA_CPLD_JTAG_TDO), + + `ifndef N300 + .JTAG1_TCK(DBB_CPLD_JTAG_TCK), + .JTAG1_TMS(DBB_CPLD_JTAG_TMS), + .JTAG1_TDI(DBB_CPLD_JTAG_TDI), + .JTAG1_TDO(DBB_CPLD_JTAG_TDO), + `else + .JTAG1_TCK(), + .JTAG1_TMS(), + .JTAG1_TDI(), + .JTAG1_TDO('b0), + `endif + + .FCLK_CLK0(FCLK_CLK0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_RESET1_N(), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_RESET2_N(), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET3_N(), + + .WR_UART_txd(wr_uart_rxd), // rx <-> tx + .WR_UART_rxd(wr_uart_txd), // rx <-> tx + + .qsfp_sda_i(qsfp_sda_i), + .qsfp_sda_o(qsfp_sda_o), + .qsfp_sda_t(qsfp_sda_t), + .qsfp_scl_i(qsfp_scl_i), + .qsfp_scl_o(qsfp_scl_o), + .qsfp_scl_t(qsfp_scl_t), + + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + // Outward connections to the pins + .MIO(MIO), + .DDR_cas_n(DDR_CAS_n), + .DDR_cke(DDR_CKE), + .DDR_ck_n(DDR_Clk_n), + .DDR_ck_p(DDR_Clk), + .DDR_cs_n(DDR_CS_n), + .DDR_reset_n(DDR_DRSTB), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_n), + .DDR_we_n(DDR_WEB), + .DDR_ba(DDR_BankAddr), + .DDR_addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_n), + .DDR_dqs_p(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); + + /////////////////////////////////////////////////////////////////////////////////// + // + // Xilinx DDR3 Controller and PHY. + // + /////////////////////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (200MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + + // Instantiate the DDR3 MIG core + // + // The top-level IP block has no parameters defined for some reason. + // Most of configurable parameters are hard-coded in the mig so get + // some additional knobs we pull those out into verilog headers. + // + // Synthesis params: ip/ddr3_32bit/ddr3_32bit_mig_parameters.vh + // Simulation params: ip/ddr3_32bit/ddr3_32bit_mig_sim_parameters.vh + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 200Hz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 200 MHz. + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + + .sys_rst (~global_rst) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL("INTERNAL"), + .XADC_CLK_PERIOD(5000 /* 200MHz clock period in ps */) + ) tempmon_i ( + .clk(bus_clk), .xadc_clk(bus_clk), .rst(bus_rst), + .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) + ); + + /////////////////////////////////////////////////////// + // + // DB PS SPI Connections + // + /////////////////////////////////////////////////////// + wire [NUM_CHANNELS-1:0] rx_atr; + wire [NUM_CHANNELS-1:0] tx_atr; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] rx_atr_reg; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] tx_atr_reg; + + // Radio GPIO control for DSA + wire [16*NUM_CHANNELS-1:0] db_gpio_out; + wire [16*NUM_CHANNELS-1:0] db_gpio_ddr; + wire [16*NUM_CHANNELS-1:0] db_gpio_in; + wire [16*NUM_CHANNELS-1:0] db_gpio_fab; + + // DB A SPI Connections + wire cpld_a_cs_n; + wire lmk_a_cs_n; + wire dac_a_cs_n; + wire myk_a_cs_n; + + // Split out the SCLK and MOSI data to Mykonos and the CPLD. + assign DBA_CPLD_PS_SPI_SCLK = spi0_sclk; + assign DBA_CPLD_PS_SPI_SDI = spi0_mosi; + + assign DBA_MYK_SPI_SCLK = spi0_sclk; + assign DBA_MYK_SPI_SDIO = spi0_mosi; + // Assign individual chip selects from PS SPI MASTER 0. + assign cpld_a_cs_n = spi0_ss0; + assign lmk_a_cs_n = spi0_ss1; + assign dac_a_cs_n = ps_gpio_out[8]; // DAC select driven through GPIO. + assign myk_a_cs_n = spi0_ss2; + + // Returned data mux from the SPI interfaces. + assign spi0_miso = ~myk_a_cs_n ? DBA_MYK_SPI_SDO : // From Mykonos + DBA_CPLD_PS_SPI_SDO; + + // For the PS SPI connection to the CPLD, we use the LE and ADDR lines as individual + // chip selects for the CPLD endpoint as well as the LMK and DAC endpoints. + // LE = CPLD + // ADDR[0] = LMK + // ADDR[1] = DAC + assign DBA_CPLD_PS_SPI_LE = cpld_a_cs_n; + assign DBA_CPLD_PS_SPI_ADDR[0] = lmk_a_cs_n; + assign DBA_CPLD_PS_SPI_ADDR[1] = dac_a_cs_n; + assign DBA_MYK_SPI_CS_n = myk_a_cs_n; + + // Instantiate DSA registers in the IOB + (* IOB = "true" *) reg [5:0] dsa_tx1_a_out_iob, dsa_rx1_a_out_iob; + (* IOB = "true" *) reg [5:0] dsa_tx2_a_out_iob, dsa_rx2_a_out_iob; + always @(posedge radio_clk) begin + dsa_tx1_a_out_iob <= db_gpio_out[16*0+11:16*0+6]; + dsa_rx1_a_out_iob <= db_gpio_out[16*0+5:16*0+0]; + dsa_tx2_a_out_iob <= db_gpio_out[16*1+11:16*1+6]; + dsa_rx2_a_out_iob <= db_gpio_out[16*1+5:16*1+0]; + end + + assign DBA_CH1_TX_DSA_DATA = dsa_tx1_a_out_iob; + assign DBA_CH1_RX_DSA_DATA = dsa_rx1_a_out_iob; + assign DBA_CH2_TX_DSA_DATA = dsa_tx2_a_out_iob; + assign DBA_CH2_RX_DSA_DATA = dsa_rx2_a_out_iob; + + assign DBA_ATR_RX_1 = rx_atr_reg[0]; + assign DBA_ATR_RX_2 = rx_atr_reg[1]; + assign DBA_ATR_TX_1 = tx_atr_reg[0]; + assign DBA_ATR_TX_2 = tx_atr_reg[1]; + + assign DBA_MYK_GPIO_0 = 1'b0; + assign DBA_MYK_GPIO_1 = 1'b0; + assign DBA_MYK_GPIO_3 = 1'b0; + assign DBA_MYK_GPIO_4 = 1'b0; + assign DBA_MYK_GPIO_12 = 1'b0; + assign DBA_MYK_GPIO_13 = 1'b0; + assign DBA_MYK_GPIO_14 = 1'b0; + assign DBA_MYK_GPIO_15 = 1'b0; + +`ifndef N300 + + // DB B SPI Connections + wire cpld_b_cs_n; + wire lmk_b_cs_n; + wire dac_b_cs_n; + wire myk_b_cs_n; + + // Split out the SCLK and MOSI data to Mykonos and the CPLD. + assign DBB_CPLD_PS_SPI_SCLK = spi1_sclk; + assign DBB_CPLD_PS_SPI_SDI = spi1_mosi; + + assign DBB_MYK_SPI_SCLK = spi1_sclk; + assign DBB_MYK_SPI_SDIO = spi1_mosi; + + // Assign individual chip selects from PS SPI MASTER 1. + assign cpld_b_cs_n = spi1_ss0; + assign lmk_b_cs_n = spi1_ss1; + assign dac_b_cs_n = ps_gpio_out[9]; // DAC select driven through GPIO. + assign myk_b_cs_n = spi1_ss2; + + // Returned data mux from the SPI interfaces. + assign spi1_miso = ~myk_b_cs_n ? DBB_MYK_SPI_SDO : // From Mykonos + DBB_CPLD_PS_SPI_SDO; + + // For the PS SPI connection to the CPLD, we use the LE and ADDR lines as individual + // chip selects for the CPLD endpoint as well as the LMK and DAC endpoints. + // LE = CPLD + // ADDR[0] = LMK + // ADDR[1] = DAC + assign DBB_CPLD_PS_SPI_LE = cpld_b_cs_n; + assign DBB_CPLD_PS_SPI_ADDR[0] = lmk_b_cs_n; + assign DBB_CPLD_PS_SPI_ADDR[1] = dac_b_cs_n; + assign DBB_MYK_SPI_CS_n = myk_b_cs_n; + + // Instantiate DSA registers in the IOB + (* IOB = "true" *) reg [5:0] dsa_tx1_b_out_iob, dsa_rx1_b_out_iob; + (* IOB = "true" *) reg [5:0] dsa_tx2_b_out_iob, dsa_rx2_b_out_iob; + always @(posedge radio_clk) begin + dsa_tx1_b_out_iob <= db_gpio_out[16*2+11:16*2+6]; + dsa_rx1_b_out_iob <= db_gpio_out[16*2+5:16*2+0]; + dsa_tx2_b_out_iob <= db_gpio_out[16*3+11:16*3+6]; + dsa_rx2_b_out_iob <= db_gpio_out[16*3+5:16*3+0]; + end + + assign DBB_CH1_TX_DSA_DATA = dsa_tx1_b_out_iob; + assign DBB_CH1_RX_DSA_DATA = dsa_rx1_b_out_iob; + assign DBB_CH2_TX_DSA_DATA = dsa_tx2_b_out_iob; + assign DBB_CH2_RX_DSA_DATA = dsa_rx2_b_out_iob; + + assign DBB_ATR_RX_1 = rx_atr_reg[2]; + assign DBB_ATR_RX_2 = rx_atr_reg[3]; + assign DBB_ATR_TX_1 = tx_atr_reg[2]; + assign DBB_ATR_TX_2 = tx_atr_reg[3]; + + assign DBB_MYK_GPIO_0 = 1'b0; + assign DBB_MYK_GPIO_1 = 1'b0; + assign DBB_MYK_GPIO_3 = 1'b0; + assign DBB_MYK_GPIO_4 = 1'b0; + assign DBB_MYK_GPIO_12 = 1'b0; + assign DBB_MYK_GPIO_13 = 1'b0; + assign DBB_MYK_GPIO_14 = 1'b0; + assign DBB_MYK_GPIO_15 = 1'b0; + +`endif + + /////////////////////////////////////////////////////// + // + // N3xx CORE + // + /////////////////////////////////////////////////////// + + wire [31:0] rx[NUM_CHANNELS-1:0]; + wire [31:0] tx[NUM_CHANNELS-1:0]; + wire [32*NUM_CHANNELS-1:0] rx_flat; + wire [32*NUM_CHANNELS-1:0] tx_flat; + + wire [NUM_CHANNELS-1:0] rx_stb; + wire [NUM_CHANNELS-1:0] tx_stb; + + wire [31:0] build_datestamp; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_flat[32*i+31:32*i] = rx[i]; + assign tx[i] = tx_flat[32*i+31:32*i]; + end + endgenerate + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + n3xx_core #( + .REG_AWIDTH(14), + .BUS_CLK_RATE(BUS_CLK_RATE), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + `ifdef USE_REPLAY + .USE_REPLAY(1) + `else + .USE_REPLAY(0) + `endif + ) n3xx_core( + // Clocks and resets + `ifdef NO_DB + .radio_clk(bus_clk), + .radio_rst(bus_rst), + `else + .radio_clk(radio_clk), + .radio_rst(radio_rst), + `endif + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps(pps_radioclk1x), + .pps_select(pps_select), + .pps_out_enb(pps_out_enb), + .pps_select_sfp(pps_select_sfp), + .ref_clk_reset(), + .meas_clk_reset(meas_clk_reset), + .ref_clk_locked(1'b1), + .meas_clk_locked(meas_clk_locked), + .enable_ref_clk_async(enable_ref_clk_async), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_XBAR_AWADDR), + .s_axi_awvalid(M_AXI_XBAR_AWVALID), + .s_axi_awready(M_AXI_XBAR_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_XBAR_WDATA), + .s_axi_wstrb(M_AXI_XBAR_WSTRB), + .s_axi_wvalid(M_AXI_XBAR_WVALID), + .s_axi_wready(M_AXI_XBAR_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_XBAR_BRESP), + .s_axi_bvalid(M_AXI_XBAR_BVALID), + .s_axi_bready(M_AXI_XBAR_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_XBAR_ARADDR), + .s_axi_arvalid(M_AXI_XBAR_ARVALID), + .s_axi_arready(M_AXI_XBAR_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_XBAR_RDATA), + .s_axi_rresp(M_AXI_XBAR_RRESP), + .s_axi_rvalid(M_AXI_XBAR_RVALID), + .s_axi_rready(M_AXI_XBAR_RREADY), + // ps gpio source + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + // FP_GPIO + .fp_gpio_inout(FPGA_GPIO), + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + // Radio GPIO DSA + .db_gpio_out_flat(db_gpio_out), + .db_gpio_in_flat(db_gpio_in), + .db_gpio_ddr_flat(db_gpio_ddr), + .db_gpio_fab_flat(db_gpio_fab), + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + // CPLD RX_LO TX_LO SPI + `ifndef N300 + .sclk_flat({DBB_CPLD_PL_SPI_SCLK, + DBA_CPLD_PL_SPI_SCLK}), + .sen_flat({5'b0,DBB_CPLD_PL_SPI_ADDR[1],DBB_CPLD_PL_SPI_ADDR[0],DBB_CPLD_PL_SPI_LE, + 5'b0,DBA_CPLD_PL_SPI_ADDR[1],DBA_CPLD_PL_SPI_ADDR[0],DBA_CPLD_PL_SPI_LE}), + .mosi_flat({DBB_CPLD_PL_SPI_SDI, + DBA_CPLD_PL_SPI_SDI}), + .miso_flat({DBB_CPLD_PL_SPI_SDO, + DBA_CPLD_PL_SPI_SDO}), + `else + .sclk_flat(DBA_CPLD_PL_SPI_SCLK), + .sen_flat({5'b0,DBA_CPLD_PL_SPI_ADDR[1],DBA_CPLD_PL_SPI_ADDR[0],DBA_CPLD_PL_SPI_LE}), + .mosi_flat(DBA_CPLD_PL_SPI_SDI), + .miso_flat(DBA_CPLD_PL_SPI_SDO), + `endif + // DRAM signals + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e0_tdata(v2e0_tdata), + .v2e0_tvalid(v2e0_tvalid), + .v2e0_tlast(v2e0_tlast), + .v2e0_tready(v2e0_tready), + + .v2e1_tdata(v2e1_tdata), + .v2e1_tlast(v2e1_tlast), + .v2e1_tvalid(v2e1_tvalid), + .v2e1_tready(v2e1_tready), + + // Ethernet to VITA + .e2v0_tdata(e2v0_tdata), + .e2v0_tlast(e2v0_tlast), + .e2v0_tvalid(e2v0_tvalid), + .e2v0_tready(e2v0_tready), + + .e2v1_tdata(e2v1_tdata), + .e2v1_tlast(e2v1_tlast), + .e2v1_tvalid(e2v1_tvalid), + .e2v1_tready(e2v1_tready), + + //regport interface to npio + .reg_wr_req_npio(reg_wr_req_npio), + .reg_wr_addr_npio(reg_wr_addr_npio), + .reg_wr_data_npio(reg_wr_data_npio), + .reg_rd_req_npio(reg_rd_req_npio), + .reg_rd_addr_npio(reg_rd_addr_npio), + .reg_rd_resp_npio(reg_rd_resp_npio), + .reg_rd_data_npio(reg_rd_data_npio), + + .build_datestamp(build_datestamp), + .xadc_readback({20'h0, device_temp}), + .sfp_ports_info({sfp_port1_info, sfp_port0_info}), + .device_id(device_id) + ); + + // Register the ATR bits once between sending them out to the CPLD to avoid + // glitches on the outputs! + always @(posedge radio_clk) begin + rx_atr_reg <= rx_atr; + tx_atr_reg <= tx_atr; + end + + // ////////////////////////////////////////////////////////////////////// + // + // Daughterboard Cores + // + // ////////////////////////////////////////////////////////////////////// + + wire [49:0] bRegPortInFlatA; + wire [33:0] bRegPortOutFlatA; + wire rx_a_valid; + wire tx_a_rfi; +`ifndef N300 + wire [49:0] bRegPortInFlatB; + wire [33:0] bRegPortOutFlatB; + wire rx_b_valid; + wire tx_b_rfi; +`endif + +`ifdef BUILD_WR + localparam INCL_WR_TDC = 1'b1; +`else + localparam INCL_WR_TDC = 1'b0; +`endif + + wire reg_portA_rd; + wire reg_portA_wr; + wire [14-1:0] reg_portA_addr; + wire [32-1:0] reg_portA_wr_data; + wire [32-1:0] reg_portA_rd_data; + wire reg_portA_ready; + wire validA_unused; + + assign bRegPortInFlatA = {2'b0, reg_portA_addr, reg_portA_wr_data, reg_portA_rd, reg_portA_wr}; + assign {reg_portA_rd_data, validA_unused, reg_portA_ready} = bRegPortOutFlatA; + + DbCore #( + .kInclWhiteRabbitTdc(INCL_WR_TDC) + ) dba_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBA_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBA_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clk), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2x), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatA), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatA), //out std_logic_vector(33:0) + .kSlotId(1'b0), //in std_logic + .sSysRefFpgaLvds_p(DBA_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBA_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBA_CPLD_PL_SPI_ADDR[2]), //out std_logic + .JesdRefClk_p(USRPIO_A_MGTCLK_P), //in std_logic + .JesdRefClk_n(USRPIO_A_MGTCLK_N), //in std_logic + .aAdcRx_p(USRPIO_A_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(USRPIO_A_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(DBA_MYK_SYNC_IN_n), //out std_logic + .aDacTx_p(USRPIO_A_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(USRPIO_A_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(DBA_MYK_SYNC_OUT_n), //in std_logic + .sAdcDataValid(rx_a_valid), //out std_logic + .sAdcDataSamples0I(rx[0][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples0Q(rx[0][15:0]), //out std_logic_vector(15:0) + .sAdcDataSamples1I(rx[1][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples1Q(rx[1][15:0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_a_rfi), //out std_logic + .sDacDataSamples0I(tx[0][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples0Q(tx[0][15:0]), //in std_logic_vector(15:0) + .sDacDataSamples1I(tx[1][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples1Q(tx[1][15:0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCA_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCA_1), //inout std_logic + .sPps(pps_radioclk1x), //out std_logic + .sPpsToIob(pps_radioclk1x_iob), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCA_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCA_3), //inout std_logic + .aPpsSfpSel(pps_select_sfp), //out std_logic_vector(1:0) + .sAdcSync(), //out std_logic + .sDacSync(), //out std_logic + .sSysRef(), //out std_logic + .rRpTransfer(), //out std_logic + .sSpTransfer(), //out std_logic + .rWrRpTransfer(), //out std_logic + .sWrSpTransfer() //out std_logic + ); + + assign rx_stb[0] = rx_a_valid; + assign rx_stb[1] = rx_a_valid; + assign tx_stb[0] = tx_a_rfi; + assign tx_stb[1] = tx_a_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportA_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD0_AWADDR), + .s_axi_awvalid(M_AXI_JESD0_AWVALID), + .s_axi_awready(M_AXI_JESD0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD0_WDATA), + .s_axi_wstrb(M_AXI_JESD0_WSTRB), + .s_axi_wvalid(M_AXI_JESD0_WVALID), + .s_axi_wready(M_AXI_JESD0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD0_BRESP), + .s_axi_bvalid(M_AXI_JESD0_BVALID), + .s_axi_bready(M_AXI_JESD0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD0_ARADDR), + .s_axi_arvalid(M_AXI_JESD0_ARVALID), + .s_axi_arready(M_AXI_JESD0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_JESD0_RDATA), + .s_axi_rresp(M_AXI_JESD0_RRESP), + .s_axi_rvalid(M_AXI_JESD0_RVALID), + .s_axi_rready(M_AXI_JESD0_RREADY), + // Register port + .reg_port_in_rd (reg_portA_rd), + .reg_port_in_wt (reg_portA_wr), + .reg_port_in_addr (reg_portA_addr), + .reg_port_in_data (reg_portA_wr_data), + .reg_port_out_data (reg_portA_rd_data), + .reg_port_out_ready(reg_portA_ready) + ); + +`ifndef N300 + wire reg_portB_rd; + wire reg_portB_wr; + wire [14-1:0] reg_portB_addr; + wire [32-1:0] reg_portB_wr_data; + wire [32-1:0] reg_portB_rd_data; + wire reg_portB_ready; + wire validB_unused; + + assign bRegPortInFlatB = {2'b0, reg_portB_addr, reg_portB_wr_data, reg_portB_rd, reg_portB_wr}; + assign {reg_portB_rd_data, validB_unused, reg_portB_ready} = bRegPortOutFlatB; + + DbCore #( + .kInclWhiteRabbitTdc(INCL_WR_TDC) + ) dbb_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBB_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBB_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatB), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatB), //out std_logic_vector(33:0) + .kSlotId(1'b1), //in std_logic + .sSysRefFpgaLvds_p(DBB_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBB_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBB_CPLD_PL_SPI_ADDR[2]), //out std_logic + .JesdRefClk_p(USRPIO_B_MGTCLK_P), //in std_logic + .JesdRefClk_n(USRPIO_B_MGTCLK_N), //in std_logic + .aAdcRx_p(USRPIO_B_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(USRPIO_B_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(DBB_MYK_SYNC_IN_n), //out std_logic + .aDacTx_p(USRPIO_B_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(USRPIO_B_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(DBB_MYK_SYNC_OUT_n), //in std_logic + .sAdcDataValid(rx_b_valid), //out std_logic + .sAdcDataSamples0I(rx[2][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples0Q(rx[2][15:0]), //out std_logic_vector(15:0) + .sAdcDataSamples1I(rx[3][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples1Q(rx[3][15:0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_b_rfi), //out std_logic + .sDacDataSamples0I(tx[2][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples0Q(tx[2][15:0]), //in std_logic_vector(15:0) + .sDacDataSamples1I(tx[3][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples1Q(tx[3][15:0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCB_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCB_1), //inout std_logic + .sPps(), //out std_logic + .sPpsToIob(), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCB_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCB_3), //inout std_logic + .aPpsSfpSel(2'b0), //out std_logic_vector(1:0) + .sAdcSync(), //out std_logic + .sDacSync(), //out std_logic + .sSysRef(), //out std_logic + .rRpTransfer(), //out std_logic + .sSpTransfer(), //out std_logic + .rWrRpTransfer(), //out std_logic + .sWrSpTransfer() //out std_logic + ); + + assign rx_stb[2] = rx_b_valid; + assign rx_stb[3] = rx_b_valid; + assign tx_stb[2] = tx_b_rfi; + assign tx_stb[3] = tx_b_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportB_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY), + // Register port + .reg_port_in_rd (reg_portB_rd), + .reg_port_in_wt (reg_portB_wr), + .reg_port_in_addr (reg_portB_addr), + .reg_port_in_data (reg_portB_wr_data), + .reg_port_out_data (reg_portB_rd_data), + .reg_port_out_ready(reg_portB_ready) + ); +`else + // Tie off second daughterboard interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_dbb_core ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY) + ); + +`endif + + // ////////////////////////////////////////////////////////////////////// + // + // LEDS + // + // ////////////////////////////////////////////////////////////////////// + + assign PANEL_LED_LINK = ps_gpio_out[45]; + assign PANEL_LED_REF = ps_gpio_out[46]; + assign PANEL_LED_GPS = ps_gpio_out[47]; + + + ///////////////////////////////////////////////////////////////////// + // + // PUDC Workaround + // + ////////////////////////////////////////////////////////////////////// + // This is a workaround for a silicon bug in Series 7 FPGA where a + // race condition with the reading of PUDC during the erase of the FPGA + // image cause glitches on output IO pins. + // + // Workaround: + // - Define the PUDC pin in the XDC file with a pullup. + // - Implements an IBUF on the PUDC input and make sure that it does + // not get optimized out. + (* dont_touch = "true" *) wire fpga_pudc_b_buf; + IBUF pudc_ibuf_i ( + .I(FPGA_PUDC_B), + .O(fpga_pudc_b_buf)); + +endmodule diff --git a/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs new file mode 100644 index 000000000..1296e68e6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs @@ -0,0 +1,32 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +################################################## +# DB IFC Sources +################################################## +RHODIUM_DB_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/db_ifc/, \ +DbCore.vhd \ +DaughterboardRegs.vhd \ +ClockingRegs.vhd \ +PkgRhPersonality.vhd \ +PkgDaughterboardRegMap.vhd \ +PkgClockingRegMap.vhd \ +PkgJesdConfig.vhd \ +PkgAdcDacInterfaceTypes.vhd \ +RadioClocking.vhd \ +Jesd204bXcvrCore.edf \ +)) + +RHODIUM_TOP_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +n3xx.v \ +)) + +RHODIUM_DB_CLOCKS_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +db_clocks.xdc \ +)) + +RHODIUM_DB_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +db_pins.xdc \ +db_timing.xdc \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile new file mode 100644 index 000000000..ff1598894 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile @@ -0,0 +1,27 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +.PHONY: all clean + +SRCS=rhodium_top.qpf rhodium_top.qsf rhodium_top.sdc rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v +SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v +SHORT_HASH=$(addprefix GIT_HASH=,$(shell ../../../../../tools/scripts/git-hash.sh)) + +all: cpld-rhodium-revb.svf + +output_files/rhodium_top.pof: $(SRCS) + quartus_map rhodium_top --verilog_macro="$(SHORT_HASH)" + quartus_fit rhodium_top + quartus_asm rhodium_top + quartus_sta rhodium_top + +cpld-rhodium-revb.svf: output_files/rhodium_top.pof + quartus_cpf --convert --frequency 10.0MHz --voltage 2.5 --operation p $? $@ + +clean: + rm -rf db incremental_db output_files simulation cpld-rhodium-revb.svf + +a.out: $(SIM_SRCS) + iverilog -tvvp -D$(SHORT_HASH) -s rh_tb $(SIM_SRCS) + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v new file mode 100644 index 000000000..fb5f62328 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v @@ -0,0 +1,410 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rh_tb +// Simple testbench for rhodium_top +// This creates a rudimentary stimulus only, to allow results to be viewed +// in the waveform viewer +////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + + +module rh_tb; + +reg ADC_A_Over_Range_18, ADC_B_Over_Range_18; + +wire [13:0] usrpio_io; // TODO: use one of these as pl_spi_addr[3] + +wire CPLD_PS_SPI_LE_25, CPLD_PS_SPI_CLK_25, + CPLD_PS_ADDR0_25, CPLD_PS_ADDR1_25, CPLD_PS_SPI_SDI_25; +wire CPLD_PS_SPI_SDO_25; + +wire CPLD_PL_SPI_SDO_18; +wire CPLD_PL_SPI_LE_18, CPLD_PL_SPI_SCLK_18, + CPLD_PL_SPI_SDI_18, + CPLD_PL_SPI_ADDR0_18, CPLD_PL_SPI_ADDR1_18, + CPLD_PL_SPI_ADDR2_18, + CPLD_ATR_TX_18, CPLD_ATR_RX_18; +// NOTE: TxRx front-end switches are driven direct from the motherboard, so these ATR +// lines have no function at this time. + +wire ADC_SPI_CS_L_18, ADC_SPI_SCLK_18; +wire ADC_SPI_SDIO_18; + +wire DAC_SPI_CS_L_18, DAC_SPI_SCLK_18; +wire DAC_SPI_SDIO_18; +reg DAC_Alarm_18; // TODO: drive to gpio? + +wire PHDAC_SPI_CS_L, PHDAC_SPI_SCLK, PHDAC_SPI_SDI; + + +reg LO_SYNC; + +wire CLKDIST_SPI_CS_L, + CLKDIST_SPI_SCLK; +wire CLKDIST_SPI_SDIO; + +wire Tx_DSA_C1, + Tx_DSA_C2, + Tx_DSA_C4, + Tx_DSA_C8, + Tx_DSA_C16; + wire Tx_DSA1_LE, + Tx_DSA2_LE; + wire Tx_Sw1_Ctrl_1, + Tx_Sw1_Ctrl_2, + Tx_Sw2_Ctrl_1, + Tx_Sw2_Ctrl_2, + Tx_Sw3_Ctrl_1, + Tx_Sw3_Ctrl_2, + Tx_Sw3_Ctrl_3, + Tx_Sw3_Ctrl_4, + Rx_LO_Input_Select, + Rx_LO_Filter_Sw_1, + Rx_LO_Filter_Sw_2, + Tx_LO_Input_Select, + Tx_LO_Filter_Sw_1, + Tx_LO_Filter_Sw_2; +wire CLKDIST_Status_LD1, + CLKDIST_Status_LD2; +wire LOSYNTH_RX_MUXOUT, + LOSYNTH_TX_MUXOUT; + +wire LO_SPI_SCLK, + LO_SPI_SDI, + LO_TX_CS_L, + LO_RX_CS_L, + Rx_Sw1_Ctrl_1, + Rx_Sw1_Ctrl_2, + Rx_DSA_C1, + Rx_DSA_C2, + Rx_DSA_C4, + Rx_DSA_C8, + Rx_DSA_C16; + wire Rx_DSA1_LE, + Rx_DSA2_LE; + wire Rx_Sw2_Ctrl, + Rx_Sw3_Ctrl_1, + Rx_Sw3_Ctrl_2, + Rx_Sw4_Ctrl_1, + Rx_Sw4_Ctrl_2, + Rx_Sw4_Ctrl_3, + Rx_Sw4_Ctrl_4, + Rx_Demod_ADJ_1, + Rx_Demod_ADJ_2; +wire LO_DSA_C1, + LO_DSA_C2, + LO_DSA_C4, + LO_DSA_C8, + LO_DSA_C16; +wire RxLO_DSA_LE, + TxLO_DSA_LE; +wire LODIST_Bd_SPI_CS_L, + LODIST_Bd_SPI_SDI, + LODIST_Bd_SPI_SCLK, + Tx_Sw5_Ctrl_1, + Tx_Sw5_Ctrl_2, + Rx_Sw6_Ctrl_1, + Rx_Sw6_Ctrl_2; +wire LODIST_Bd_IO1; +wire Tx_HB_LB_Select, +Rx_HB_LB_Select, +Cal_iso_Sw_Ctrl; + + +parameter dly = 20; + +integer scnt; +integer acnt; +integer ccnt; +integer ccnt_max; + +reg ps_sck; +reg ps_mosi; +reg clkdis_cs_b; +reg cpld_ps_cs_b; +reg phdac_cs_b; +reg adc_cs_b; +reg dac_cs_b; + +reg pl_sck; +reg pl_mosi; +reg txlo_cs_b; +reg rxlo_cs_b; +reg lodis_cs_b; +reg cpld_pl_cs_b; + +task ps_cpld_xfer; + input [1:0] tbl; + input [5:0] cmd; + input [15:0] data; + reg [23:0] shiftreg; + integer i; +begin + ps_sck <= 1'b0; + clkdis_cs_b <= 1'b1; + cpld_ps_cs_b <= 1'b1; + phdac_cs_b <= 1'b1; + adc_cs_b <= 1'b1; + dac_cs_b <= 1'b1; + txlo_cs_b <= 1'b1; + rxlo_cs_b <= 1'b1; + lodis_cs_b <= 1'b1; + cpld_pl_cs_b <= 1'b1; + shiftreg <= {tbl,cmd,data}; + #(dly); + cpld_ps_cs_b <= 1'b0; + #(dly); + for (i = 0; i < 24; i = i + 1) begin + ps_sck <= 1'b0; + ps_mosi <= shiftreg[23-i]; + #(dly); + ps_sck <= 1'b1; + #(dly); + end + ps_sck <= 1'b0; + #(dly); + cpld_ps_cs_b <= 1'b1; + #(dly); +end +endtask + +task pl_cpld_xfer; + input [1:0] tbl; + input [5:0] cmd; + input [15:0] data; + reg [23:0] shiftreg; + integer i; +begin + pl_sck <= 1'b0; + clkdis_cs_b <= 1'b1; + cpld_ps_cs_b <= 1'b1; + phdac_cs_b <= 1'b1; + adc_cs_b <= 1'b1; + dac_cs_b <= 1'b1; + txlo_cs_b <= 1'b1; + rxlo_cs_b <= 1'b1; + lodis_cs_b <= 1'b1; + cpld_pl_cs_b <= 1'b1; + shiftreg <= {tbl,cmd,data}; + #(dly); + cpld_pl_cs_b <= 1'b0; + #(dly); + for (i = 0; i < 24; i = i + 1) begin + pl_sck <= 1'b0; + pl_mosi <= shiftreg[23-i]; + #(dly); + pl_sck <= 1'b1; + #(dly); + end + pl_sck <= 1'b0; + #(dly); + cpld_pl_cs_b <= 1'b1; + #(dly); +end +endtask + +assign CPLD_PS_SPI_LE_25 = clkdis_cs_b; +assign CPLD_PS_ADDR0_25 = cpld_ps_cs_b; +assign CPLD_PS_ADDR1_25 = phdac_cs_b; +assign usrpio_io[12] = adc_cs_b; +assign usrpio_io[13] = dac_cs_b; +assign CPLD_PS_SPI_CLK_25 = ps_sck; +assign CPLD_PS_SPI_SDI_25 = ps_mosi; + +assign CPLD_PL_SPI_LE_18 = txlo_cs_b; +assign CPLD_PL_SPI_ADDR1_18 = rxlo_cs_b; +assign CPLD_PL_SPI_ADDR2_18 = lodis_cs_b; +assign CPLD_PL_SPI_ADDR0_18 = cpld_pl_cs_b; +assign CPLD_PL_SPI_SCLK_18 = pl_sck; +assign CPLD_PL_SPI_SDI_18 = pl_mosi; + +assign CLKDIST_Status_LD1 = 1'b0; +assign LOSYNTH_RX_MUXOUT = 1'b1; +assign LOSYNTH_TX_MUXOUT = 1'b1; + +initial +begin + $dumpfile("rh_cpld.vcd"); + $dumpvars; + // Check Signature register read-back + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b1}, 16'h0000); + // Check Signature register is read-only + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b0}, 16'h1234); + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b1}, 16'h0000); + + // Load portions of lower RX gain table with some values + #(dly) ps_cpld_xfer(2'b00, {5'b00110, 1'b0}, 16'h0000); /* Write GAIN_BAND_SEL for lower table */ + #(dly) ps_cpld_xfer(2'b01, 6'd0, {2'd0, 5'd0, 5'd1, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd1, {2'd0, 5'd0, 5'd2, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd2, {2'd0, 5'd1, 5'd2, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd3, {2'd0, 5'd1, 5'd3, 1'b1, 3'd0}); + + // Load portions of upper RX gain table with some values + #(dly) ps_cpld_xfer(2'b00, {5'b00110, 1'b0}, 16'h0101); /* Write GAIN_BAND_SEL for upper table */ + #(dly) ps_cpld_xfer(2'b01, 6'd4, {2'd0, 5'd2, 5'd3, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd5, {2'd0, 5'd2, 5'd4, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd6, {2'd0, 5'd3, 5'd4, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd7, {2'd0, 5'd3, 5'd5, 1'b1, 3'd0}); + + // Check RX gain table readback + #(dly) ps_cpld_xfer(2'b01, 6'd0, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd1, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd2, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd3, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd4, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd5, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd6, 16'h0); + + // Check can write a couple registers on PL side + // (Also make sure we're looking at the lower gain tables) + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h0000); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0000); + + // Check retrieval of gain values for RX table and program DSAs + #(dly) pl_cpld_xfer(2'b01, 6'd2, {2'b0, 1'b1, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b01, 6'd3, {2'b0, 1'b0, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b01, 6'd1, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + + // Check writes to RXBS and TXBS registers + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h1ABC); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h1CAB); + + // Check TX DSA programming is independent of RX DSA programming + #(dly) pl_cpld_xfer(2'b10, 6'd4, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + + // Check LO gain programming works + #(dly) pl_cpld_xfer(2'b11, 6'd5, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + #(dly) pl_cpld_xfer(2'b11, 6'd7, {2'b0, 1'b0, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b11, 6'd0, {2'b0, 1'b0, 6'b0, 1'b0, 6'b0}); + + // More checks for PL register writes + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h0ABC); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0CAB); + #(dly) pl_cpld_xfer(2'b00, {5'd8, 1'b0}, 16'hAA5C); + #(dly) pl_cpld_xfer(2'b00, {5'd8, 1'b0}, 16'h5A5C); + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h1C42); + + // Check low/high gain tables and independence of RX vs. TX + #(dly) pl_cpld_xfer(2'b01, 6'd0, 16'h2040); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h104C); + #(dly) pl_cpld_xfer(2'b10, 6'd0, 16'h2040); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0C80); + #(dly) pl_cpld_xfer(2'b10, 6'd5, 16'h2040); + $finish; +end + +rhodium_top toplevel_inst(usrpio_io, // bank 1A, 1B and 6 +ADC_A_Over_Range_18, ADC_B_Over_Range_18, // bank 1A + +// bank 6 +CPLD_PS_SPI_LE_25, +CPLD_PS_SPI_CLK_25, +CPLD_PS_ADDR0_25, +CPLD_PS_ADDR1_25, +CPLD_PS_SPI_SDI_25, +CPLD_PS_SPI_SDO_25, +PHDAC_SPI_CS_L, PHDAC_SPI_SCLK, PHDAC_SPI_SDI, +LO_SYNC, + +// bank 2 +CPLD_PL_SPI_SDO_18, +CPLD_PL_SPI_LE_18, +CPLD_PL_SPI_SCLK_18, +CPLD_PL_SPI_SDI_18, +CPLD_PL_SPI_ADDR0_18, +CPLD_PL_SPI_ADDR1_18, +CPLD_PL_SPI_ADDR2_18, +CPLD_ATR_TX_18, +CPLD_ATR_RX_18, +ADC_SPI_CS_L_18, +ADC_SPI_SCLK_18, +ADC_SPI_SDIO_18, +DAC_SPI_CS_L_18, +DAC_SPI_SCLK_18, +DAC_SPI_SDIO_18, +DAC_Alarm_18, + +// bank 3 + +CLKDIST_SPI_CS_L, +CLKDIST_SPI_SCLK, +CLKDIST_SPI_SDIO, +Tx_DSA_C1, +Tx_DSA_C2, +Tx_DSA_C4, +Tx_DSA_C8, +Tx_DSA_C16, +Tx_DSA1_LE, +Tx_DSA2_LE, +Tx_Sw1_Ctrl_1, +Tx_Sw1_Ctrl_2, +Tx_Sw2_Ctrl_1, +Tx_Sw2_Ctrl_2, +Tx_Sw3_Ctrl_1, +Tx_Sw3_Ctrl_2, +Tx_Sw3_Ctrl_3, +Tx_Sw3_Ctrl_4, +Rx_LO_Input_Select, +Rx_LO_Filter_Sw_1, +Rx_LO_Filter_Sw_2, +Tx_LO_Input_Select, +Tx_LO_Filter_Sw_1, +Tx_LO_Filter_Sw_2, +CLKDIST_Status_LD1, +CLKDIST_Status_LD2, +LOSYNTH_RX_MUXOUT, +LOSYNTH_TX_MUXOUT, + +// bank 8 +LO_SPI_SCLK, // fans out to both rx & tx synths +LO_SPI_SDI, +LO_TX_CS_L, +LO_RX_CS_L, +Rx_Sw1_Ctrl_1, +Rx_Sw1_Ctrl_2, +Rx_DSA_C1, +Rx_DSA_C2, +Rx_DSA_C4, +Rx_DSA_C8, +Rx_DSA_C16, +Rx_DSA1_LE, +Rx_DSA2_LE, +Rx_Sw2_Ctrl, +Rx_Sw3_Ctrl_1, +Rx_Sw3_Ctrl_2, +Rx_Sw4_Ctrl_1, +Rx_Sw4_Ctrl_2, +Rx_Sw4_Ctrl_3, +Rx_Sw4_Ctrl_4, +Rx_Demod_ADJ_1, +Rx_Demod_ADJ_2, + +// bank 5 +LO_DSA_C1, +LO_DSA_C2, +LO_DSA_C4, +LO_DSA_C8, +LO_DSA_C16, +RxLO_DSA_LE, +TxLO_DSA_LE, +LODIST_Bd_SPI_CS_L, +LODIST_Bd_SPI_SDI, +LODIST_Bd_SPI_SCLK, +LODIST_Bd_IO1, +Tx_Sw5_Ctrl_1, +Tx_Sw5_Ctrl_2, +Rx_Sw6_Ctrl_1, +Rx_Sw6_Ctrl_2, + +Tx_HB_LB_Select, +Rx_HB_LB_Select, +Cal_iso_Sw_Ctrl + + +); +endmodule // rh_tb diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v new file mode 100644 index 000000000..b13eca846 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v @@ -0,0 +1,203 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_gain_ctrl +// Description: +// Gain controller for Rhodium +// Provides 2 SPI slaves: +// The "load" slave is used to load the gain table with DSA settings for +// each index. +// The "ctrl" slave takes in a gain index and drives the DSAs with the +// setting found in the gain table. +// The SPI formats are provided below. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +/** +* SPI DATA FORMAT +* LOADER +* M {table_sel[1:0], gain_index[5:0], rsvd[1:0], dsa1[4:0], dsa2[4:0], wr_en, rsvd[2:0]} +* S {-------------------------------, rsvd[1:0], dsa1[4:0], dsa2[4:0], -------rsvd[3:0]} +* CTRL +* M {table_sel[1:0], gain_index[5:0], rsvd[1:0], wr_dsa1, -rsvd[5:0], wr_dsa2, rsvd[5:0]} +* S {-------------------------------, ---------rsvd[2:0], gain1[5:0], ---rsvd, gain2[5:0]} +*/ +module rhodium_gain_ctrl +#( + parameter TABLE_NUM = 2'b01 +) ( + input wire load_table_sel, + input wire load_sck, + input wire load_csb, + input wire load_mosi, + output wire load_miso, + input wire ctrl_table_sel, + input wire ctrl_sck, + input wire ctrl_csb, + input wire ctrl_mosi, + output reg ctrl_miso, + output wire [4:0] dsa, + output reg dsa1_le, + output reg dsa2_le +); + +localparam CNT_GAIN1_DRIVE = 10, + CNT_DSA1_LE_RISE = 11, + CNT_DSA1_LE_FALL = 14, + CNT_GAIN1_RELEASE = 17; +localparam CNT_GAIN2_DRIVE = 17, + CNT_DSA2_LE_RISE = 18, + CNT_DSA2_LE_FALL = 21, + CNT_GAIN2_RELEASE = 24; + +/****************** +* Gain table loader +*******************/ +reg [4:0] load_bit_cnt; +reg [1:0] load_tbl; +reg [5:0] load_index; +reg [15:0] load_rd_data; +reg [4:0] load_dsa1; +reg [4:0] load_dsa2; +wire [4:0] load_dsa1_prev; +wire [4:0] load_dsa2_prev; + +assign load_miso = load_rd_data[15]; // Shift out on neg edge + +wire wr_en; +assign wr_en = (!load_csb) && (load_tbl == TABLE_NUM) && (load_bit_cnt == 20) && (load_mosi); + +// Cycle counter for where we are in protocol and shift register for input +always @ (posedge load_sck or posedge load_csb) +begin + if (load_csb) begin + load_bit_cnt <= 5'd0; + end else if (!load_csb) begin + {load_dsa1, load_dsa2} <= {load_dsa1[3:0], load_dsa2, load_mosi}; + + if (load_bit_cnt < 23) begin + load_bit_cnt <= load_bit_cnt + 5'd1; + end + if (load_bit_cnt < 8) begin + {load_tbl, load_index} <= {load_tbl[0], load_index, load_mosi}; + end + end +end + +// Readback shift register +always @ (negedge load_sck) +begin + if (load_bit_cnt == 9) begin + load_rd_data <= {load_dsa1_prev, load_dsa2_prev, 5'b000}; + end else begin + load_rd_data <= {load_rd_data[14:0], 1'b0}; + end +end + +/****************** +* Gain table RAM +*******************/ +wire [4:0] ctrl_dsa1; +wire [4:0] ctrl_dsa2; + +/* Use half of table for low band, other half for high band + * Software decides address mapping + */ +rhodium_gain_table gain_table( + .wr_clk(load_sck), + .wr_en(wr_en), + .wr_addr({load_table_sel, load_index}), + .wr_data({load_dsa1, load_dsa2}), + .wr_data_prev({load_dsa1_prev, load_dsa2_prev}), + .rd_clk(ctrl_sck), + .rd_addr({ctrl_table_sel, ctrl_index}), + .rd_data({ctrl_dsa1, ctrl_dsa2}) +); + +/****************** +* Gain control +*******************/ +reg [4:0] ctrl_bit_cnt; +reg [1:0] ctrl_tbl; +reg [5:0] ctrl_index; + +reg [5:0] gain1; +reg [5:0] gain2; +reg gain1_t; +reg gain2_t; + +assign dsa = !gain1_t ? ctrl_dsa1 : + (!gain2_t ? ctrl_dsa2 : + 5'b11111); + +// Cycle counter for where we are in protocol and shift register for input +// Also controls timing of DSAs' latch enable signals +always @ (posedge ctrl_sck or posedge ctrl_csb) +begin + if (ctrl_csb) begin + ctrl_bit_cnt <= 5'd0; + dsa1_le <= 1'b0; + dsa2_le <= 1'b0; + gain1_t <= 1'b1; + gain2_t <= 1'b1; + end else if (!ctrl_csb) begin + if (ctrl_bit_cnt < 23) begin + ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1; + end + + if (ctrl_bit_cnt < 8) begin + {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi}; + end + + if (ctrl_tbl == TABLE_NUM) begin + if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin + gain1 <= ctrl_index; + gain1_t <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin + dsa1_le <= 1'b1; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin + dsa1_le <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin + gain1_t <= 1'b1; + end + + if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin + gain2 <= ctrl_index; + gain2_t <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin + dsa2_le <= 1'b1; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin + dsa2_le <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin + gain2_t <= 1'b1; + end + end + end +end + +// SPI readback for ctrl bus, based on current bit count +always @ (negedge ctrl_sck) +begin + case (ctrl_bit_cnt) // Shift out on neg edge + 11: ctrl_miso <= gain1[5]; + 12: ctrl_miso <= gain1[4]; + 13: ctrl_miso <= gain1[3]; + 14: ctrl_miso <= gain1[2]; + 15: ctrl_miso <= gain1[1]; + 16: ctrl_miso <= gain1[0]; + 18: ctrl_miso <= gain2[5]; + 19: ctrl_miso <= gain2[4]; + 20: ctrl_miso <= gain2[3]; + 21: ctrl_miso <= gain2[2]; + 22: ctrl_miso <= gain2[1]; + 23: ctrl_miso <= gain2[0]; + default: ctrl_miso <= 1'b0; + endcase +end + +endmodule // rhodium_gain_ctrl +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v new file mode 100644 index 000000000..abaca43ba --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v @@ -0,0 +1,54 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_gain_table +// Description: +// Simple dual port memory for use as gain table +// Implements a 128 x 16 bit dual-port RAM for storing 10-bit gain values. +// Write and read domains are independent. Data takes 1 cycle to become valid +// on the output of the RAM once written. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +module rhodium_gain_table +( + input wire wr_clk, + input wire wr_en, + input wire [6:0] wr_addr, + input wire [9:0] wr_data, + + // Read data for wr_addr (read-first/read-before-write): One cycle latency + output wire [9:0] wr_data_prev, + + input wire rd_clk, + input wire [6:0] rd_addr, + output wire [9:0] rd_data // Read data for rd_addr: One cycle latency +); + +reg [15:0] gain_table[127:0]; +reg [15:0] wr_data_prev_r; +reg [15:0] rd_data_r; + +assign wr_data_prev = wr_data_prev_r[15:6]; +assign rd_data = rd_data_r[15:6]; + +always @ (posedge wr_clk) +begin + if (wr_en) + gain_table[wr_addr] <= {wr_data, 6'b0}; + wr_data_prev_r <= gain_table[wr_addr]; +end + +always @ (posedge rd_clk) +begin + rd_data_r <= gain_table[rd_addr]; +end + + +endmodule // rhodium_gain_table +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v new file mode 100644 index 000000000..0c4ed4c52 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v @@ -0,0 +1,124 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_lo_gain +// Description: +// LO Gain controller for Rhodium +// Implements a gain index register (not a table) +// +// Provides 1 SPI slave: +// The "ctrl" slave takes in a gain index and drives the DSA with that +// value. +// The SPI formats are provided below. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +/** +* SPI DATA FORMAT (left-most bit is first) +* CTRL +* M {table_sel[1:0], rsvd, gain[4:0], rsvd[1:0], wr_dsa1, ------rsvd[5:0], wr_dsa2, ----rsvd[5:0] +* S {-------------------------------, --------------rsvd[3:0], gain1[4:0], -rsvd[1:0], gain2[4:0]} +*/ +module rhodium_lo_gain #( + parameter TABLE_NUM = 2'b01 +) ( + input wire ctrl_sck, + input wire ctrl_csb, + input wire ctrl_mosi, + output reg ctrl_miso, + output wire [4:0] dsa, + output reg dsa1_le, + output reg dsa2_le +); + +localparam CNT_GAIN1_DRIVE = 10, + CNT_DSA1_LE_RISE = 11, + CNT_DSA1_LE_FALL = 14, + CNT_GAIN1_RELEASE = 17; +localparam CNT_GAIN2_DRIVE = 17, + CNT_DSA2_LE_RISE = 18, + CNT_DSA2_LE_FALL = 21, + CNT_GAIN2_RELEASE = 24; + +reg [4:0] ctrl_bit_cnt; +reg [1:0] ctrl_tbl; +reg [5:0] ctrl_index; +reg [5:0] gain1, gain2; +reg gain1_t; +reg gain2_t; + +assign dsa = (!gain1_t | !gain2_t) ? ctrl_index[4:0] : 5'b11111; + +// Cycle counter for where we are in protocol and shift register for input +// Also controls timing of DSAs' latch enable signals +always @ (posedge ctrl_sck or posedge ctrl_csb) +begin + if (ctrl_csb) begin + ctrl_bit_cnt <= 5'd0; + dsa1_le <= 1'b0; + dsa2_le <= 1'b0; + gain1_t <= 1'b1; + gain2_t <= 1'b1; + end else if (!ctrl_csb) begin + if (ctrl_bit_cnt < 23) begin + ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1; + end + + if (ctrl_bit_cnt < 8) begin + {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi}; + end + + if (ctrl_tbl == TABLE_NUM) begin + if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin + gain1 <= ctrl_index; + gain1_t <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin + dsa1_le <= 1'b1; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin + dsa1_le <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin + gain1_t <= 1'b1; + end + + if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin + gain2 <= ctrl_index; + gain2_t <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin + dsa2_le <= 1'b1; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin + dsa2_le <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin + gain2_t <= 1'b1; + end + end + end +end + +// SPI readback for ctrl bus, based on current bit count +always @ (negedge ctrl_sck) +begin + case (ctrl_bit_cnt) // Shift out on neg edge + 11: ctrl_miso <= gain1[5]; + 12: ctrl_miso <= gain1[4]; + 13: ctrl_miso <= gain1[3]; + 14: ctrl_miso <= gain1[2]; + 15: ctrl_miso <= gain1[1]; + 16: ctrl_miso <= gain1[0]; + 18: ctrl_miso <= gain2[5]; + 19: ctrl_miso <= gain2[4]; + 20: ctrl_miso <= gain2[3]; + 21: ctrl_miso <= gain2[2]; + 22: ctrl_miso <= gain2[1]; + 23: ctrl_miso <= gain2[0]; + default: ctrl_miso <= 1'b0; + endcase +end + + +endmodule // rhodium_lo_gain +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf new file mode 100644 index 000000000..5e1bf4d57 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition +# Date created = 08:22:34 September 13, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "08:22:34 September 13, 2017" + +# Revisions + +PROJECT_REVISION = "rhodium_top" diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf new file mode 100644 index 000000000..e94f0bbc8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf @@ -0,0 +1,306 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition +# Date created = 08:22:34 September 13, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# rhodium_top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M04SAU169I7G +set_global_assignment -name TOP_LEVEL_ENTITY rhodium_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:22:34 SEPTEMBER 13, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_D11 -to CPLD_PS_SPI_LE_25 +set_location_assignment PIN_F13 -to CPLD_PS_SPI_CLK_25 +set_location_assignment PIN_E10 -to CPLD_PS_ADDR0_25 +set_location_assignment PIN_A12 -to CPLD_PS_ADDR1_25 +set_location_assignment PIN_F12 -to CPLD_PS_SPI_SDI_25 +set_location_assignment PIN_F10 -to CPLD_PS_SPI_SDO_25 +set_location_assignment PIN_B1 -to ADC_A_Over_Range_18 +set_location_assignment PIN_D1 -to ADC_B_Over_Range_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_A_Over_Range_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_B_Over_Range_18 +set_instance_assignment -name IO_STANDARD LVDS -to LO_SYNC +set_location_assignment PIN_G9 -to LO_SYNC +set_location_assignment PIN_G10 -to "LO_SYNC(n)" +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_CS_L_18 +set_location_assignment PIN_C2 -to ADC_SPI_CS_L_18 +set_location_assignment PIN_C1 -to ADC_SPI_SCLK_18 +set_location_assignment PIN_E3 -to ADC_SPI_SDIO_18 +set_location_assignment PIN_M5 -to CLKDIST_SPI_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_CS_L +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SDIO_18 +set_location_assignment PIN_L5 -to CLKDIST_SPI_SCLK +set_location_assignment PIN_N5 -to CLKDIST_SPI_SDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SDIO +set_location_assignment PIN_K6 -to CLKDIST_Status_LD1 +set_location_assignment PIN_J6 -to CLKDIST_Status_LD2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD2 +set_location_assignment PIN_M1 -to CPLD_ATR_TX_18 +set_location_assignment PIN_L1 -to CPLD_ATR_RX_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_RX_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_TX_18 +set_location_assignment PIN_H6 -to CPLD_PL_SPI_ADDR0_18 +set_location_assignment PIN_K2 -to CPLD_PL_SPI_ADDR1_18 +set_location_assignment PIN_J2 -to CPLD_PL_SPI_ADDR2_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR0_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR1_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR2_18 +set_location_assignment PIN_K1 -to CPLD_PL_SPI_LE_18 +set_location_assignment PIN_H5 -to CPLD_PL_SPI_SCLK_18 +set_location_assignment PIN_L3 -to CPLD_PL_SPI_SDI_18 +set_location_assignment PIN_L2 -to CPLD_PL_SPI_SDO_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_LE_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDI_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDO_18 +set_location_assignment PIN_M2 -to DAC_Alarm_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_Alarm_18 +set_location_assignment PIN_N3 -to DAC_SPI_SDIO_18 +set_location_assignment PIN_N2 -to DAC_SPI_SCLK_18 +set_location_assignment PIN_M3 -to DAC_SPI_CS_L_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_CS_L_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SDIO_18 +set_location_assignment PIN_M7 -to LOSYNTH_RX_MUXOUT +set_location_assignment PIN_N7 -to LOSYNTH_TX_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_RX_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_TX_MUXOUT +set_location_assignment PIN_E6 -to LO_RX_CS_L +set_location_assignment PIN_B2 -to LO_SPI_SCLK +set_location_assignment PIN_M4 -to LO_SPI_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_RX_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SDI +set_location_assignment PIN_K5 -to LO_TX_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_TX_CS_L +set_location_assignment PIN_B6 -to Rx_DSA1_LE +set_location_assignment PIN_A9 -to Rx_DSA2_LE +set_location_assignment PIN_D8 -to Rx_DSA_C1 +set_location_assignment PIN_D6 -to Rx_DSA_C2 +set_location_assignment PIN_A11 -to Rx_DSA_C4 +set_location_assignment PIN_B10 -to Rx_DSA_C8 +set_location_assignment PIN_A10 -to Rx_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA1_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA2_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C16 +set_location_assignment PIN_B3 -to Rx_Demod_ADJ_1 +set_location_assignment PIN_N4 -to Rx_Demod_ADJ_2 +set_location_assignment PIN_J5 -to Rx_LO_Filter_Sw_1 +set_location_assignment PIN_J7 -to Rx_LO_Filter_Sw_2 +set_location_assignment PIN_L4 -to Rx_LO_Input_Select +set_location_assignment PIN_A6 -to Rx_Sw1_Ctrl_1 +set_location_assignment PIN_A7 -to Rx_Sw1_Ctrl_2 +set_location_assignment PIN_A5 -to Rx_Sw2_Ctrl +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw2_Ctrl +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Input_Select +set_location_assignment PIN_A4 -to Rx_Sw3_Ctrl_1 +set_location_assignment PIN_A3 -to Rx_Sw3_Ctrl_2 +set_location_assignment PIN_C10 -to Rx_Sw4_Ctrl_1 +set_location_assignment PIN_A8 -to Rx_Sw4_Ctrl_2 +set_location_assignment PIN_B9 -to Rx_Sw4_Ctrl_3 +set_location_assignment PIN_C9 -to Rx_Sw4_Ctrl_4 +set_location_assignment PIN_K13 -to Tx_DSA1_LE +set_location_assignment PIN_K12 -to Tx_DSA2_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA1_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA2_LE +set_location_assignment PIN_H13 -to Tx_DSA_C1 +set_location_assignment PIN_H8 -to Tx_DSA_C2 +set_location_assignment PIN_J13 -to Tx_DSA_C4 +set_location_assignment PIN_H10 -to Tx_DSA_C8 +set_location_assignment PIN_J12 -to Tx_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C16 +set_location_assignment PIN_N6 -to Tx_LO_Filter_Sw_1 +set_location_assignment PIN_N12 -to Tx_LO_Filter_Sw_2 +set_location_assignment PIN_N8 -to Tx_LO_Input_Select +set_location_assignment PIN_L10 -to Tx_Sw1_Ctrl_1 +set_location_assignment PIN_N10 -to Tx_Sw1_Ctrl_2 +set_location_assignment PIN_N11 -to Tx_Sw2_Ctrl_1 +set_location_assignment PIN_L11 -to Tx_Sw2_Ctrl_2 +set_location_assignment PIN_L12 -to Tx_Sw3_Ctrl_1 +set_location_assignment PIN_M13 -to Tx_Sw3_Ctrl_2 +set_location_assignment PIN_K11 -to Tx_Sw3_Ctrl_3 +set_location_assignment PIN_J9 -to Tx_Sw3_Ctrl_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Input_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_4 +set_location_assignment PIN_B11 -to PHDAC_SPI_CS_L +set_location_assignment PIN_C11 -to PHDAC_SPI_SCLK +set_location_assignment PIN_D9 -to PHDAC_SPI_SDI +set_location_assignment PIN_N9 -to LODIST_Bd_SPI_CS_L +set_location_assignment PIN_J8 -to LODIST_Bd_SPI_SCLK +set_location_assignment PIN_M9 -to LODIST_Bd_SPI_SDI +set_location_assignment PIN_L13 -to LO_DSA_C1 +set_location_assignment PIN_K10 -to LO_DSA_C2 +set_location_assignment PIN_H9 -to LO_DSA_C4 +set_location_assignment PIN_G12 -to LO_DSA_C8 +set_location_assignment PIN_G13 -to LO_DSA_C16 +set_location_assignment PIN_J10 -to RxLO_DSA_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RxLO_DSA_LE +set_location_assignment PIN_B4 -to Rx_Sw6_Ctrl_1 +set_location_assignment PIN_B5 -to Rx_Sw6_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_2 +set_location_assignment PIN_M8 -to TxLO_DSA_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TxLO_DSA_LE +set_location_assignment PIN_M11 -to Tx_Sw5_Ctrl_1 +set_location_assignment PIN_M12 -to Tx_Sw5_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_2 +set_location_assignment PIN_D12 -to Cal_iso_Sw_Ctrl +set_location_assignment PIN_K8 -to LODIST_Bd_IO1 +set_location_assignment PIN_M10 -to Tx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_HB_LB_Select +set_location_assignment PIN_E8 -to Rx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_CS_L +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SCLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SDI +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR0_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR1_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_CLK_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_LE_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDI_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDO_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to Cal_iso_Sw_Ctrl +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to LODIST_Bd_IO1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_location_assignment PIN_E4 -to usrp_io[0] +set_location_assignment PIN_G5 -to usrp_io[1] +set_location_assignment PIN_H4 -to usrp_io[2] +set_location_assignment PIN_J1 -to usrp_io[3] +set_location_assignment PIN_F1 -to usrp_io[4] +set_location_assignment PIN_C12 -to usrp_io[5] +set_location_assignment PIN_C13 -to usrp_io[6] +set_location_assignment PIN_E12 -to usrp_io[7] +set_location_assignment PIN_E13 -to usrp_io[8] +set_location_assignment PIN_B13 -to usrp_io[9] +set_location_assignment PIN_F9 -to usrp_io[10] +set_location_assignment PIN_B12 -to usrp_io[11] +set_location_assignment PIN_E9 -to usrp_io[12] +set_location_assignment PIN_F8 -to usrp_io[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[13] +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH rh_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME rh_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id rh_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "9000 ns" -section_id rh_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME rh_tb -section_id rh_tb +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name VERILOG_FILE rhodium_top.v +set_global_assignment -name VERILOG_FILE rhodium_gain_ctrl.v +set_global_assignment -name VERILOG_FILE rhodium_gain_table.v +set_global_assignment -name VERILOG_FILE rhodium_lo_gain.v +set_global_assignment -name VERILOG_FILE rh_tb.v +set_global_assignment -name EDA_TEST_BENCH_FILE rh_tb.v -section_id rh_tb + + +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name GENERATE_SVF_FILE ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc new file mode 100644 index 000000000..4b00a5053 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc @@ -0,0 +1,415 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Copyright 2019 Ettus Research, A National Instruments Company +# +# Timing constraints for Rhodium's MAX 10 board controller + +set_time_format -unit ns -decimal_places 3 + +# Some constants for constraining the design with the FPGA-centric method: +# Maximum trace propagation delay is assumed to be 0.6 ns on any traces +# to on-dboard slaves +set board_delay 0.600 +set clk_uncertainty 0.150 + +############################################################################### +# Clocks +############################################################################### + +# The PS SPI clock is maximum 10 MHz. It is driven from another source and +# provided with the data. +# CPLD_PS_SPI_CLK_25: 8 MHz +set sclk_ps_period 125.000 + +# Create clock for the PS's SPI interface +create_clock -name sclk_ps -period $sclk_ps_period \ + [get_ports CPLD_PS_SPI_CLK_25] + +# The PL SPI clock is split into two pieces. For the normal case, the clock +# frequency is 10 MHz. This is for any read operations. +# +# CPLD_PL_SPI_SCLK_18 pass through / read back ONLY: 10 MHz +set sclk_pl_period 100.000 +create_clock -name sclk_pl -period $sclk_pl_period \ + [get_ports CPLD_PL_SPI_SCLK_18] + +# We can go faster for the PL writes to the internal registers and LOs. +# This rate is not supported for readback, but it helps with getting the DSA +# settings and LO settings in faster. +# CPLD_PL_SPI_SCLK_18 internal ONLY: 25 MHz +set sclk_pl_wr_period 40.000 +create_clock -name sclk_pl_wr -period $sclk_pl_wr_period \ + [get_ports CPLD_PL_SPI_SCLK_18] -add + +# Output clocks for the MAX 10's SPI master interfaces (1 for each slave IC) +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name clkdist_clk [get_ports CLKDIST_SPI_SCLK] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name adc_clk [get_ports ADC_SPI_SCLK_18] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name dac_clk [get_ports DAC_SPI_SCLK_18] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name phdac_clk [get_ports PHDAC_SPI_SCLK] + +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl] \ + -name lo_clk [get_ports LO_SPI_SCLK] +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl_wr] \ + -name lo_wr_clk [get_ports LO_SPI_SCLK] -add +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl] \ + -name lodist_clk [get_ports LODIST_Bd_SPI_SCLK] + +# Virtual clock for DSA writes for skew calculations +#create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|clk] +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl_wr] \ + -name dsa_reg_clk [get_pins lo_gain_table\|dsa1_le\|q] + +create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|q] \ + -name dsa_clk [get_ports RxLO_DSA_LE] + +# PL's pass through clock doesn't interact with internal clock +set_clock_groups -physically_exclusive \ + -group [get_clocks {sclk_pl_wr lo_wr_clk dsa_reg_clk dsa_clk}] \ + -group [get_clocks {sclk_pl lo_clk lodist_clk}] + +set_clock_groups -asynchronous \ + -group [get_clocks {sclk_ps clkdist_clk adc_clk dac_clk phdac_clk}] \ + -group [get_clocks {sclk_pl sclk_pl_wr lo_clk lodist_clk}] + +set_clock_uncertainty -to [get_clocks {sclk_ps sclk_pl sclk_pl_wr clkdist_clk + adc_clk dac_clk phdac_clk lo_clk lo_wr_clk lodist_clk dsa_reg_clk dsa_clk}] \ + $clk_uncertainty + +############################################################################### +# Timing Budget Calculations +############################################################################### +# Here we carve out some timing budget for the master's SPI interfaces. +# The master will use these values to time its SPI interface. +# The PL's write-only values are smaller because there are no external chip +# dependencies. +set setup_ps 25 +set hold_ps 30 + +# PL SPI is constrained on the master with an allowed skew value of +/- 3 ns +# relative to the launch clock +# Increase to 5 ns here for more margin +set pl_skew 5 + +# Clocks are nominally a 50% duty cycle, so difference between latch and +# launch is half a period, so subtract allowed skew from that for setup/hold +# specification. The half period is due to launch being the falling edge and +# latch being the rising edge. +set setup_pl [expr {$sclk_pl_period / 2 - $pl_skew}] +set hold_pl [expr {$sclk_pl_period / 2 - $pl_skew}] +set setup_pl_wr [expr {$sclk_pl_wr_period / 2 - $pl_skew}] +set hold_pl_wr [expr {$sclk_pl_wr_period / 2 - $pl_skew}] + +# Calculate input delays relative to falling edge (launch) +# Min is hold time after previous rising edge (previous latch) +# Max is setup time before next rising edge (next latch) +set input_delay_min_ps [expr {-$sclk_ps_period / 2 + $hold_ps}] +set input_delay_max_ps [expr {$sclk_ps_period / 2 - $setup_ps}] +set input_delay_min_pl [expr {-$sclk_pl_period / 2 + $hold_pl}] +set input_delay_max_pl [expr {$sclk_pl_period / 2 - $setup_pl}] +set input_delay_min_pl_wr [expr {-$sclk_pl_wr_period / 2 + $hold_pl_wr}] +set input_delay_max_pl_wr [expr {$sclk_pl_wr_period / 2 - $setup_pl_wr}] + +# Again, carve out timing budget for master's SPI interface +# Readback on the master will depend on clk-to-q of our slave. +# These values will need to be at least as large as the worst slave. +# Clock arrival at the slave will be delayed by propagation through the MAX 10 +# Data to the MAX 10's input port will be further delayed by slave's clk-to-q +# On top of that, we then need budget for the data to cross the MAX 10, head +# out the I/O, and propagate to the master's pin. Then the master will need +# some budget for setup time. +# +# Here is what we'll budget: +# Clk propagation to I/O: 7 ns +# Clk trace delay: 1 ns +# Worst-case chip clk-to-q: 10 ns +# Data trace delay: 1 ns +# Data propagation delay from input pin to output pin: 8 ns +# Total clk-to-q from MAX 10 sclk input to MAX 10 output: 27 ns +# +# Then master's budget is 23 ns for clock delay + data delay + setup time +set clk_q_max_ps 27.000 + +# For the PL, the worst-case chip changes to 2 ns, so there is more budget +set clk_q_max_pl 20.000 + +# clk-to-q determines one side of the data invalid window +# The maximum output delay is simply latch edge - clk-to-q +# Launch is falling edge, and latch is rising edge, so... +set output_delay_max_ps [expr {$sclk_ps_period / 2 - $clk_q_max_ps}] +set output_delay_max_pl [expr {$sclk_pl_period / 2 - $clk_q_max_pl}] + +# The minimum output delay represents the other edge of the data invalid +# window. Our clock is likely quite delayed already, but add a little more +# margin for hold time. +set output_delay_min_ps -5.000 +set output_delay_min_pl -5.000 + + +############################################################################### +# I/O groups (for reference later) +############################################################################### + +# Chip selects +set ps_csb [get_ports { + CPLD_PS_ADDR0_25 + CPLD_PS_ADDR1_25 + CPLD_PS_SPI_LE_25 + usrp_io[12] + usrp_io[13] +}] +set pl_csb [get_ports { + CPLD_PL_SPI_ADDR0_18 + CPLD_PL_SPI_ADDR1_18 + CPLD_PL_SPI_ADDR2_18 + CPLD_PL_SPI_LE_18 +}] + +# Data for internal PL SPI +set pl_src [get_ports { + CPLD_PL_SPI_SDI_18 +}] + +# Passthrough inputs (forward direction) +# CPLD_PS_SPI_CLK_25 and CPLD_PL_SPI_SCLK_18 are special +set ps_pt_src [get_ports {CPLD_PS_SPI_LE_25 + usrp_io[12] + usrp_io[13] + CPLD_PS_ADDR1_25 + CPLD_PS_SPI_SDI_25 + }] + +set pl_pt_src [get_ports {CPLD_PL_SPI_LE_18 + CPLD_PL_SPI_ADDR1_18 + CPLD_PL_SPI_ADDR2_18 + CPLD_PL_SPI_SDI_18 + }] + +# Passthrough outputs (forward direction) +# And inputs from the SPI slaves (readback direction) +set clkdist_spi_out [get_ports { + CLKDIST_SPI_CS_L + CLKDIST_SPI_SDIO +}] + +set clkdist_spi_in [get_ports { + CLKDIST_SPI_SDIO +}] + +set phdac_spi [get_ports { + PHDAC_SPI_CS_L + PHDAC_SPI_SDI +}] + +set dac_spi_out [get_ports { + DAC_SPI_CS_L_18 + DAC_SPI_SDIO_18 +}] + +set dac_spi_in [get_ports { + DAC_SPI_SDIO_18 +}] + +set adc_spi_out [get_ports { + ADC_SPI_CS_L_18 + ADC_SPI_SDIO_18 +}] + +set adc_spi_in [get_ports { + ADC_SPI_SDIO_18 +}] + +set lo_spi_out [get_ports { + LO_TX_CS_L + LO_RX_CS_L + LO_SPI_SDI +}] + +set lo_spi_in [get_ports { + LOSYNTH_RX_MUXOUT + LOSYNTH_TX_MUXOUT +}] + +set lodist_spi_out [get_ports { + LODIST_Bd_SPI_CS_L + LODIST_Bd_SPI_SDI +}] + +# Readback outputs +set ps_rb_out [get_ports CPLD_PS_SPI_SDO_25] +set pl_rb_out [get_ports CPLD_PL_SPI_SDO_18] + +############################################################################## +# Chip-selects provide async resets +############################################################################## +set_false_path -from $ps_csb -to [get_pins *|clrn] +set_false_path -from $pl_csb -to [get_pins *|clrn] + +# Also ignore setup/hold analysis for chip-selects affecting readback path +# These are available many cycles before readback begins and have +# combinatorial paths to the output +set_false_path -from $ps_csb -to $ps_rb_out +set_false_path -from $pl_csb -to $pl_rb_out + +set_input_delay -clock sclk_ps -clock_fall -max $input_delay_max_ps \ + [get_ports CPLD_PS_ADDR0_25] +set_input_delay -clock sclk_ps -clock_fall -min $input_delay_min_ps \ + [get_ports CPLD_PS_ADDR0_25] + +set_input_delay -clock sclk_pl -clock_fall -max $input_delay_max_pl \ + [get_ports CPLD_PL_SPI_ADDR0_18] +set_input_delay -clock sclk_pl -clock_fall -min $input_delay_min_pl \ + [get_ports CPLD_PL_SPI_ADDR0_18] + +set_input_delay -clock sclk_pl_wr -clock_fall -max $input_delay_max_pl_wr \ + [get_ports CPLD_PL_SPI_ADDR0_18] -add +set_input_delay -clock sclk_pl_wr -clock_fall -min $input_delay_min_pl_wr \ + [get_ports CPLD_PL_SPI_ADDR0_18] -add + + +############################################################################## +# Input delays from SPI master +############################################################################## +set_input_delay -clock sclk_ps -clock_fall -max $input_delay_max_ps $ps_pt_src +set_input_delay -clock sclk_ps -clock_fall -min $input_delay_min_ps $ps_pt_src + +set_input_delay -clock sclk_pl -clock_fall -max $input_delay_max_pl $pl_pt_src +set_input_delay -clock sclk_pl -clock_fall -min $input_delay_min_pl $pl_pt_src + +set_input_delay -clock sclk_pl_wr -clock_fall -max $input_delay_max_pl_wr $pl_src -add +set_input_delay -clock sclk_pl_wr -clock_fall -min $input_delay_min_pl_wr $pl_src -add + +############################################################################## +# Output delays to each SPI slave (uses setup/hold times from data sheet) +############################################################################## +set adc_setup 4 +set adc_hold 2 +set_output_delay -clock adc_clk -max [expr {$adc_setup + $board_delay}] \ + $adc_spi_out +set_output_delay -clock adc_clk -min [expr {-$adc_hold - $board_delay}] \ + $adc_spi_out + +set dac_setup 10 +set dac_hold 5 +set_output_delay -clock dac_clk -max [expr {$dac_setup + $board_delay}] \ + $dac_spi_out +set_output_delay -clock dac_clk -min [expr {-$dac_hold - $board_delay}] \ + $dac_spi_out + +set phdac_setup 5 +set phdac_hold 5 +set_output_delay -clock phdac_clk -max [expr {$phdac_setup + $board_delay}] \ + $phdac_spi +set_output_delay -clock phdac_clk -min [expr {-$phdac_hold - $board_delay}] \ + $phdac_spi + +set clkdist_setup 10 +set clkdist_hold 10 +set_output_delay -clock clkdist_clk -max [expr {$clkdist_setup + $board_delay}] \ + $clkdist_spi_out +set_output_delay -clock clkdist_clk -min [expr {-$clkdist_hold - $board_delay}] \ + $clkdist_spi_out + +set lo_setup 2 +set lo_hold 2 +set_output_delay -clock lo_wr_clk -max [expr {$lo_setup + $board_delay}] \ + $lo_spi_out +set_output_delay -clock lo_wr_clk -min [expr {-$lo_hold - $board_delay}] \ + $lo_spi_out + +############################################################################## +# Input delays from each SPI slave (uses clk-to-q times from data sheet) +# One board delay for clock, another for data +############################################################################## +set lo_clk_q 2 +set_input_delay -clock lo_clk -clock_fall -max [expr {$lo_clk_q + $board_delay + $board_delay}] \ + $lo_spi_in +set_input_delay -clock lo_clk -clock_fall -min 0 \ + $lo_spi_in + +set adc_clk_q 10 +set dac_clk_q 10 +set clkdist_clk_q 10 +set_input_delay -clock adc_clk -clock_fall -max [expr {$adc_clk_q + $board_delay + $board_delay}] \ + $adc_spi_in +set_input_delay -clock adc_clk -clock_fall -min 0 \ + $adc_spi_in +set_input_delay -clock dac_clk -clock_fall -max [expr {$dac_clk_q + $board_delay + $board_delay}] \ + $dac_spi_in +set_input_delay -clock dac_clk -clock_fall -min 0 \ + $dac_spi_in +set_input_delay -clock clkdist_clk -clock_fall -max [expr {$clkdist_clk_q + $board_delay + $board_delay}] \ + $clkdist_spi_in +set_input_delay -clock clkdist_clk -clock_fall -min 0 \ + $clkdist_spi_in + + +############################################################################## +# Output delays for readback path +############################################################################## +set_output_delay -clock sclk_ps -max $output_delay_max_ps $ps_rb_out +set_output_delay -clock sclk_ps -min $output_delay_min_ps $ps_rb_out + +set_output_delay -clock sclk_pl -max $output_delay_max_pl $pl_rb_out +set_output_delay -clock sclk_pl -min $output_delay_min_pl $pl_rb_out + +############################################################################## +# GPIOs and DSAs +# Outputs that aren't timing-critical +############################################################################## +set gpos [get_ports {Tx_Sw* + Rx_LO_* + Tx_LO_* + Rx_Sw* + Rx_Demod_* + Tx_HB_LB_Select + Rx_HB_LB_Select + Cal_iso_Sw_Ctrl + LODIST_Bd_IO1 + }] + +# Inputs that aren't timing-critical +set gpis [get_ports {LO_SYNC + CPLD_ATR_TX_18 + CPLD_ATR_RX_18 + DAC_Alarm_18 + CLKDIST_Status* + LODIST_Bd_IO1 + }] + +# DSAs (special skew needs) +# RxLO_DSA_LE used for skew basis +set dsas [get_ports {Tx_DSA* + Rx_DSA* + TxLO_DSA* + LO_DSA* + }] + +# Just do false paths for gpios +set_false_path -to $gpos +set_false_path -from $gpis + +# Unused +set_false_path -to $lodist_spi_out + +# DSA skew timing +# Earlier, we created a "clock" for one of the DSA latch enable signals +# Use set_output_delay to constrain skew around the latch enable +# set_multicycle_path is used to make latch clock = launch clock for setup +# Constrain skew to 8 ns -- controller nominally does 120 ns minimum between +# edges, and 100 ns is the DSA's requirement for setup/hold +set dsa_skew 8.0 +set_output_delay -clock dsa_clk -max -$dsa_skew $dsas +set_output_delay -clock dsa_clk -min $dsa_skew $dsas +set_multicycle_path -start -setup 0 -to $dsas + +set_max_delay -from [get_ports CPLD_ATR_TX_18] \ + -to [get_ports {Tx_Sw1_Ctrl_1 Tx_Sw1_Ctrl_2}] 10.0 + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v new file mode 100644 index 000000000..1d0d640da --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v @@ -0,0 +1,605 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_top +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +module rhodium_top( + +input [13:0] usrp_io, // bank 1A, 1B and 6 + +input ADC_A_Over_Range_18, input ADC_B_Over_Range_18, // bank 1A + +// bank 6 +input CPLD_PS_SPI_LE_25, +input CPLD_PS_SPI_CLK_25, +input CPLD_PS_ADDR0_25, +input CPLD_PS_ADDR1_25, +input CPLD_PS_SPI_SDI_25, +output reg CPLD_PS_SPI_SDO_25, +output PHDAC_SPI_CS_L, +output PHDAC_SPI_SCLK, +output PHDAC_SPI_SDI, +input LO_SYNC, + +// bank 2 +output reg CPLD_PL_SPI_SDO_18, +input CPLD_PL_SPI_LE_18, +input CPLD_PL_SPI_SCLK_18, +input CPLD_PL_SPI_SDI_18, +input CPLD_PL_SPI_ADDR0_18, +input CPLD_PL_SPI_ADDR1_18, +input CPLD_PL_SPI_ADDR2_18, +// NOTE: TxRx front-end switches are driven direct from the motherboard, so these ATR +// lines have no function at this time. +input CPLD_ATR_TX_18, +input CPLD_ATR_RX_18, +output ADC_SPI_CS_L_18, +output ADC_SPI_SCLK_18, +inout ADC_SPI_SDIO_18, +output DAC_SPI_CS_L_18, +output DAC_SPI_SCLK_18, +inout DAC_SPI_SDIO_18, +input DAC_Alarm_18, // TODO: drive to gpio? + +// bank 3 + +output CLKDIST_SPI_CS_L, +output CLKDIST_SPI_SCLK, +inout CLKDIST_SPI_SDIO, +output Tx_DSA_C1, +output Tx_DSA_C2, +output Tx_DSA_C4, +output Tx_DSA_C8, +output Tx_DSA_C16, +output Tx_DSA1_LE, +output Tx_DSA2_LE, +output Tx_Sw1_Ctrl_1, +output Tx_Sw1_Ctrl_2, +output Tx_Sw2_Ctrl_1, +output Tx_Sw2_Ctrl_2, +output Tx_Sw3_Ctrl_1, +output Tx_Sw3_Ctrl_2, +output Tx_Sw3_Ctrl_3, +output Tx_Sw3_Ctrl_4, +output Rx_LO_Input_Select, +output Rx_LO_Filter_Sw_1, +output Rx_LO_Filter_Sw_2, +output Tx_LO_Input_Select, +output Tx_LO_Filter_Sw_1, +output Tx_LO_Filter_Sw_2, +input CLKDIST_Status_LD1, +input CLKDIST_Status_LD2, +input LOSYNTH_RX_MUXOUT, +input LOSYNTH_TX_MUXOUT, + +// bank 8 +output LO_SPI_SCLK, // fans out to both rx & tx synths +output LO_SPI_SDI, +output LO_TX_CS_L, +output LO_RX_CS_L, +output Rx_Sw1_Ctrl_1, +output Rx_Sw1_Ctrl_2, +output Rx_DSA_C1, +output Rx_DSA_C2, +output Rx_DSA_C4, +output Rx_DSA_C8, +output Rx_DSA_C16, +output Rx_DSA1_LE, +output Rx_DSA2_LE, +output Rx_Sw2_Ctrl, +output Rx_Sw3_Ctrl_1, +output Rx_Sw3_Ctrl_2, +output Rx_Sw4_Ctrl_1, +output Rx_Sw4_Ctrl_2, +output Rx_Sw4_Ctrl_3, +output Rx_Sw4_Ctrl_4, +output Rx_Demod_ADJ_1, +output Rx_Demod_ADJ_2, + +// bank 5 +output LO_DSA_C1, +output LO_DSA_C2, +output LO_DSA_C4, +output LO_DSA_C8, +output LO_DSA_C16, +output RxLO_DSA_LE, +output TxLO_DSA_LE, +output LODIST_Bd_SPI_CS_L, +output LODIST_Bd_SPI_SDI, +output LODIST_Bd_SPI_SCLK, +inout LODIST_Bd_IO1, +output Tx_Sw5_Ctrl_1, +output Tx_Sw5_Ctrl_2, +output Rx_Sw6_Ctrl_1, +output Rx_Sw6_Ctrl_2, + +output Tx_HB_LB_Select, +output Rx_HB_LB_Select, +output Cal_iso_Sw_Ctrl + + +); + +/* PS SPI */ + +localparam GIT_HASH = 36'h`GIT_HASH; +localparam PROD_SIGNATURE = 16'h0045; // Product signature (Rhodium atomic number in BCD) +localparam REVISION_MINOR = 16'h0002; +localparam REVISION_MAJOR = 16'h0004; +localparam CPLD_BUILD_LSB = GIT_HASH[15:0]; // Build code LSB +localparam CPLD_BUILD_MSB = GIT_HASH[31:16]; // Build code MSB +localparam PSADDR_SIGNATURE = 3'd0; +localparam PSADDR_REV_MINOR = 3'd1; // Minor version register +localparam PSADDR_REV_MAJOR = 3'd2; // Major version register +localparam PSADDR_BUILD_LSB = 3'd3; +localparam PSADDR_BUILD_MSB = 3'd4; +localparam PSADDR_SCRATCH = 3'd5; // scratchpad register +localparam PSADDR_GAIN_SEL = 3'd6; // band select for gain table loader +localparam PSADDR_DAC_ALARM = 3'd7; // DAC alarm pin register + +// Sub-device selection for PS SPI +localparam PS_CPLD_REGS = 2'b00; +localparam GAIN_TABLE_RX = 2'b01; +localparam GAIN_TABLE_TX = 2'b10; +localparam GAIN_TABLE_LO = 2'b11; + +// Setting to put TX SW1 in isolation mode +localparam [1:0] TX_SW1_TERM = 2'b11; + +wire clkdis_cs_b = CPLD_PS_SPI_LE_25; +wire cpld_ps_cs_b = CPLD_PS_ADDR0_25; +wire phdac_cs_b = CPLD_PS_ADDR1_25; +wire adc_cs_b = usrp_io[12]; +wire dac_cs_b = usrp_io[13]; + +// CPLD PS SPI format (left-most bit first): +// {table_sel[1:0], rsvd, reg_addr[3:0], rnw, data[15:0]} +wire [1:0] cpld_ps_table_sel; +wire [6:0] cpld_ps_spi_addr; +wire cpld_ps_spi_rnw; +reg [7:0] cpld_ps_spi_cmd; +reg [15:0] cpld_ps_spi_rdata; +reg [14:0] cpld_ps_spi_wdata; +reg cpld_ps_spi_sdo; +reg [4:0] cpld_ps_cnt; + +assign {cpld_ps_spi_addr, cpld_ps_spi_rnw} = cpld_ps_spi_cmd; + +// CPLD registers +reg [15:0] spad; +reg [15:0] gain_load_sel; + +// Double sync. the DAC ALARM pin (async). +reg dac_alarm_ms, dac_alarm = 0; +always @(posedge CPLD_PS_SPI_CLK_25) begin + {dac_alarm, dac_alarm_ms} <= {dac_alarm_ms, DAC_Alarm_18}; +end + +wire rx_gain_load_tbl_sel; +wire rx_gain_load_miso; +wire rx_gain_ctrl_tbl_sel; +wire rx_gain_ctrl_miso; +wire tx_gain_load_tbl_sel; +wire tx_gain_load_miso; +wire tx_gain_ctrl_tbl_sel; +wire tx_gain_ctrl_miso; +wire lo_gain_ctrl_miso; + +assign rx_gain_load_tbl_sel = gain_load_sel[0]; +assign tx_gain_load_tbl_sel = gain_load_sel[8]; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge cpld_ps_cs_b) +begin + if (cpld_ps_cs_b) begin + cpld_ps_cnt <= 5'd0; + end else if (!cpld_ps_cs_b) begin + if (cpld_ps_cnt < 8) begin // Address / command + cpld_ps_spi_cmd <= {cpld_ps_spi_cmd[6:0], CPLD_PS_SPI_SDI_25}; + cpld_ps_cnt <= cpld_ps_cnt + 5'd1; + end else if (cpld_ps_cnt < 23) begin // Shift in write data + cpld_ps_spi_wdata <= {cpld_ps_spi_wdata[13:0], CPLD_PS_SPI_SDI_25}; + cpld_ps_cnt <= cpld_ps_cnt + 5'd1; + end else if (!cpld_ps_spi_rnw && cpld_ps_cnt == 23 && cpld_ps_spi_addr[6:5] == PS_CPLD_REGS) begin // Write + case (cpld_ps_spi_addr[2:0]) + PSADDR_SIGNATURE: ; + PSADDR_REV_MINOR: ; + PSADDR_REV_MAJOR: ; + PSADDR_BUILD_LSB: ; + PSADDR_BUILD_MSB: ; + PSADDR_SCRATCH: spad <= {cpld_ps_spi_wdata, CPLD_PS_SPI_SDI_25}; + PSADDR_GAIN_SEL: gain_load_sel <= {cpld_ps_spi_wdata, CPLD_PS_SPI_SDI_25}; + endcase + end + if (cpld_ps_cnt == 7) begin // Set up read one cycle earlier + case (cpld_ps_spi_cmd[2:0]) + + PSADDR_SIGNATURE: cpld_ps_spi_rdata <= PROD_SIGNATURE; + PSADDR_REV_MINOR: cpld_ps_spi_rdata <= REVISION_MINOR; + PSADDR_REV_MAJOR: cpld_ps_spi_rdata <= REVISION_MAJOR; + PSADDR_BUILD_LSB: cpld_ps_spi_rdata <= CPLD_BUILD_LSB; + PSADDR_BUILD_MSB: cpld_ps_spi_rdata <= CPLD_BUILD_MSB; + PSADDR_SCRATCH: cpld_ps_spi_rdata <= spad; + PSADDR_GAIN_SEL: cpld_ps_spi_rdata <= gain_load_sel; + PSADDR_DAC_ALARM: cpld_ps_spi_rdata <= {15'b0, dac_alarm}; + endcase + end else begin + cpld_ps_spi_rdata <= {cpld_ps_spi_rdata[14:0], 1'b1}; + end + end +end + +always @(negedge CPLD_PS_SPI_CLK_25) +begin + cpld_ps_spi_sdo <= cpld_ps_spi_rdata[15]; // Shift out on negative edge +end + +// CLKDIST 3-wire to 4-wire +reg [4:0] clkdis_cnt; +reg clkdis_rd_pre, clkdis_rd, clkdis_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge clkdis_cs_b) +begin + if (clkdis_cs_b) begin + clkdis_cnt <= 5'd0; + clkdis_rd <= 1'b0; + clkdis_rd_pre <= 1'b0; + end else if (!clkdis_cs_b) begin + if (clkdis_cnt < 23) + clkdis_cnt <= clkdis_cnt + 5'd1; + + if (clkdis_cnt == 5'd0) // Check if read + clkdis_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (clkdis_cnt == 5'd15) + clkdis_rd <= clkdis_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge clkdis_cs_b) +begin + if (clkdis_cs_b) begin + clkdis_sdio_t <= 1'b0; + end else begin + clkdis_sdio_t <= clkdis_rd; + end +end + +// ADC 3-wire to 4-wire +reg [4:0] adc_cnt; +reg adc_rd_pre, adc_rd, adc_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge adc_cs_b) +begin + if (adc_cs_b) begin + adc_cnt <= 5'd0; + adc_rd <= 1'b0; + adc_rd_pre <= 1'b0; + end else if (!adc_cs_b) begin + if (adc_cnt < 23) + adc_cnt <= adc_cnt + 5'd1; + + if (adc_cnt == 5'd0) // Check if read + adc_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (adc_cnt == 5'd15) + adc_rd <= adc_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge adc_cs_b) +begin + if (adc_cs_b) begin + adc_sdio_t <= 1'b0; + end else begin + adc_sdio_t <= adc_rd; + end +end + +// DAC 3-wire to 4-wire +reg [4:0] dac_cnt; +reg dac_rd_pre, dac_rd, dac_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge dac_cs_b) +begin + if (dac_cs_b) begin + dac_cnt <= 5'd0; + dac_rd <= 1'b0; + dac_rd_pre <= 1'b0; + end else if (!dac_cs_b) begin + if (dac_cnt < 23) + dac_cnt <= dac_cnt + 5'd1; + + if (dac_cnt == 5'd0) // Check if read + dac_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (dac_cnt == 5'd7) + dac_rd <= dac_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge dac_cs_b) +begin + if (dac_cs_b) begin + dac_sdio_t <= 1'b0; + end else begin + dac_sdio_t <= dac_rd; + end +end + +// multiplexed slave device SPI ports +wire phdac_sck, phdac_sdi; +wire clkdis_sck, adc_sck, dac_sck; +assign clkdis_sck = (clkdis_cs_b == 1'b0) ? CPLD_PS_SPI_CLK_25 : 1'b0; + +assign CLKDIST_SPI_CS_L = clkdis_cs_b; +assign CLKDIST_SPI_SCLK = clkdis_sck; + +assign adc_sck = !adc_cs_b ? CPLD_PS_SPI_CLK_25 : 1'b0; +assign dac_sck = !dac_cs_b ? CPLD_PS_SPI_CLK_25 : 1'b0; + +assign ADC_SPI_CS_L_18 = adc_cs_b; +assign ADC_SPI_SCLK_18 = adc_sck; + +assign DAC_SPI_CS_L_18 = dac_cs_b; +assign DAC_SPI_SCLK_18 = dac_sck; + +assign CLKDIST_SPI_SDIO = (!clkdis_sdio_t && !clkdis_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; +assign ADC_SPI_SDIO_18 = (!adc_sdio_t && !adc_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; +assign DAC_SPI_SDIO_18 = (!dac_sdio_t && !dac_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; + +always @(*) +begin + CPLD_PS_SPI_SDO_25 = 1'b1; + case ({cpld_ps_cs_b, clkdis_cs_b, adc_cs_b, dac_cs_b}) + 4'b0111: begin + case (cpld_ps_spi_addr[6:5]) + PS_CPLD_REGS : CPLD_PS_SPI_SDO_25 = cpld_ps_spi_sdo; + GAIN_TABLE_RX: CPLD_PS_SPI_SDO_25 = rx_gain_load_miso; + GAIN_TABLE_TX: CPLD_PS_SPI_SDO_25 = tx_gain_load_miso; + GAIN_TABLE_LO: CPLD_PS_SPI_SDO_25 = 1'b1; + endcase + end + 4'b1011: CPLD_PS_SPI_SDO_25 = CLKDIST_SPI_SDIO; + 4'b1101: CPLD_PS_SPI_SDO_25 = ADC_SPI_SDIO_18; + 4'b1110: CPLD_PS_SPI_SDO_25 = DAC_SPI_SDIO_18; + default: ; + endcase +end + +// note: no readback from PHDAC +assign phdac_sck = (phdac_cs_b == 1'b0) ? CPLD_PS_SPI_CLK_25 : 1'b0; +assign phdac_sdi = (phdac_cs_b == 1'b0) ? CPLD_PS_SPI_SDI_25 : 1'b1; + + +assign PHDAC_SPI_SCLK = phdac_sck; +assign PHDAC_SPI_CS_L = phdac_cs_b; +assign PHDAC_SPI_SDI = phdac_sdi; + + +/* PL SPI */ +// CPLD PL SPI format (left-most bit first): +// {table_sel[1:0], reg_addr[4:0], rnw, data[15:0]} + +//TXLO, RXLO, LODIS, CPLD +localparam PLADDR_SCRATCH = 4'b0101; // scratchpad register +localparam PLADDR_RXBS = 4'b0110; +localparam PLADDR_TXBS = 4'b0111; +localparam PLADDR_RFCTRL = 4'b1000; +localparam PL_CPLD_REGS = 2'b00; + +// CPLD PL registers +reg [15:0] rxbs = 'h0; +reg [15:0] txbs = 'h0; +reg [15:0] rfctrl = 'h0; + +// register address on the falling edge of chip-select +wire txlo_cs_b = CPLD_PL_SPI_LE_18; +wire rxlo_cs_b = CPLD_PL_SPI_ADDR1_18; +wire lodis_cs_b = CPLD_PL_SPI_ADDR2_18; +wire cpld_pl_cs_b = CPLD_PL_SPI_ADDR0_18; + +wire cpld_pl_spi_rnw; +wire [6:0] cpld_pl_spi_addr; +reg [7:0] cpld_pl_spi_cmd; +reg [15:0] cpld_pl_spi_rdata; +reg [14:0] cpld_pl_spi_wdata; +reg cpld_pl_spi_sdo; +reg [4:0] cpld_pl_cnt; + +assign {cpld_pl_spi_addr, cpld_pl_spi_rnw} = cpld_pl_spi_cmd; + +reg [15:0] pl_spad; + +always @(posedge CPLD_PL_SPI_SCLK_18 or posedge cpld_pl_cs_b) +begin + if (cpld_pl_cs_b) begin + cpld_pl_cnt <= 5'd0; + end else if (!cpld_pl_cs_b) begin + if (cpld_pl_cnt < 8) begin // Address / command + cpld_pl_spi_cmd <= {cpld_pl_spi_cmd[6:0], CPLD_PL_SPI_SDI_18}; + cpld_pl_cnt <= cpld_pl_cnt + 5'd1; + end else if (cpld_pl_cnt < 23) begin // Shift in write data + cpld_pl_spi_wdata <= {cpld_pl_spi_wdata[13:0], CPLD_PL_SPI_SDI_18}; + cpld_pl_cnt <= cpld_pl_cnt + 5'd1; + end else if (!cpld_pl_spi_rnw && cpld_pl_cnt == 23 && cpld_pl_spi_addr[6:5] == PL_CPLD_REGS) begin // Write + case (cpld_pl_spi_addr[3:0]) + PLADDR_SCRATCH: pl_spad <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_RXBS: rxbs <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_TXBS: txbs <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_RFCTRL: rfctrl <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + endcase + end + if (cpld_pl_cnt == 7) begin // Set up read one cycle earlier + case (cpld_pl_spi_cmd[3:0]) + PLADDR_SCRATCH: cpld_pl_spi_rdata <= pl_spad; + PLADDR_RXBS: cpld_pl_spi_rdata <= rxbs; + PLADDR_TXBS: cpld_pl_spi_rdata <= txbs; + PLADDR_RFCTRL: cpld_pl_spi_rdata <= rfctrl; + endcase + end else begin + cpld_pl_spi_rdata <= {cpld_pl_spi_rdata[14:0], 1'b1}; + end + end +end + +always @(negedge CPLD_PL_SPI_SCLK_18) +begin + cpld_pl_spi_sdo <= cpld_pl_spi_rdata[15]; // Shift out on negative edge +end + +// multiplexed slave device SPI ports, names aliased to protect the innocent +wire lo_sck, lodis_sck; +wire lo_sdi, lodis_sdi; +// Note: lo_sck and lo_sdi -> fan out to both rxlo and txlo synths + +assign { LO_TX_CS_L, LO_RX_CS_L } = { txlo_cs_b, rxlo_cs_b}; +assign LO_SPI_SCLK = lo_sck; +assign LO_SPI_SDI = lo_sdi; + + +assign LODIST_Bd_SPI_CS_L = lodis_cs_b; +assign LODIST_Bd_SPI_SDI = lodis_sdi; +assign LODIST_Bd_SPI_SCLK = lodis_sck; + + +assign lodis_sck = !lodis_cs_b ? CPLD_PL_SPI_SCLK_18 : 1'b0; +assign lodis_sdi = !lodis_cs_b ? CPLD_PL_SPI_SDI_18 : 1'b1; + +assign { lo_sck, lo_sdi } = (!txlo_cs_b | !rxlo_cs_b) ? {CPLD_PL_SPI_SCLK_18,CPLD_PL_SPI_SDI_18} : 2'b01; + + +always @(*) +begin + CPLD_PL_SPI_SDO_18 = 1'bz; + case ({cpld_pl_cs_b, txlo_cs_b, rxlo_cs_b}) + 3'b110: CPLD_PL_SPI_SDO_18 = LOSYNTH_RX_MUXOUT; + 3'b101: CPLD_PL_SPI_SDO_18 = LOSYNTH_TX_MUXOUT; + 3'b011: begin + case (cpld_pl_spi_addr[6:5]) + PL_CPLD_REGS : CPLD_PL_SPI_SDO_18 = cpld_pl_spi_sdo; + GAIN_TABLE_RX: CPLD_PL_SPI_SDO_18 = rx_gain_ctrl_miso; + GAIN_TABLE_TX: CPLD_PL_SPI_SDO_18 = tx_gain_ctrl_miso; + GAIN_TABLE_LO: CPLD_PL_SPI_SDO_18 = lo_gain_ctrl_miso; + endcase + end + default: ; + endcase +end + +assign rx_gain_ctrl_tbl_sel = rxbs[12]; +assign { Rx_Sw6_Ctrl_2, + Rx_Sw6_Ctrl_1, + Rx_Sw4_Ctrl_4, + Rx_Sw4_Ctrl_3, + Rx_Sw4_Ctrl_2, + Rx_Sw4_Ctrl_1, + Rx_Sw3_Ctrl_2, + Rx_Sw3_Ctrl_1, + Rx_Sw2_Ctrl, + Rx_Sw1_Ctrl_2, + Rx_Sw1_Ctrl_1 } = { rxbs[11:1] }; + +assign tx_gain_ctrl_tbl_sel = txbs[12]; +assign { Tx_Sw5_Ctrl_2, + Tx_Sw5_Ctrl_1, + Tx_Sw3_Ctrl_4, + Tx_Sw3_Ctrl_3, + Tx_Sw3_Ctrl_2, + Tx_Sw3_Ctrl_1, + Tx_Sw2_Ctrl_2, + Tx_Sw2_Ctrl_1} = { txbs[11:4] }; + +// Terminate TX when idle +assign {Tx_Sw1_Ctrl_2, Tx_Sw1_Ctrl_1} = CPLD_ATR_TX_18 ? txbs[3:2] : TX_SW1_TERM; + +assign { Rx_LO_Filter_Sw_2, + Rx_LO_Filter_Sw_1, + Tx_LO_Filter_Sw_2, + Tx_LO_Filter_Sw_1, + Rx_Demod_ADJ_1, + Rx_Demod_ADJ_2, + Rx_LO_Input_Select } = rfctrl[15:9]; + +assign { Rx_HB_LB_Select, + Tx_LO_Input_Select } = rfctrl[7:6]; + +assign { Tx_HB_LB_Select, + Cal_iso_Sw_Ctrl } + = { rfctrl[4:3] }; + + +// RX Gain Table +wire [4:0] rx_dsa; + +rhodium_gain_ctrl #( + .TABLE_NUM(GAIN_TABLE_RX) +) rx_gain_table ( + .load_table_sel(rx_gain_load_tbl_sel), + .load_sck(CPLD_PS_SPI_CLK_25), + .load_csb(cpld_ps_cs_b), + .load_mosi(CPLD_PS_SPI_SDI_25), + .load_miso(rx_gain_load_miso), + .ctrl_table_sel(rx_gain_ctrl_tbl_sel), + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(rx_gain_ctrl_miso), + .dsa(rx_dsa), + .dsa1_le(Rx_DSA1_LE), + .dsa2_le(Rx_DSA2_LE) +); + +// TX Gain Table +wire [4:0] tx_dsa; + +rhodium_gain_ctrl #( + .TABLE_NUM(GAIN_TABLE_TX) +) tx_gain_table ( + .load_table_sel(tx_gain_load_tbl_sel), + .load_sck(CPLD_PS_SPI_CLK_25), + .load_csb(cpld_ps_cs_b), + .load_mosi(CPLD_PS_SPI_SDI_25), + .load_miso(tx_gain_load_miso), + .ctrl_table_sel(tx_gain_ctrl_tbl_sel), + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(tx_gain_ctrl_miso), + .dsa(tx_dsa), + .dsa1_le(Tx_DSA1_LE), + .dsa2_le(Tx_DSA2_LE) +); + +// LO Gain Table +wire [4:0] lo_dsa; + +rhodium_lo_gain #( + .TABLE_NUM(GAIN_TABLE_LO) +) lo_gain_table ( + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(lo_gain_ctrl_miso), + .dsa(lo_dsa), + .dsa1_le(RxLO_DSA_LE), + .dsa2_le(TxLO_DSA_LE) +); + +// Rx data shared by DSA1, DSA2 +assign { Rx_DSA_C16, Rx_DSA_C8, Rx_DSA_C4, Rx_DSA_C2, Rx_DSA_C1 } = rx_dsa; + +// Tx data shared by DSA1, DSA2 +assign { Tx_DSA_C16, Tx_DSA_C8, Tx_DSA_C4, Tx_DSA_C2, Tx_DSA_C1 } = tx_dsa; + +// data shared by both tx and rx lo DSAs +assign { LO_DSA_C16, LO_DSA_C8, LO_DSA_C4, LO_DSA_C2, LO_DSA_C1 } = lo_dsa; + +endmodule +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc new file mode 100644 index 000000000..e78342849 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc @@ -0,0 +1,118 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx". +# See this spreadsheet for more details and explanations. + +#******************************************************************************* +## Daughterboard Clocks +# +# 122.88, 200, 245.76 and 250 MHz Sample Rates are allowable with 2:1/1:2 DSP and +# 2 samples/cycle arriving at the FPGA: +# +# <-- 2:1/1:2 --> +# | Supported | Sample rate | FPGA Clk | +# |sample rates | at JESD core | Frequency | +# | (MSPS) | (MSPS) | (MHz) | +# |-------------|--------------|-----------| +# | 122.88 | 491.52 | 245.76 | (uses DUC/DDC) +# | 200.00 | 400.00 | 200.00 | +# | 245.76 | 491.52 | 245.76 | +# | 250.00 | 500.00 | 250.00 | +# +# Therefore, supported sample clocks are: 122.88, 200, 245.76 and 250 MHz. +# Constrain the paths to the max rate to support all rates in a single FPGA image. +set SAMPLE_CLK_PERIOD 4.00 +create_clock -name fpga_clk_a -period $SAMPLE_CLK_PERIOD [get_ports DBA_FPGA_CLK_P] +create_clock -name fpga_clk_b -period $SAMPLE_CLK_PERIOD [get_ports DBB_FPGA_CLK_P] +create_clock -name mgt_clk_dba -period $SAMPLE_CLK_PERIOD [get_ports DBA_MGTCLK_P] +create_clock -name mgt_clk_dbb -period $SAMPLE_CLK_PERIOD [get_ports DBB_MGTCLK_P] + +# The Radio Clocks coming from the DBs are synchronized together (at the converters) to +# a typical value of less than 100ps. To give ourselves and Vivado some margin, we claim +# here that the DB-B Radio Clock can arrive 500ps before or after the DB-A clock at +# the FPGA (note that the trace lengths of the Radio Clocks coming from the DBs to the +# FPGA are about 0.5" different, thereby incurring ~80ps of additional skew at the FPGA). +# There is one spot in the FPGA where we cross domains between the DB-A and +# DB-B clock, so we must ensure that Vivado can analyze that path safely. +set FPGA_CLK_EARLY -0.5 +set FPGA_CLK_LATE 0.5 +set_clock_latency -source -early $FPGA_CLK_EARLY [get_clocks fpga_clk_b] +set_clock_latency -source -late $FPGA_CLK_LATE [get_clocks fpga_clk_b] + +# Virtual clocks for constraining I/O (used below) +create_clock -name fpga_clk_a_v -period $SAMPLE_CLK_PERIOD +create_clock -name fpga_clk_b_v -period $SAMPLE_CLK_PERIOD + +# The set_clock_latency constraints set on fpga_clk_b are problematic when used with +# I/O timing, since the analyzer gives us a double-hit on the latency. One workaround +# (used here) is to simply swap the early and late times for the virtual clock so that +# it cancels out the source latency during analysis. D. Jepson tested this by setting +# the early and late numbers to zero and then their actual value, running timing reports +# on each. The slack report matches for both cases, showing that the reversed early/late +# numbers on the virtual clock zero out the latency effects on the actual clock. +# +# Note this is not a problem for the fpga_clk_a, since no latency is added. So only apply +# it to fpga_clk_b_v. +set_clock_latency -source -early $FPGA_CLK_LATE [get_clocks fpga_clk_b_v] +set_clock_latency -source -late $FPGA_CLK_EARLY [get_clocks fpga_clk_b_v] + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + +create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + + + +#******************************************************************************* +## Generated clocks for output busses to the daughterboard +# +# These clock definitions need to come above the set_clock_groups commands below to work! + +# Define clocks on the PL SPI clock output pins for both DBs. Actual divider values are +# set by SW at run-time. Current divider value is 125 based on what radio clock +# rate is set. +# For the CPLD SPI endpoint alone, we need it to run at ~25 MHz (writes only), this means +# that at times, the PL SPI will have its divider set to 10 (radio_clock = 250 MHz) or 8 +# (radio_clock = 200 MHz). +# The readback clock is lower (~10 MHz), so create a separate clock for it. +# Use readback divide value of 24 for an even divider (and some overconstraining). +set PL_SPI_DIVIDE_VAL 10 +set PL_SPI_RB_DIVIDE_VAL 24 +set PL_SPI_CLK_A [get_ports DBA_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_a \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_A +create_generated_clock -name pl_spi_rb_clk_a \ + -master_clock [get_clocks radio_clk] \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_RB_DIVIDE_VAL -add $PL_SPI_CLK_A +set PL_SPI_CLK_B [get_ports DBB_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_b \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_B +create_generated_clock -name pl_spi_rb_clk_b \ + -master_clock [get_clocks radio_clk] \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_RB_DIVIDE_VAL -add $PL_SPI_CLK_B + +#******************************************************************************* +## JTAG +set DB_JTAG_DIVISOR 4 +create_generated_clock -name dba_jtag_tck -divide_by $DB_JTAG_DIVISOR \ + -source [get_pins {inst_n310_ps/jtag_0/U0/bitq_ctrl/bitq_state_reg[1]/C}] \ + [get_ports DBA_CPLD_JTAG_TCK] + +create_generated_clock -name dbb_jtag_tck -divide_by $DB_JTAG_DIVISOR \ + -source [get_pins {inst_n310_ps/jtag_1/U0/bitq_ctrl/bitq_state_reg[1]/C}] \ + [get_ports DBB_CPLD_JTAG_TCK] + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd new file mode 100644 index 000000000..52c68ab4a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd @@ -0,0 +1,345 @@ +------------------------------------------------------------------------------- +-- +-- File: ClockingRegs.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N32x +-- Date: 17 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register access to the control/status bits and interfaces for the +-- RadioClocking module. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgClockingRegMap.all; + use work.PkgRegs.all; + + +entity ClockingRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + -- Register Bus Clock -- this module connects the BusClk to PsClk, so it's limited + -- to 200 MHz! + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Phase shift interface to the RadioClkMmcm. + -- There is a reset crossing here between the MMCM reset and aReset. The outgoing + -- crossing is safe because (a) the enable signal driven to the MMCM is a strobe-only + -- signal and (b) this interface should only be used when the MMCM is not in reset + -- (SW waits for the MMCM to be out of reset and locked before using this interface). + -- The only input signal, pPsDone, is double-synced in this file before being used. + -- This is OK (even though it is a strobe signal) because there is only a reset + -- crossing and not a clock domain crossing. + pPsInc : out std_logic; + pPsEn : out std_logic; + pPsDone : in std_logic; + + -- PsClk is driven directly by BusClk, so p = b in the logic below! + PsClk : out std_logic; + + -- Sync reset strobes from the register bus to the RadioClkMmcm. + bRadioClkMmcmReset : out std_logic; + -- Status of RadioClk MMCM lock to register bus. + aRadioClksValid : in std_logic; + + bRadioClk1xEnabled : out std_logic; + bRadioClk2xEnabled : out std_logic; + bRadioClk3xEnabled : out std_logic; + + bJesdRefClkPresent : in std_logic + ); +end ClockingRegs; + + +architecture RTL of ClockingRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRadioClkMmcmResetInt : std_logic := '1'; + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + + signal bPsDone, + bPsEn, + bPsInc, + pPsDoneDs_ms, + pPsDoneDs : std_logic := '0'; + + signal bRadioClk1xEnabledInt, + bRadioClk2xEnabledInt, + bRadioClk3xEnabledInt, + bRadioClksValid_ms, + bRadioClksValid : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClksValid_ms : signal is "true"; + attribute ASYNC_REG of bRadioClksValid : signal is "true"; + attribute ASYNC_REG of pPsDoneDs_ms : signal is "true"; + attribute ASYNC_REG of pPsDoneDs : signal is "true"; + +begin + + -- Locals to outputs. + PsClk <= BusClk; + pPsInc <= bPsInc; + pPsEn <= bPsEn; + + bRadioClkMmcmReset <= bRadioClkMmcmResetInt; + + bRadioClk1xEnabled <= bRadioClk1xEnabledInt; + bRadioClk2xEnabled <= bRadioClk2xEnabledInt; + bRadioClk3xEnabled <= bRadioClk3xEnabledInt; + + + -- Write Registers : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + WriteRegisters: process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + else + -- Clear strobe + bPsEn <= '0'; + + if RegWrite(kPhaseShiftControl, bRegPortIn) then + if bRegPortIn.Data(kPsInc) = '1' then + bPsInc <= '1'; + bPsEn <= '1'; + elsif bRegPortIn.Data(kPsDec) = '1' then + bPsInc <= '0'; + bPsEn <= '1'; + end if; + end if; + + if RegWrite(kRadioClkMmcm, bRegPortIn) then + -- Set/Clear pair + if bRegPortIn.Data(kRadioClkMmcmResetSet) = '1' then + bRadioClkMmcmResetInt <= '1'; + elsif bRegPortIn.Data(kRadioClkMmcmResetClear) = '1' then + bRadioClkMmcmResetInt <= '0'; + end if; + end if; + + if RegWrite(kRadioClkEnables, bRegPortIn) then + bRadioClk1xEnabledInt <= bRegPortIn.Data(kRadioClk1xEnabled); + bRadioClk2xEnabledInt <= bRegPortIn.Data(kRadioClk2xEnabled); + bRadioClk3xEnabledInt <= bRegPortIn.Data(kRadioClk3xEnabled); + end if; + + end if; + end if; + end process WriteRegisters; + + + DoubleSyncs : process (aReset, BusClk) + begin + if aReset then + bRadioClksValid_ms <= '0'; + bRadioClksValid <= '0'; + pPsDoneDs_ms <= '0'; + pPsDoneDs <= '0'; + elsif rising_edge(BusClk) then + -- No sync reset on double-syncs (however there are default assignments above)! + bRadioClksValid_ms <= aRadioClksValid; + bRadioClksValid <= bRadioClksValid_ms; + pPsDoneDs_ms <= pPsDone; + pPsDoneDs <= pPsDoneDs_ms; + end if; + end process; + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + else + -- Deassert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + -- Process the returned data from the phase shifter in the MMCM. Note that even + -- though the prefixes are different (p and b), we drive the PsClk from the BusClk + -- so this "crossing" is actually safe. Whenever the Done signal asserts (pPsDone - + -- pay attention to the prefix!) from the MMCM, we set a sticky bit to tell SW + -- that the shift operation is complete. + -- + -- However, if pPsDone asserts at the same time that SW tries to read the register, + -- we should accurately report that the operation is indeed complete and then NOT + -- store the sticky (since it has already been read by SW). If a read does not come + -- through at the same time pPsDone is asserted, then we store the done state as a + -- sticky, bPsDone, which is only cleared by a read to this register. + if RegRead(kPhaseShiftControl, bRegPortIn) then + -- The phase shift is always enabled for the feedback clock in RadioClocking.vhd + bRegPortOutLcl.Data(kPsEnabledForFdbClk) <= '1'; + bRegPortOutLcl.Data(kPsDone) <= bPsDone or pPsDoneDs; + bPsDone <= '0'; + elsif pPsDoneDs = '1' then + bPsDone <= '1'; + end if; + + if RegRead(kRadioClkMmcm, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClkMmcmLocked) <= bRadioClksValid; + end if; + + if RegRead(kRadioClkEnables, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClk1xEnabled) <= bRadioClk1xEnabledInt; + bRegPortOutLcl.Data(kRadioClk2xEnabled) <= bRadioClk2xEnabledInt; + bRegPortOutLcl.Data(kRadioClk3xEnabled) <= bRadioClk3xEnabledInt; + end if; + + if RegRead(kMgtRefClkStatus, bRegPortIn) then + bRegPortOutLcl.Data(kJesdRefClkPresent) <= bJesdRefClkPresent; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +--<regmap name="ClockingRegMap"> +-- <group name="ClockingRegs"> +-- +-- <register name="RadioClkMmcm" size="32" offset="0x20" attributes="Readable|Writable"> +-- <info> +-- </info> +-- <bitfield name="RadioClkMmcmLocked" range="4"> +-- <info> +-- Reflects the locked status of the MMCM. '1' = locked. This bit is only valid +-- when the MMCM reset is de-asserted. Read-only. +-- </info> +-- </bitfield> +-- <bitfield name="RadioClkMmcmResetClear" range="1" attributes="Strobe"> +-- <info> +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to de-assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- </info> +-- </bitfield> +-- <bitfield name="RadioClkMmcmResetSet" range="0" attributes="Strobe"> +-- <info> +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="PhaseShiftControl" size="32" offset="0x24" attributes="Readable|Writable"> +-- <info> +-- Phase Shift for RadioClkMmcm. +-- </info> +-- <bitfield name="PsDone" range="28"> +-- <info> +-- This bit should set after a shift operation successfully completes. +-- Reading this register will clear this bit. Read-only. +-- </info> +-- </bitfield> +-- <bitfield name="PsInc" range="0" attributes="Strobe"> +-- <info> +-- Strobe this bit to increment the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- </info> +-- </bitfield> +-- <bitfield name="PsDec" range="4" attributes="Strobe"> +-- <info> +-- Strobe this bit to decrement the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- </info> +-- </bitfield> +-- <bitfield name="PsEnabledForFdbClk" range="16"> +-- <info> +-- Read-only. +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="RadioClkEnables" size="32" offset="0x28" attributes="Readable|Writable"> +-- <info> +-- </info> +-- <bitfield name="RadioClk3xEnabled" range="8"> +-- <info> +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- </info> +-- </bitfield> +-- <bitfield name="RadioClk2xEnabled" range="4"> +-- <info> +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- </info> +-- </bitfield> +-- <bitfield name="RadioClk1xEnabled" range="0"> +-- <info> +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- </info> +-- </bitfield> +-- </register> +-- +-- <register name="MgtRefClkStatus" size="32" offset="0x30" attributes="Readable"> +-- <info> +-- </info> +-- <bitfield name="JesdRefClkPresent" range="0"> +-- <info> +-- Live indicator of the MGT Reference Clock toggling and within expected +-- frequency limits. If this bit is de-asserted, then the JESD204b core will +-- not function correctly! +-- </info> +-- </bitfield> +-- </register> +-- +-- </group> +-- +--</regmap> +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd new file mode 100644 index 000000000..8a9c20372 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- +-- File: DaughterboardRegs.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N32x +-- Date: 27 April 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register interface to the semi-static control lines for the Mg +-- Daughterboard. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgDaughterboardRegMap.all; + use work.PkgRegs.all; + + +entity DaughterboardRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Slot and DB ID values. These should be tied to constants! + kDbId : in std_logic_vector(15 downto 0); + kSlotId : in std_logic + + ); +end DaughterboardRegs; + + +architecture RTL of DaughterboardRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + +begin + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + elsif rising_edge(BusClk) then + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + else + -- De-assert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + if RegRead(kDaughterboardId, bRegPortIn) then + bRegPortOutLcl.Data(kDbIdValMsb downto kDbIdVal) <= kDbId; + bRegPortOutLcl.Data(kSlotIdVal) <= kSlotId; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +--<regmap name="DaughterboardRegMap"> +-- <group name="StaticControl" order="1"> +-- +-- <register name="DaughterboardId" size="32" offset="0x30" attributes="Readable"> +-- <info> +-- </info> +-- <bitfield name="DbIdVal" range="15..0"> +-- <info> +-- ID for the DB with which this file is designed to communicate. Matches the DB +-- EEPROM ID. +-- </info> +-- </bitfield> +-- <bitfield name="SlotIdVal" range="16"> +-- <info> +-- ID for the Slot this module controls. Options are 0 and 1 for the N310 MB. +-- </info> +-- </bitfield> +-- </register> +-- +-- </group> +-- +-- +--</regmap> +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd new file mode 100644 index 000000000..f54a976d1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd @@ -0,0 +1,563 @@ +------------------------------------------------------------------------------- +-- +-- File: DbCore.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N320 +-- Date: 12 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for Daughterboard Control. This includes the semi-static control +-- and status registers, clocking, synchronization, and JESD204B cores. +-- +-- There is no version register for the plain-text files here. +-- Version control for the Sync and JESD204B cores is internal to the netlists. +-- +-- The resets for this core are almost entirely local and/or synchronous. +-- bBusReset is a Synchronous reset on the BusClk domain that resets all of the +-- registers connected to the RegPort, as well as any other stray registers +-- connected to the BusClk. All other resets are local to the modules they touch. +-- No other reset drives all modules universally. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRhPersonality.all; + use work.PkgRegs.all; + use work.PkgJesdConfig.all; + use work.PkgAdcDacInterfaceTypes.all; + + +entity DbCore is + generic( + -- Set to '1' to include the White Rabbit TDC. + kInclWhiteRabbitTdc : std_logic := '0' + ); + port( + + -- Resets -- + -- Synchronous Reset for the BusClk domain (mainly for the RegPort) + bBusReset : in std_logic; + + -- Clocks -- + -- Register Bus Clock (any frequency) + BusClk : in std_logic; + -- Always-on at 40 MHz + Clk40 : in std_logic; + -- Super secret crazy awesome measurement clock at weird frequencies. + MeasClk : in std_logic; + -- FPGA Sample Clock from DB LMK + FpgaClk_p : in std_logic; + FpgaClk_n : in std_logic; + + -- Sample Clock Sharing. The clocks generated in this module are exported out to the + -- top level so they can be shared amongst daughterboards. Therefore they must be + -- driven back into the SampleClk*x inputs at a higher level in order for this module + -- to work correctly. There are a few isolated cases where SampleClk*xOut is used + -- directly in this module, and those are documented below. + SampleClk1xOut : out std_logic; + SampleClk1x : in std_logic; + SampleClk2xOut : out std_logic; + SampleClk2x : in std_logic; + + + -- Register Ports -- + -- + -- Only synchronous resets can be used for these ports! + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + + -- Slot ID value. This should be tied to a constant! + kSlotId : in std_logic; + + + -- SYSREF -- + -- + -- SYSREF direct from the LMK + sSysRefFpgaLvds_p, + sSysRefFpgaLvds_n : in std_logic; + -- SYNC directly to the LMK + aLmkSync : out std_logic; + + + -- JESD Signals -- + -- + -- GTX Sample Clock Reference Input. Direct connect to FPGA pins. + JesdRefClk_p, + JesdRefClk_n : in std_logic; + + -- ADC JESD PHY Interface. Direct connect to FPGA pins. + aAdcRx_p, + aAdcRx_n : in std_logic_vector(3 downto 0); + aSyncAdcOut_n : out std_logic; + + -- DAC JESD PHY Interface. Direct connect to FPGA pins. + aDacTx_p, + aDacTx_n : out std_logic_vector(3 downto 0); + aSyncDacIn_n : in std_logic; + + + -- Data Pipes to/from the DACs/ADCs -- + -- + -- - Data is presented as two samples per cycle. + -- - sAdcDataValid asserts when ADC data is valid. + -- - sDacReadyForInput asserts when DAC data is ready to be received. + -- + -- Reset Crossings: + -- The ADC data and valid outputs are synchronously cleared before the asynchronous + -- reset is asserted--preventing any reset crossing issues here between the RX + -- (internal to the core) reset and the no-reset domain of RFNoC. + -- + -- The DAC samples should be zeros on reset de-assertion due to RFI being de-asserted + -- in reset. If they are not zeros, then it is still OK because data is ignored until + -- RFI is asserted. DAC RFI is double-synchronized to protect against the reset + -- crossing. This is safe to do because it simply delays the output of RFI by two + -- cycles on the assertion edge, and as long as reset is held for more than two + -- cycles, the de-assertion edge of RFI should come long before the TX module is + -- taken out of reset. + + -- Supporting 2 samples per clk cycle. + sAdcDataValid : out std_logic; + sAdcDataSample0I : out std_logic_vector(15 downto 0); + sAdcDataSample0Q : out std_logic_vector(15 downto 0); + sAdcDataSample1I : out std_logic_vector(15 downto 0); + sAdcDataSample1Q : out std_logic_vector(15 downto 0); + -- + sDacReadyForInput : out std_logic; + sDacDataSample0I : in std_logic_vector(15 downto 0); + sDacDataSample0Q : in std_logic_vector(15 downto 0); + sDacDataSample1I : in std_logic_vector(15 downto 0); + sDacDataSample1Q : in std_logic_vector(15 downto 0); + + + -- RefClk & Timing & Sync -- + RefClk : in std_logic; + rPpsPulse : in std_logic; + rGatedPulseToPin : inout std_logic; -- straight to pin + sGatedPulseToPin : inout std_logic; -- straight to pin + sPps : out std_logic; + sPpsToIob : out std_logic; + + -- White Rabbit Timing & Sync -- + WrRefClk : in std_logic; + rWrPpsPulse : in std_logic; + rWrGatedPulseToPin : inout std_logic; -- straight to pin + sWrGatedPulseToPin : inout std_logic; -- straight to pin + aPpsSfpSel : in std_logic_vector(1 downto 0); + + -- Debug for JESD + sAdcSync : out std_logic; + sDacSync : out std_logic; + sSysRef : out std_logic; + + -- Debug for Timing & Sync + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + rWrRpTransfer : out std_logic; + sWrSpTransfer : out std_logic + ); + +end DbCore; + + +architecture RTL of DbCore is + + component Jesd204bXcvrCore + port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aLmkSync : out STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR(49 downto 0); + bRegPortOutFlat : out STD_LOGIC_VECTOR(33 downto 0); + CaptureSysRefClk : in STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR(3 downto 0); + aAdcRx_n : in STD_LOGIC_VECTOR(3 downto 0); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR(3 downto 0); + aDacTx_n : out STD_LOGIC_VECTOR(3 downto 0); + aSyncDacIn_n : in STD_LOGIC; + fAdcDataFlatter : out STD_LOGIC_VECTOR(63 downto 0); + fDacDataFlatter : in STD_LOGIC_VECTOR(63 downto 0); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC); + end component; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + --vhook_sigstart + signal aAdcSync: STD_LOGIC; + signal aDacSync: STD_LOGIC; + signal bClockingRegPortOut: RegPortOut_t; + signal bDbRegPortOut: RegPortOut_t; + signal bFpgaClksStable: STD_LOGIC; + signal bJesdCoreRegPortInFlat: STD_LOGIC_VECTOR(49 downto 0); + signal bJesdCoreRegPortOutFlat: STD_LOGIC_VECTOR(33 downto 0); + signal bJesdRefClkPresent: STD_LOGIC; + signal bRadioClk1xEnabled: std_logic; + signal bRadioClk2xEnabled: std_logic; + signal bRadioClk3xEnabled: std_logic; + signal bRadioClkMmcmReset: std_logic; + signal bRadioClksValid: std_logic; + signal pPsDone: std_logic; + signal pPsEn: std_logic; + signal pPsInc: std_logic; + signal PsClk: std_logic; + signal sAdcDataFlatter: STD_LOGIC_VECTOR(63 downto 0); + signal SampleClk1xOutLcl: std_logic; + signal sDacDataFlatter: STD_LOGIC_VECTOR(63 downto 0); + signal sDacReadyForInputAsyncReset: STD_LOGIC; + signal sRegPps: std_logic; + signal sSysRefAsyncReset: STD_LOGIC; + signal sWrPps: std_logic; + --vhook_sigend + + signal bJesdRegPortInGrp, bSyncRegPortIn, bWrSyncRegPortIn, bRegPortIn : RegPortIn_t; + signal bJesdRegPortOut, bSyncRegPortOut, bWrSyncRegPortOut, bRegPortOut : RegPortOut_t; + + signal sDacReadyForInput_ms, sDacReadyForInputLcl, + sDacSync_ms, sDacSyncLcl, + sAdcSync_ms, sAdcSyncLcl, + sSysRef_ms, sSysRefLcl : std_logic := '0'; + + signal sAdcDataAry : AdcDataAry_t; + signal sDacDataAry : DacDataAry_t; + + signal sPpsSfpSel_ms, sPpsSfpSel : std_logic_vector(1 downto 0) := (others => '0'); + signal sUseWrTdcPps : boolean := false; + signal sPpsInt, sPpsMuxed : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sDacReadyForInput_ms : signal is "true"; + attribute ASYNC_REG of sDacReadyForInputLcl : signal is "true"; + attribute ASYNC_REG of sDacSync_ms : signal is "true"; + attribute ASYNC_REG of sDacSyncLcl : signal is "true"; + attribute ASYNC_REG of sAdcSync_ms : signal is "true"; + attribute ASYNC_REG of sAdcSyncLcl : signal is "true"; + attribute ASYNC_REG of sSysRef_ms : signal is "true"; + attribute ASYNC_REG of sSysRefLcl : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel_ms : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel : signal is "true"; + +begin + + bRegPortOutFlat <= Flatten(bRegPortOut); + bRegPortIn <= Unflatten(bRegPortInFlat); + + + -- Combine return RegPorts. + bRegPortOut <= bJesdRegPortOut + + bClockingRegPortOut + + bSyncRegPortOut + bWrSyncRegPortOut + + bDbRegPortOut; + + + -- Clocking : ------------------------------------------------------------------------- + -- Automatically export the Sample Clocks and only use the incoming clocks in the + -- remainder of the logic. For a single module, the clocks must be looped back + -- in at a higher level! + -- ------------------------------------------------------------------------------------ + + --vhook_e RadioClocking + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a RadioClk1x SampleClk1xOutLcl + --vhook_a RadioClk2x SampleClk2xOut + --vhook_a RadioClk3x open + RadioClockingx: entity work.RadioClocking (rtl) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --in std_logic + bRadioClksValid => bRadioClksValid, --out std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --in std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --in std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --in std_logic + pPsInc => pPsInc, --in std_logic + pPsEn => pPsEn, --in std_logic + PsClk => PsClk, --in std_logic + pPsDone => pPsDone, --out std_logic + FpgaClk_n => FpgaClk_n, --in std_logic + FpgaClk_p => FpgaClk_p, --in std_logic + RadioClk1x => SampleClk1xOutLcl, --out std_logic + RadioClk2x => SampleClk2xOut, --out std_logic + RadioClk3x => open); --out std_logic + + -- We need an internal copy of SampleClk1x for the TDC, since we don't want to try + -- and align the other DB's clock accidentally. + SampleClk1xOut <= SampleClk1xOutLcl; + + --vhook_e ClockingRegs + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bClockingRegPortOut + --vhook_a aRadioClksValid bRadioClksValid + ClockingRegsx: entity work.ClockingRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bClockingRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + pPsInc => pPsInc, --out std_logic + pPsEn => pPsEn, --out std_logic + pPsDone => pPsDone, --in std_logic + PsClk => PsClk, --out std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --out std_logic + aRadioClksValid => bRadioClksValid, --in std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --out std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --out std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --out std_logic + bJesdRefClkPresent => bJesdRefClkPresent); --in std_logic + + + + -- JESD204B : ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + bJesdRegPortInGrp <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kJesdRegGroupInDbRegs); -- 0x2000 to 0x3FFC + + -- Expand/compress the RegPort for moving through the netlist boundary. + bJesdRegPortOut <= Unflatten(bJesdCoreRegPortOutFlat); + bJesdCoreRegPortInFlat <= Flatten(bJesdRegPortInGrp); + + + --vhook Jesd204bXcvrCore + --vhook_a bRegPortInFlat bJesdCoreRegPortInFlat + --vhook_a bRegPortOutFlat bJesdCoreRegPortOutFlat + --vhook_a FpgaClk1x SampleClk1x + --vhook_a FpgaClk2x SampleClk2x + --vhook_a ReliableClk40 Clk40 + --vhook_a CaptureSysRefClk SampleClk1xOutLcl + --vhook_a cSysRefFpgaLvds_p sSysRefFpgaLvds_p + --vhook_a cSysRefFpgaLvds_n sSysRefFpgaLvds_n + --vhook_a fSysRef sSysRefAsyncReset + --vhook_a fDacReadyForInput sDacReadyForInputAsyncReset + --vhook_a {^f(.*)} s$1 + Jesd204bXcvrCorex: Jesd204bXcvrCore + port map ( + bBusReset => bBusReset, --in STD_LOGIC + BusClk => BusClk, --in STD_LOGIC + ReliableClk40 => Clk40, --in STD_LOGIC + FpgaClk1x => SampleClk1x, --in STD_LOGIC + FpgaClk2x => SampleClk2x, --in STD_LOGIC + bFpgaClksStable => bFpgaClksStable, --in STD_LOGIC + JesdRefClk_p => JesdRefClk_p, --in STD_LOGIC + JesdRefClk_n => JesdRefClk_n, --in STD_LOGIC + bJesdRefClkPresent => bJesdRefClkPresent, --out STD_LOGIC + aLmkSync => aLmkSync, --out STD_LOGIC + bRegPortInFlat => bJesdCoreRegPortInFlat, --in STD_LOGIC_VECTOR(49:0) + bRegPortOutFlat => bJesdCoreRegPortOutFlat, --out STD_LOGIC_VECTOR(33:0) + CaptureSysRefClk => SampleClk1xOutLcl, --in STD_LOGIC + cSysRefFpgaLvds_p => sSysRefFpgaLvds_p, --in STD_LOGIC + cSysRefFpgaLvds_n => sSysRefFpgaLvds_n, --in STD_LOGIC + fSysRef => sSysRefAsyncReset, --out STD_LOGIC + aAdcRx_p => aAdcRx_p, --in STD_LOGIC_VECTOR(3:0) + aAdcRx_n => aAdcRx_n, --in STD_LOGIC_VECTOR(3:0) + aSyncAdcOut_n => aSyncAdcOut_n, --out STD_LOGIC + aDacTx_p => aDacTx_p, --out STD_LOGIC_VECTOR(3:0) + aDacTx_n => aDacTx_n, --out STD_LOGIC_VECTOR(3:0) + aSyncDacIn_n => aSyncDacIn_n, --in STD_LOGIC + fAdcDataFlatter => sAdcDataFlatter, --out STD_LOGIC_VECTOR(63:0) + fDacDataFlatter => sDacDataFlatter, --in STD_LOGIC_VECTOR(63:0) + fAdcDataValid => sAdcDataValid, --out STD_LOGIC + fDacReadyForInput => sDacReadyForInputAsyncReset, --out STD_LOGIC + aDacSync => aDacSync, --out STD_LOGIC + aAdcSync => aAdcSync); --out STD_LOGIC + + + JesdDoubleSyncToNoResetSampleClk : process (SampleClk1x) + begin + if rising_edge(SampleClk1x) then + sDacReadyForInput_ms <= sDacReadyForInputAsyncReset; + sDacReadyForInputLcl <= sDacReadyForInput_ms; + -- No clock crossing here -- just reset, although the prefix declares otherwise... + sDacSync_ms <= aDacSync; + sDacSyncLcl <= sDacSync_ms; + sAdcSync_ms <= aAdcSync; + sAdcSyncLcl <= sAdcSync_ms; + sSysRef_ms <= sSysRefAsyncReset; + sSysRefLcl <= sSysRef_ms; + end if; + end process; + + -- Locals to outputs. + sDacReadyForInput <= sDacReadyForInputLcl; + sDacSync <= sDacSyncLcl; + sAdcSync <= sAdcSyncLcl; + sSysRef <= sSysRefLcl; + + -- Just combine the first two enables, since they're the ones that are used for JESD. + -- No reset crossing here, since bFpgaClksStable is only received by a no-reset domain + -- and the MGTs directly. + bFpgaClksStable <= bRadioClksValid and bRadioClk1xEnabled and bRadioClk2xEnabled; + + -- Compress/expand the flat data types from the netlist and route to top level. + sAdcDataAry <= Unflatten(sAdcDataFlatter); + sDacDataFlatter <= Flatten(sDacDataAry); + + -- Data mapping using the array types. + sAdcDataSample0I <= (sAdcDataAry(0).Data.I & sAdcDataAry(0).Over.I & sAdcDataAry(0).CBit1.I); + sAdcDataSample0Q <= (sAdcDataAry(0).Data.Q & sAdcDataAry(0).Over.Q & sAdcDataAry(0).CBit1.Q); + sAdcDataSample1I <= (sAdcDataAry(1).Data.I & sAdcDataAry(1).Over.I & sAdcDataAry(1).CBit1.I); + sAdcDataSample1Q <= (sAdcDataAry(1).Data.Q & sAdcDataAry(1).Over.Q & sAdcDataAry(1).CBit1.Q); + -- + sDacDataAry(0).Data.I <= sDacDataSample0I; + sDacDataAry(0).Data.Q <= sDacDataSample0Q; + sDacDataAry(1).Data.I <= sDacDataSample1I; + sDacDataAry(1).Data.Q <= sDacDataSample1Q; + + + -- Timing and Sync : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + bSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc0OffsetsInEndpoint); -- 0x0200 + + --vhook_e TdcWrapper + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a sPpsPulse sRegPps + TdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sRegPps, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + WrTdcGen: if kInclWhiteRabbitTdc = '1' generate + bWrSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc1OffsetsInEndpoint); -- 0x0400 + + --vhook_e TdcWrapper WrTdcWrapperx + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a bSyncRegPortIn bWrSyncRegPortIn + --vhook_a bSyncRegPortOut bWrSyncRegPortOut + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a RefClk WrRefClk + --vhook_a rPpsPulse rWrPpsPulse + --vhook_a sPpsPulse sWrPps + --vhook_a rRpTransfer rWrRpTransfer + --vhook_a sSpTransfer sWrSpTransfer + --vhook_a rGatedPulseToPin rWrGatedPulseToPin + --vhook_a sGatedPulseToPin sWrGatedPulseToPin + WrTdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => WrRefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bWrSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bWrSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rWrPpsPulse, --in std_logic + sPpsPulse => sWrPps, --out std_logic + rRpTransfer => rWrRpTransfer, --out std_logic + sSpTransfer => sWrSpTransfer, --out std_logic + rGatedPulseToPin => rWrGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sWrGatedPulseToPin); --inout std_logic + end generate WrTdcGen; + + WrTdcNotGen: if kInclWhiteRabbitTdc = '0' generate + bWrSyncRegPortOut <= kRegPortOutZero; + sWrPps <= '0'; + rWrRpTransfer <= '0'; + sWrSpTransfer <= '0'; + rWrGatedPulseToPin <= '0'; + sWrGatedPulseToPin <= '0'; + end generate WrTdcNotGen; + + -- Mux the output PPS based on the SFP selection bits. Encoding is one-hot, with zero + -- also a valid state. Regardless of whether the user selects SFP0 or SFP1 as the time + -- source, there is only one White Rabbit TDC, so '01' and '10' are equivalent. + -- '00': Use the PPS output from the "regular" TDC. + -- '01': Use the PPS output from the "white rabbit" TDC. + -- '10': Use the PPS output from the "white rabbit" TDC. + PpsOutputMux : process (SampleClk1xOutLcl) + begin + if rising_edge(SampleClk1xOutLcl) then + -- Double-sync the control bits to the Sample Clock domain. + sPpsSfpSel_ms <= aPpsSfpSel; + sPpsSfpSel <= sPpsSfpSel_ms; + + -- OR the control bits together to produce a single override enable for the WR TDC. + sUseWrTdcPps <= to_boolean(sPpsSfpSel(0) or sPpsSfpSel(1)); + + -- Flop the outputs. One flop for the PPS output IOB, the other for use internally. + sPpsInt <= sPpsMuxed; + end if; + end process PpsOutputMux; + + sPpsMuxed <= sWrPps when sUseWrTdcPps else sRegPps; + sPps <= sPpsInt; + sPpsToIob <= sPpsMuxed; -- No added flop here since there's an IOB outside this module. + + + -- Daughterboard Control : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + --vhook_e DaughterboardRegs + --vhook_# Tying this low is safe because the sync reset is used inside DaughterboardRegs. + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bDbRegPortOut + --vhook_a kDbId std_logic_vector(to_unsigned(kDbId,kDbIdSize)) + DaughterboardRegsx: entity work.DaughterboardRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bDbRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + kDbId => std_logic_vector(to_unsigned(kDbId,kDbIdSize)), --in std_logic_vector(15:0) + kSlotId => kSlotId); --in std_logic + + + + +end RTL; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf Binary files differnew file mode 100644 index 000000000..c9df3749b --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd new file mode 100644 index 000000000..bf75e9d0d --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd @@ -0,0 +1,54 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +-- Date : Fri Nov 9 16:19:51 2018 +-- Host : hjimenez running 64-bit major release (build 9200) +-- Command : write_vhdl -mode synth_stub -force -file ./Jesd204bXcvrCore_stub.vhd +-- Design : Jesd204bXcvrCore +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Jesd204bXcvrCore is + Port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aLmkSync : out STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR ( 49 downto 0 ); + bRegPortOutFlat : out STD_LOGIC_VECTOR ( 33 downto 0 ); + CaptureSysRefClk : in STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aAdcRx_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aDacTx_n : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncDacIn_n : in STD_LOGIC; + fAdcDataFlatter : out STD_LOGIC_VECTOR ( 63 downto 0 ); + fDacDataFlatter : in STD_LOGIC_VECTOR ( 63 downto 0 ); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC + ); + +end Jesd204bXcvrCore; + +architecture stub of Jesd204bXcvrCore is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "bBusReset,BusClk,ReliableClk40,FpgaClk1x,FpgaClk2x,bFpgaClksStable,JesdRefClk_p,JesdRefClk_n,bJesdRefClkPresent,aLmkSync,bRegPortInFlat[49:0],bRegPortOutFlat[33:0],CaptureSysRefClk,cSysRefFpgaLvds_p,cSysRefFpgaLvds_n,fSysRef,aAdcRx_p[3:0],aAdcRx_n[3:0],aSyncAdcOut_n,aDacTx_p[3:0],aDacTx_n[3:0],aSyncDacIn_n,fAdcDataFlatter[63:0],fDacDataFlatter[63:0],fAdcDataValid,fDacReadyForInput,aDacSync,aAdcSync"; +begin +end; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd new file mode 100644 index 000000000..8512d133a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd @@ -0,0 +1,302 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgAdcDacInterfaceTypes.vhd +-- Author: National Instruments +-- Original Project: USRP N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- (c) 2018 Copyright National Instruments Corporation +-- All Rights Reserved +-- National Instruments Internal Information +------------------------------------------------------------------------------- +-- +-- Purpose: Contains types for ADC and DAC data so they can more easily be +-- passed through the design. +-- +-- vreview_group JesdCoreN32x +-- vreview_reviewers djepson wfife +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgJesdConfig.all; + + +package PkgAdcDacInterfaceTypes is + + -- Data type for the DACs. + type DacData_t is record + I : std_logic_vector(kDacDataWidth - 1 downto 0); + Q : std_logic_vector(kDacDataWidth - 1 downto 0); + end record; + + -- Data type for the ADCs. + type AdcData_t is record + I : std_logic_vector(kAdcDataWidth - 1 downto 0); + Q : std_logic_vector(kAdcDataWidth - 1 downto 0); + end record; + + -- Type has two bits that correspond to I and Q; example usage: overrange flags. + type IQFlags_t is record + I : std_logic; + Q : std_logic; + end record; + + -- Single data type for all information from the ADCs. + type AdcSamples_t is record + Data : AdcData_t; + Over : IQFlags_t; + CBit1 : IQFlags_t; + end record; + + -- Single data type for all information to the DACs. + type DacSamples_t is record + Data : DacData_t; + end record; + + -- To support multiple data values per clock cycle, these types + -- are arrays of the ADC and DAC data types where the size of the array + -- corresponds to the number of samples per cycle. + type AdcDataAry_t is array (kSamplesPerCycle - 1 downto 0) of AdcSamples_t; + type DacDataAry_t is array (kSamplesPerCycle - 1 downto 0) of DacSamples_t; + + -- Zero/default constant + constant kAdcDataAryZero : AdcDataAry_t := + (others => (Data => (others => (others => '0')), + Over => (others => '0'), + CBit1 => (others => '0')) + ); + + -- Zero/default constant + constant kDacDataAryZero : DacDataAry_t := + (others => (Data => (others => (others => '0'))) + ); + + -- Flattened type that converts the ADC data into std_logic_vector types. This type is + -- not suitable for use in the port maps of components that are presynthesized (into EDF + -- or NGC files) but is useful for passing data to the top level. + type AdcDataAryFlat_t is record + DataI : std_logic_vector(kSamplesPerCycle*kAdcDataWidth - 1 downto 0); + DataQ : std_logic_vector(kSamplesPerCycle*kAdcDataWidth - 1 downto 0); + OverI : std_logic_vector(kSamplesPerCycle - 1 downto 0); + OverQ : std_logic_vector(kSamplesPerCycle - 1 downto 0); + CBit1I : std_logic_vector(kSamplesPerCycle - 1 downto 0); + CBit1Q : std_logic_vector(kSamplesPerCycle - 1 downto 0); + end record; + + -- Fully flattened ADC data for passing into and out of presynthesized components. + subtype AdcDataAryFlatter_t is std_logic_vector(2*(kSamplesPerCycle*(kAdcDataWidth + 2)) - 1 downto 0); + + -- Flattened type that converts the DAC data into std_logic_vector types. This type is + -- not suitable for use in the port maps of components that are presynthesized (into EDF + -- or NGC files) but is useful for passing data from the top level. + type DacDataAryFlat_t is record + DataI : std_logic_vector(kSamplesPerCycle*kDacDataWidth - 1 downto 0); + DataQ : std_logic_vector(kSamplesPerCycle*kDacDataWidth - 1 downto 0); + end record; + + -- Fully flattened DAC data for passing into and out of presynthesized components. + subtype DacDataAryFlatter_t is std_logic_vector(2*(kSamplesPerCycle*kDacDataWidth) - 1 downto 0); + + -- Function to convert types defined above for the ADC data + function Flatten (AdcData : AdcDataAry_t) return AdcDataAryFlat_t; + function Flatten (AdcData : AdcDataAryFlat_t) return AdcDataAryFlatter_t; + function Flatten (AdcData : AdcDataAry_t) return AdcDataAryFlatter_t; + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAryFlat_t; + function Unflatten(AdcData : AdcDataAryFlat_t) return AdcDataAry_t; + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAry_t; + + + -- Function to convert types defined above for the DAC data + function Flatten (DacData : DacDataAry_t) return DacDataAryFlat_t; + function Flatten (DacData : DacDataAryFlat_t) return DacDataAryFlatter_t; + function Flatten (DacData : DacDataAry_t) return DacDataAryFlatter_t; + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAryFlat_t; + function UnFlatten(DacData : DacDataAryFlat_t) return DacDataAry_t; + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAry_t; + + +end package PkgAdcDacInterfaceTypes; + + +package body PkgAdcDacInterfaceTypes is + + -- Flattens AdcDataAry_t to AdcDataAryFlat_t + function Flatten(AdcData : AdcDataAry_t) return AdcDataAryFlat_t + is + variable ReturnVar : AdcDataAryFlat_t; + begin + ReturnVar := (DataI => (others => '0'), -- Note (others => (others => '0')) does not work here + DataQ => (others => '0'), -- since DataX and OverX/CBit1X are of different lengths (ModelSim error) + OverI => (others => '0'), + OverQ => (others => '0'), + CBit1I => (others => '0'), + CBit1Q => (others => '0')); + + -- The upstream logic puts the 0th element of an array in the MSBs of its data word + for i in 0 to kSamplesPerCycle - 1 loop + ReturnVar.DataI((kSamplesPerCycle - i)*kAdcDataWidth - 1 downto (kSamplesPerCycle - 1 - i)*kAdcDataWidth) := AdcData(i).Data.I; -- Input Data 0 to MSB + ReturnVar.DataQ((kSamplesPerCycle - i)*kAdcDataWidth - 1 downto (kSamplesPerCycle - 1 - i)*kAdcDataWidth) := AdcData(i).Data.Q; + ReturnVar.OverI (kSamplesPerCycle - 1 - i) := AdcData(i).Over.I; -- Input Data 0 to MSB + ReturnVar.OverQ (kSamplesPerCycle - 1 - i) := AdcData(i).Over.Q; + ReturnVar.CBit1I(kSamplesPerCycle - 1 - i) := AdcData(i).CBit1.I; + ReturnVar.CBit1Q(kSamplesPerCycle - 1 - i) := AdcData(i).CBit1.Q; + end loop; + + return ReturnVar; + end function Flatten; + + + -- UnFlattens AdcDataAryFlat_t to AdcDataAry_t + function Unflatten(AdcData : AdcDataAryFlat_t) return AdcDataAry_t + is + variable ReturnVar : AdcDataAry_t; + begin + ReturnVar := (others => (Data => (others => (others => '0')), Over => (others => '0'), CBit1 => (others => '0'))); + for i in 0 to kSamplesPerCycle - 1 loop + -- MSB of flattened word = 0th element of ADC data array - this corresponds to how TheWindow + -- expects data arrays to be transferred. + ReturnVar(kSamplesPerCycle - 1 - i).Data.I := AdcData.DataI((i+1)*kAdcDataWidth - 1 downto i*kAdcDataWidth); + ReturnVar(kSamplesPerCycle - 1 - i).Data.Q := AdcData.DataQ((i+1)*kAdcDataWidth - 1 downto i*kAdcDataWidth); + ReturnVar(kSamplesPerCycle - 1 - i).Over.I := AdcData.OverI(i); + ReturnVar(kSamplesPerCycle - 1 - i).Over.Q := AdcData.OverQ(i); + ReturnVar(kSamplesPerCycle - 1 - i).CBit1.I := AdcData.CBit1I(i); + ReturnVar(kSamplesPerCycle - 1 - i).CBit1.Q := AdcData.CBit1Q(i); + end loop; + return ReturnVar; + end function Unflatten; + + + + + -- Flattens AdcDataAryFlat_t to AdcDataAryFlatter_t + function Flatten(AdcData : AdcDataAryFlat_t) return AdcDataAryFlatter_t + is + variable ReturnVar : AdcDataAryFlatter_t; + begin + ReturnVar := AdcData.OverQ & AdcData.CBit1Q & AdcData.OverI & AdcData.CBit1I & AdcData.DataQ & AdcData.DataI; + return ReturnVar; + end function Flatten; + + -- UnFlattens AdcDataAryFlatter_t to AdcDataAryFlat_t + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAryFlat_t + is + variable ReturnVar : AdcDataAryFlat_t; + begin + ReturnVar.DataI := AdcData(1*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle - 1 downto 0*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.DataQ := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle - 1 downto 1*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.CBit1I := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 1*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.OverI := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 2*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 1*kSamplesPerCycle); + ReturnVar.CBit1Q := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 3*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 2*kSamplesPerCycle); + ReturnVar.OverQ := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 4*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 3*kSamplesPerCycle); + return ReturnVar; + end function Unflatten; + + + -- Flattens AdcDataAry_t to AdcDataAryFlatter_t + function Flatten(AdcData : AdcDataAry_t) return AdcDataAryFlatter_t + is + variable TempVar : AdcDataAryFlat_t; + variable ReturnVar : AdcDataAryFlatter_t; + begin + TempVar := Flatten(AdcData); + ReturnVar := Flatten(TempVar); + return ReturnVar; + end function Flatten; + + -- UnFlattens AdcDataAryFlatter_t to AdcDataAry_t + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAry_t + is + variable TempVar : AdcDataAryFlat_t; + variable ReturnVar : AdcDataAry_t; + begin + TempVar := Unflatten(AdcData); + ReturnVar := Unflatten(TempVar); + return ReturnVar; + end function Unflatten; + + + + -- Flattens DacDataAry_t to DacDataAryFlat_t + function Flatten(DacData : DacDataAry_t) return DacDataAryFlat_t + is + variable ReturnVar : DacDataAryFlat_t; + begin + ReturnVar := (others => (others => '0')); + for i in 0 to kSamplesPerCycle - 1 loop + -- MSB of flattened word = 0th element of ADC data array - this corresponds to how TheWindow + -- expects data arrays to be transferred. + ReturnVar.DataI((i+1)*kDacDataWidth - 1 downto i*kDacDataWidth) := DacData(kSamplesPerCycle - 1 - i).Data.I; + ReturnVar.DataQ((i+1)*kDacDataWidth - 1 downto i*kDacDataWidth) := DacData(kSamplesPerCycle - 1 - i).Data.Q; + end loop; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataAryFlat_t to DacDataAry_t + function UnFlatten(DacData : DacDataAryFlat_t) return DacDataAry_t + is + variable ReturnVar : DacDataAry_t; + begin + ReturnVar := (others => (Data => (others => (others => '0')))); + + -- The upstream logic puts the 0th element of an array in the MSBs of its data word + for i in 0 to kSamplesPerCycle - 1 loop + ReturnVar(kSamplesPerCycle - 1 - i).Data.I := DacData.DataI(kDacDataWidth*(i+1) - 1 downto kDacDataWidth*i); + ReturnVar(kSamplesPerCycle - 1 - i).Data.Q := DacData.DataQ(kDacDataWidth*(i+1) - 1 downto kDacDataWidth*i); + end loop; + + return ReturnVar; + end function UnFlatten; + + + + -- Flattens DacDataAryFlat_t to DacDataAryFlatter_t + function Flatten(DacData : DacDataAryFlat_t) return DacDataAryFlatter_t + is + variable ReturnVar : DacDataAryFlatter_t; + begin + ReturnVar := DacData.DataQ & DacData.DataI; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataAryFlatter_t to DacDataAryFlat_t + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAryFlat_t + is + variable ReturnVar : DacDataAryFlat_t; + begin + ReturnVar.DataI := DacData(1*kSamplesPerCycle*kDacDataWidth - 1 downto 0*kSamplesPerCycle*kDacDataWidth); + ReturnVar.DataQ := DacData(2*kSamplesPerCycle*kDacDataWidth - 1 downto 1*kSamplesPerCycle*kDacDataWidth); + return ReturnVar; + end function Unflatten; + + + -- Flattens DacDataAry_t to DacDataAryFlatter_t + function Flatten(DacData : DacDataAry_t) return DacDataAryFlatter_t + is + variable TempVar : DacDataAryFlat_t; + variable ReturnVar : DacDataAryFlatter_t; + begin + TempVar := Flatten(DacData); + ReturnVar := Flatten(TempVar); + return ReturnVar; + end function Flatten; + + -- UnFlattens DacDataAryFlatter_t to DacDataAry_t + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAry_t + is + variable TempVar : DacDataAryFlat_t; + variable ReturnVar : DacDataAry_t; + begin + TempVar := Unflatten(DacData); + ReturnVar := Unflatten(TempVar); + return ReturnVar; + end function Unflatten; + + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd new file mode 100644 index 000000000..03b95c100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgClockingRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgClockingRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- RadioClkMmcm : 0x20 (ClockingRegs.vhd) + -- PhaseShiftControl : 0x24 (ClockingRegs.vhd) + -- RadioClkEnables : 0x28 (ClockingRegs.vhd) + -- MgtRefClkStatus : 0x30 (ClockingRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group ClockingRegs +--=============================================================================== + + -- RadioClkMmcm Register (from ClockingRegs.vhd) + constant kRadioClkMmcm : integer := 16#20#; -- Register Offset + constant kRadioClkMmcmSize: integer := 32; -- register width in bits + constant kRadioClkMmcmMask : std_logic_vector(31 downto 0) := X"00000013"; + constant kRadioClkMmcmResetSetSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSetMsb : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSet : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetClearSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClearMsb : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClear : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmLockedSize : integer := 1; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLockedMsb : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLocked : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + + -- PhaseShiftControl Register (from ClockingRegs.vhd) + constant kPhaseShiftControl : integer := 16#24#; -- Register Offset + constant kPhaseShiftControlSize: integer := 32; -- register width in bits + constant kPhaseShiftControlMask : std_logic_vector(31 downto 0) := X"10010011"; + constant kPsIncSize : integer := 1; --PhaseShiftControl:PsInc + constant kPsIncMsb : integer := 0; --PhaseShiftControl:PsInc + constant kPsInc : integer := 0; --PhaseShiftControl:PsInc + constant kPsDecSize : integer := 1; --PhaseShiftControl:PsDec + constant kPsDecMsb : integer := 4; --PhaseShiftControl:PsDec + constant kPsDec : integer := 4; --PhaseShiftControl:PsDec + constant kPsEnabledForFdbClkSize : integer := 1; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClkMsb : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClk : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsDoneSize : integer := 1; --PhaseShiftControl:PsDone + constant kPsDoneMsb : integer := 28; --PhaseShiftControl:PsDone + constant kPsDone : integer := 28; --PhaseShiftControl:PsDone + + -- RadioClkEnables Register (from ClockingRegs.vhd) + constant kRadioClkEnables : integer := 16#28#; -- Register Offset + constant kRadioClkEnablesSize: integer := 32; -- register width in bits + constant kRadioClkEnablesMask : std_logic_vector(31 downto 0) := X"00000111"; + constant kRadioClk1xEnabledSize : integer := 1; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabledMsb : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabled : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk2xEnabledSize : integer := 1; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabledMsb : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabled : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk3xEnabledSize : integer := 1; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabledMsb : integer := 8; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabled : integer := 8; --RadioClkEnables:RadioClk3xEnabled + + -- MgtRefClkStatus Register (from ClockingRegs.vhd) + constant kMgtRefClkStatus : integer := 16#30#; -- Register Offset + constant kMgtRefClkStatusSize: integer := 32; -- register width in bits + constant kMgtRefClkStatusMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kJesdRefClkPresentSize : integer := 1; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresentMsb : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresent : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + +end package; + +package body PkgClockingRegMap is + + -- function kRadioClkMmcmRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPhaseShiftControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRadioClkEnablesRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMgtRefClkStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd new file mode 100644 index 000000000..06708cde3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd @@ -0,0 +1,56 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgDaughterboardRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgDaughterboardRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- DaughterboardId : 0x630 (DaughterboardRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group StaticControl +--=============================================================================== + + -- DaughterboardId Register (from DaughterboardRegs.vhd) + constant kDaughterboardId : integer := 16#630#; -- Register Offset + constant kDaughterboardIdSize: integer := 32; -- register width in bits + constant kDaughterboardIdMask : std_logic_vector(31 downto 0) := X"0001ffff"; + constant kDbIdValSize : integer := 16; --DaughterboardId:DbIdVal + constant kDbIdValMsb : integer := 15; --DaughterboardId:DbIdVal + constant kDbIdVal : integer := 0; --DaughterboardId:DbIdVal + constant kSlotIdValSize : integer := 1; --DaughterboardId:SlotIdVal + constant kSlotIdValMsb : integer := 16; --DaughterboardId:SlotIdVal + constant kSlotIdVal : integer := 16; --DaughterboardId:SlotIdVal + +end package; + +package body PkgDaughterboardRegMap is + + -- function kDaughterboardIdRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd new file mode 100644 index 000000000..4913b03fc --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd @@ -0,0 +1,165 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgJesdConfig.vhd +-- Author: National Instruments +-- Original Project: N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: JESD204B setup constants and functions. These constants are shared +-- between RX and TX JESD cores. +-- +-- vreview_group JesdCoreN32x +-- vreview_reviewers djepson wfife +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgJesdConfig is + + -- "JESD" in ASCII - with the core number 0 or 1 on the LSb. + constant kJesdSignature : std_logic_vector(31 downto 0) := x"4a455344"; + + -- Register endpoints + constant kJesdDrpRegsInEndpoint : RegOffset_t := (kOffset => 16#0800#, -- 0x2800 to + kWidth => 16#0800#); -- 0x2FFF + + -- Selects the UsrClk2 for the transceivers. For 64-bit wide transceivers, the + -- UsrClk = 2*UserClk2 frequency. For 32-bit wide transceivers, UsrClk = UserClk2 + -- frequency. This is a generalization, the clock ratio should be confirmed based on + -- the transceiver configuration. + -- The N310 transceivers use the single rate reference, hence = false. + constant kDoubleRateUsrClk : boolean := false; + + -- For the N32x, all lanes are in one quad and we use the QPLL. + constant kJesdUseQpll : boolean := true; + + constant kAdcDataWidth : integer := 14; -- ADC data width in bits + constant kDacDataWidth : integer := 16; -- DAC data width in bits + constant kSamplesPerCycle : integer := 2; -- Number of samples per SampleClk1x + + constant kGtxDrpAddrWidth : natural := 9; + constant kGtxAddrLsbPosition : natural := 2; + constant kQpllDrpAddrWidth : natural := 8; + constant kGtxDrpDataWidth : natural := 16; + + -- Max supported number of lanes + constant kMaxNumLanes : natural := 4; + -- Max supported number of quads (normally there is 1 quad per 4 lanes but disconnect + -- the definitions to allow quad sharing) + constant kMaxNumQuads : natural := 1; + + -- Rhodium: + -- JESD shared setup - LMFS = 4211, HD = 1 (Samples are split across multiple lanes). + constant kNumLanes : natural := 4; -- L + constant kNumConvs : positive := 2; -- M + constant kOctetsPerFrame : natural := 1; -- F + constant kDacJesdSamplesPerCycle : integer := 1; -- S + constant kOctetsPerLane : natural := 2; -- MGT data is kOctetsPerLane*8 = 16 bits wide + constant kNumQuads : natural := kNumLanes / 4; -- 4 lanes per quad + constant kHighDensity : boolean := true; -- HD + constant kConvResBits : positive := kDacDataWidth; -- Converter resolution in bits + constant kConvSampleBits : positive := 16; -- Sample Length in bits + constant kInitLaneAlignCnt : positive := 4; + constant kFramesPerMulti : natural := 24; -- K + + -- Rhodium: + -- The converters are running at 400/491.52/500 MSPS (DeviceClk), and the sampling + -- clock at the FPGA (UserClk) is 200/245.76/250 MHz; so UsrClk = (DeviceClk / 2). + -- The frame rate = DeviceClk, and the Multiframe rate = (frame rate / kFramesPerMulti) + -- Thus, kUserClksPerMulti = (UsrClk / Multiframe rate) + -- = (UsrClk / (DeviceClk / kFramesPerMulti)) + -- since UsrClk = DeviceClk / 2 then, + -- kUserClksPerMulti = ((DeviceClk / 2) / (DeviceClk / kFramesPerMulti)) + -- therefore, + -- kUserClksPerMulti = kFramesPerMulti / 2 + constant kUserClksPerMulti : integer := kFramesPerMulti / 2; + + + type NaturalVector is array ( natural range <>) of natural; + + -- The PCB connections are are passed trough, any swapping is handled somewhere else. + -- + -- Transceiver MGT Channel ADC Lane DAC Lane + -- *********** *********** ******** ******** + -- GT0: X0Y8 0 0 0 + -- GT1: X0Y9 1 1 1 + -- GT2: X0Y10 2 2 2 + -- GT3: X0Y11 3 3 3 + constant kRxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => ADC (in above table) + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kTxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => DAC lane + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kLaneToQuadMap : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- All lanes are in one quad + 0 => 0, + 1 => 0, + 2 => 0, + 3 => 0 + ); + + + -- The master transceiver channel for channel bonding. E(kMasterBondingChannel) + -- must have the highest value decrementing to b"000" for that last channels to bond. + constant kMasterBondingChannel : integer := 1; + + -- Channel bonding occurs when a master detects a K-char sequence and aligns its + -- internal FIFO to the start of this sequence. A signal is then generated to other + -- slave transceivers that cause them to bond to the sequence - this bonding signal is + -- cascaded from master to slave to slave to slave, etc where each slave must know how + -- many levels to the master there are. The last slave to bond must be at level b"000" + -- and the master is at the highest level; the number of levels in the sequence is + -- governed by the size of the transceiver FIFO (see the Xilinx user guides for more + -- information). + type BondLevels_t is array(0 to kNumLanes - 1) of std_logic_vector(2 downto 0); + constant kBondLevel : BondLevels_t := ( + 0 => b"000", -- Control from 1 + 1 => b"001", -- Master + 2 => b"000", -- Control from 1 + 3 => b"000" -- Control from 1 + ); + + + -- User Rx Data + -- ADC Word data width: 14 sample bits + 2 tails bits + constant kAdcWordWidth : integer := 16; + subtype AdcWord_t is std_logic_vector(kAdcWordWidth - 1 downto 0); + type AdcWordArray_t is array(kSamplesPerCycle*2 - 1 downto 0) of AdcWord_t; -- The *2 is because there are two samples (I and Q) per "sample" + + -- Constants to specify the contents of the AdcWord_t vector. + constant kAdcWordDataMsb : integer := 15; + constant kAdcWordDataLsb : integer := 2; + constant kAdcWordOver : integer := 1; + constant kAdcWordCBit1 : integer := 0; + + + -- Option to pipeline stages to improve timing, if needed + constant kPipelineDetectCharsStage : boolean := false; + constant kPipelineCharReplStage : boolean := false; + +end package; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd new file mode 100644 index 000000000..801a46d15 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd @@ -0,0 +1,62 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgRhPersonality.vhd +-- Author: National Instruments +-- Original Project: N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: This package contains constants and helpful functions that enable +-- the FPGA to be compiled with different features. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgRhPersonality is + + -- Rhodium daughterboard ID definition. + constant kDbId : integer := 16#152#; + constant kDbIdSize : integer := 16; + + + -- RegPort Address Definitions : ------------------------------------------------------ + -- + -- DB Regs ... + -- + -- Clocking Offset: 0x 000 Width: 0x 200 + -- Tdco0 Offset: 0x 200 Width: 0x 200 + -- Tdco1 Offset: 0x 400 Width: 0x 200 + -- Daughterboard Ctrl Offset: 0x 600 Width: 0x 200 + -- Total: 0x2000 + -- JESD 2x - A Offset: 0x2000 Width: 0x1000 + -- JESD 2x - B Offset: 0x3000 Width: 0x1000 + -- Total: 0x4000 + -- Total: 0x8000 for two DBs + -- ------------------------------------------------------------------------------------ + + -- A single RegPort runs to the JESD204B Core. + constant kJesdRegGroupInDbRegs : RegOffset_t := (kOffset => 16#2000#, -- 0x2000 to + kWidth => 16#1000#); -- 0x2FFF + + -- DB Regs : -------------------------------------------------------------------------- + constant kClockingOffsetInEndpoint : RegOffset_t := (kOffset => 16#0000#, -- 0x0000 to + kWidth => 16#0200#); -- 0x01FF + constant kTdc0OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0200#, -- 0x0200 to + kWidth => 16#0200#); -- 0x03FF + constant kTdc1OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0400#, -- 0x0400 to + kWidth => 16#0200#); -- 0x05FF + constant kDaughterboardOffsetInEndpoint : RegOffset_t := (kOffset => 16#0600#, -- 0x0600 to + kWidth => 16#0200#); -- 0x07FF + +end package PkgRhPersonality; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd new file mode 100644 index 000000000..69a15d49a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd @@ -0,0 +1,305 @@ +------------------------------------------------------------------------------- +-- +-- File: RadioClocking.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 February 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Instantiates a MMCM to produce 1x, 2x, and 3x versions of the Radio Clock +-- coming from the FPGA input pin. Handles all the buffering for the input clock. +-- Additionally allows the clocks to be turned on and off, and phase shifted. +-- +-- NOTE: This module hard-codes the MMCM settings for a SPECIFIC clock rate! +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library unisim; + use unisim.vcomponents.all; + + +entity RadioClocking is + port ( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + + -- Should be a always-on clock + BusClk : in std_logic; + + -- Sync reset to the RadioClkMmcm. + bRadioClkMmcmReset : in std_logic; + + -- Locked indication from the RadioClkMmcm in BusClk and aReset domains. + bRadioClksValid : out std_logic; + + bRadioClk1xEnabled : in std_logic; + bRadioClk2xEnabled : in std_logic; + bRadioClk3xEnabled : in std_logic; + + -- Phase shift interface for the RadioClkMmcm. PsClk must be <= 200 MHz. + pPsInc : in std_logic; + pPsEn : in std_logic; + PsClk : in std_logic; + pPsDone : out std_logic; + + -- Straight from pins. Buffer included in here. + FpgaClk_n : in std_logic; + FpgaClk_p : in std_logic; + + RadioClk1x : out std_logic; + RadioClk2x : out std_logic; + RadioClk3x : out std_logic + + ); +end RadioClocking; + + +architecture rtl of RadioClocking is + + --vhook_sigstart + signal RadioClk1xLcl: std_logic; + signal RadioClk1xPll: std_logic; + signal RadioClk2xLcl: std_logic; + signal RadioClk2xPll: std_logic; + signal RadioClk3xLcl: std_logic; + signal RadioClk3xPll: std_logic; + --vhook_sigend + + signal RadioClkMmcmFeedbackIn, + RadioClkMmcmFeedbackOut, + FpgaClkSE, + aRadioClkMmcmLocked : std_logic; + + signal bRadioClkMmcmLocked_ms, + bRadioClkMmcmLocked, + bEnableRadioClkBufgOutputs, + bEnableRadioClk1xBufgOutput, + bEnableRadioClk2xBufgOutput, + bEnableRadioClk3xBufgOutput : std_logic := '0'; + + signal aRadioClkMmcmResetInternal : std_logic := '1'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClkMmcmLocked_ms : signal is "true"; + attribute ASYNC_REG of bRadioClkMmcmLocked : signal is "true"; + +begin + + -- Radio Clock Buffering : ------------------------------------------------------------ + -- + -- ------------------------------------------------------------------------------------ + --vhook_i IBUFDS FpgaClkIbufg hidegeneric=true + --vhook_a I FpgaClk_p + --vhook_a IB FpgaClk_n + --vhook_a O FpgaClkSE + FpgaClkIbufg: IBUFDS + port map ( + O => FpgaClkSE, --out std_ulogic + I => FpgaClk_p, --in std_ulogic + IB => FpgaClk_n); --in std_ulogic + + + ResetDelay : process(aReset, BusClk) + begin + if aReset then + aRadioClkMmcmResetInternal <= '1'; + elsif rising_edge(BusClk) then + if bReset then + aRadioClkMmcmResetInternal <= '1'; + else + -- Delay by 1 to allow the BUFGs to turn off before the MMCM is reset. + aRadioClkMmcmResetInternal <= bRadioClkMmcmReset; + end if; + end if; + end process ResetDelay; + + + RadioClkMmcm: MMCME2_ADV + generic map( + COMPENSATION => "ZHOLD", + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 4.000, -- Feedback + CLKOUT0_DIVIDE_F => 4.000, -- Data Clock 1x, RadioClk1xPll + CLKOUT1_DIVIDE => 2, -- Data Clock 2x, RadioClk2xPll + CLKOUT2_DIVIDE => 2, -- Data Clock 3x, RadioClk3xPll + CLKOUT3_DIVIDE => 1, -- unused + CLKOUT4_DIVIDE => 1, -- unused + CLKOUT5_DIVIDE => 1, -- unused + CLKOUT6_DIVIDE => 1, -- unused + CLKFBOUT_PHASE => 0.000, -- Feedback + CLKOUT0_PHASE => 0.000, -- Data Clock 1x + CLKOUT1_PHASE => 0.000, -- Data Clock 2x + CLKOUT2_PHASE => 0.000, -- Data Clock 3x + CLKOUT3_PHASE => 0.000, -- unused + CLKOUT4_PHASE => 0.000, -- unused + CLKOUT5_PHASE => 0.000, -- unused + CLKOUT6_PHASE => 0.000, -- unused + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT4_DUTY_CYCLE => 0.500, + CLKOUT5_DUTY_CYCLE => 0.500, + CLKOUT6_DUTY_CYCLE => 0.500, + DIVCLK_DIVIDE => 1, + REF_JITTER1 => 0.010, + CLKIN1_PERIOD => 4.069, -- 245.76 MHz max + CLKFBOUT_USE_FINE_PS => true, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_USE_FINE_PS => false, + STARTUP_WAIT => false, + CLKOUT4_CASCADE => false) + port map ( + CLKINSEL => '1', + CLKIN1 => FpgaClkSE, + CLKIN2 => '0', + CLKFBIN => RadioClkMmcmFeedbackIn, + RST => aRadioClkMmcmResetInternal, + PWRDWN => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DWE => '0', + DEN => '0', + DCLK => '0', + DO => open, + DRDY => open, + PSINCDEC => pPsInc, + PSEN => pPsEn, + PSCLK => PsClk, + PSDONE => pPsDone, + CLKOUT0 => RadioClk1xPll, + CLKOUT0B => open, + CLKOUT1 => RadioClk2xPll, + CLKOUT1B => open, + CLKOUT2 => RadioClk3xPll, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBOUT => RadioClkMmcmFeedbackOut, + CLKFBOUTB => open, + LOCKED => aRadioClkMmcmLocked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open); + + RadioClkMmcmFeedbackBufg: BUFG + port map ( + I => RadioClkMmcmFeedbackOut, + O => RadioClkMmcmFeedbackIn + ); + + + -- Only enable the WRAPBUFGs when the MMCM is locked. If the MMCM is ever placed in + -- reset, we turn off the clocks one cycle before the asynchronous version + -- (aRadioClkMmcmResetInternal) reaches the MMCM inputs in order to prevent + -- output glitches. + CombineEnablesForBuffers : process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + elsif rising_edge(BusClk) then + if bReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + else + bRadioClkMmcmLocked_ms <= aRadioClkMmcmLocked; + bRadioClkMmcmLocked <= bRadioClkMmcmLocked_ms; + + bEnableRadioClkBufgOutputs <= bRadioClkMmcmLocked and + not bRadioClkMmcmReset; + bEnableRadioClk1xBufgOutput <= bRadioClk1xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk2xBufgOutput <= bRadioClk2xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk3xBufgOutput <= bRadioClk3xEnabled and bEnableRadioClkBufgOutputs; + end if; + end if; + end process CombineEnablesForBuffers; + + bRadioClksValid <= bEnableRadioClkBufgOutputs; + + --vhook_e WrapBufg RadioClk1xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk1xPll + --vhook_a aCe bEnableRadioClk1xBufgOutput + --vhook_a ClkOut RadioClk1xLcl + RadioClk1xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk1xPll, --in std_logic + aCe => bEnableRadioClk1xBufgOutput, --in std_logic + ClkOut => RadioClk1xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk2xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk2xPll + --vhook_a aCe bEnableRadioClk2xBufgOutput + --vhook_a ClkOut RadioClk2xLcl + RadioClk2xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk2xPll, --in std_logic + aCe => bEnableRadioClk2xBufgOutput, --in std_logic + ClkOut => RadioClk2xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk3xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk3xPll + --vhook_a aCe bEnableRadioClk3xBufgOutput + --vhook_a ClkOut RadioClk3xLcl + RadioClk3xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk3xPll, --in std_logic + aCe => bEnableRadioClk3xBufgOutput, --in std_logic + ClkOut => RadioClk3xLcl); --out std_logic + + + -- Assign outputs from locals. + RadioClk1x <= RadioClk1xLcl; + RadioClk2x <= RadioClk2xLcl; + RadioClk3x <= RadioClk3xLcl; + + + +end rtl; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc new file mode 100644 index 000000000..b67269cd9 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc @@ -0,0 +1,280 @@ +## TDC : ################################################################################ +## Bank 10, 2.5V (DB A) +######################################################################################### + +set_property PACKAGE_PIN AB15 [get_ports {UNUSED_PIN_TDCA_0}] +set_property PACKAGE_PIN AB14 [get_ports {UNUSED_PIN_TDCA_1}] +set_property PACKAGE_PIN AB16 [get_ports {UNUSED_PIN_TDCA_2}] +set_property PACKAGE_PIN AB17 [get_ports {UNUSED_PIN_TDCA_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCA_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCA_*}] + + +## TDC : ################################################################################ +## Bank 11, 2.5V (DB B) +######################################################################################### + +set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}] +set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}] +set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}] +set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}] + + +## USRP IO A : ########################################################################## +# DBA +######################################################################################### + +set_property PACKAGE_PIN G1 [get_ports DBA_MODULE_PWR_ENABLE] +set_property PACKAGE_PIN E5 [get_ports DBA_RF_PWR_ENABLE] + +set_property PACKAGE_PIN AF14 [get_ports DBA_FPGA_CLK_P] +set_property PACKAGE_PIN AG14 [get_ports DBA_FPGA_CLK_N] + +set_property PACKAGE_PIN N8 [get_ports DBA_MGTCLK_P] +set_property PACKAGE_PIN N7 [get_ports DBA_MGTCLK_N] + +set_property PACKAGE_PIN AG17 [get_ports DBA_FPGA_SYSREF_P] +set_property PACKAGE_PIN AG16 [get_ports DBA_FPGA_SYSREF_N] +set_property IOB TRUE [get_ports DBA_FPGA_SYSREF_*] + + +# set_property PACKAGE_PIN AD10 [get_ports NET2CLK_P] +# set_property PACKAGE_PIN AD9 [get_ports NET2CLK_N] + +set_property PACKAGE_PIN C2 [get_ports DBA_CPLD_PL_SPI_SCLK] +set_property PACKAGE_PIN B1 [get_ports DBA_TXLO_SPI_CS_B]; # DBA_CPLD_PL_SPI_LE +set_property PACKAGE_PIN B2 [get_ports DBA_CPLD_PL_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[0] +set_property PACKAGE_PIN F4 [get_ports DBA_RXLO_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[1] +set_property PACKAGE_PIN F3 [get_ports DBA_LODIS_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[2] +set_property PACKAGE_PIN C1 [get_ports DBA_CPLD_PL_SPI_MISO] +set_property PACKAGE_PIN A3 [get_ports DBA_CPLD_PL_SPI_MOSI] + +set_property PACKAGE_PIN AC16 [get_ports DBA_CPLD_PS_SPI_SCLK]; # DBA_CPLD_PS_SPI_ADDR[0] +set_property PACKAGE_PIN AE15 [get_ports DBA_CPLD_PS_SPI_CS_B]; # DBA_CPLD_PS_SPI_ADDR[1] +set_property PACKAGE_PIN AE16 [get_ports DBA_PHDAC_SPI_CS_B]; # DBA_CPLD_PS_SPI_LE +set_property PACKAGE_PIN AF17 [get_ports DBA_CLKDIS_SPI_CS_B] +set_property PACKAGE_PIN AK16 [get_ports DBA_ADC_SPI_CS_B]; # DBA_CPLD_UNUSED[12] +set_property PACKAGE_PIN AJ16 [get_ports DBA_DAC_SPI_CS_B]; # DBA_CPLD_UNUSED[13] +set_property PACKAGE_PIN AC17 [get_ports DBA_CPLD_PS_SPI_MISO] +set_property PACKAGE_PIN AF18 [get_ports DBA_CPLD_PS_SPI_MOSI] + +set_property PACKAGE_PIN AH13 [get_ports DBA_CPLD_JTAG_TDI] +set_property PACKAGE_PIN AH14 [get_ports DBA_CPLD_JTAG_TDO] +set_property PACKAGE_PIN AE13 [get_ports DBA_CPLD_JTAG_TMS] +set_property PACKAGE_PIN AF13 [get_ports DBA_CPLD_JTAG_TCK] + +set_property PACKAGE_PIN E1 [get_ports DBA_CLKDIST_SYNC] + +set_property PACKAGE_PIN A2 [get_ports DBA_ATR_TX] +set_property PACKAGE_PIN E3 [get_ports DBA_ATR_RX] + +set_property PACKAGE_PIN E2 [get_ports DBA_TXRX_SW_CTRL_1] +set_property PACKAGE_PIN F5 [get_ports DBA_TXRX_SW_CTRL_2] + +set_property PACKAGE_PIN AE12 [get_ports DBA_ADC_SYNCB_P] +set_property PACKAGE_PIN AF12 [get_ports DBA_ADC_SYNCB_N] +set_property PACKAGE_PIN AD14 [get_ports DBA_DAC_SYNCB_P]; # Layout swapped, RTL is negated. +set_property PACKAGE_PIN AD13 [get_ports DBA_DAC_SYNCB_N]; # Layout swapped, RTL is negated. + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the AD9695 and the DAC37J82 crossbar settings. +set_property PACKAGE_PIN V6 [get_ports DBA_RX_P[0]] +set_property PACKAGE_PIN V5 [get_ports DBA_RX_N[0]] +set_property PACKAGE_PIN U4 [get_ports DBA_RX_P[1]] +set_property PACKAGE_PIN U3 [get_ports DBA_RX_N[1]] +set_property PACKAGE_PIN T6 [get_ports DBA_RX_P[2]] +set_property PACKAGE_PIN T5 [get_ports DBA_RX_N[2]] +set_property PACKAGE_PIN P6 [get_ports DBA_RX_P[3]] +set_property PACKAGE_PIN P5 [get_ports DBA_RX_N[3]] + +set_property PACKAGE_PIN T2 [get_ports DBA_TX_P[0]] +set_property PACKAGE_PIN T1 [get_ports DBA_TX_N[0]] +set_property PACKAGE_PIN R4 [get_ports DBA_TX_P[1]] +set_property PACKAGE_PIN R3 [get_ports DBA_TX_N[1]] +set_property PACKAGE_PIN P2 [get_ports DBA_TX_P[2]] +set_property PACKAGE_PIN P1 [get_ports DBA_TX_N[2]] +set_property PACKAGE_PIN N4 [get_ports DBA_TX_P[3]] +set_property PACKAGE_PIN N3 [get_ports DBA_TX_N[3]] + +set_property PACKAGE_PIN AG12 [get_ports DBA_LED_RX] +set_property PACKAGE_PIN AH12 [get_ports DBA_LED_RX2] +set_property PACKAGE_PIN AJ13 [get_ports DBA_LED_TX] + +# Possibly need to be used. Connected to CPLD. +# set_property PACKAGE_PIN C4 [get_ports DBA_CPLD_UNUSED[0]] +# set_property PACKAGE_PIN C3 [get_ports DBA_CPLD_UNUSED[1]] +# set_property PACKAGE_PIN K1 [get_ports DBA_CPLD_UNUSED[2]] +# set_property PACKAGE_PIN L1 [get_ports DBA_CPLD_UNUSED[3]] +# set_property PACKAGE_PIN D1 [get_ports DBA_CPLD_UNUSED[4]] +# set_property PACKAGE_PIN AE17 [get_ports DBA_CPLD_UNUSED[5]] +# set_property PACKAGE_PIN AE18 [get_ports DBA_CPLD_UNUSED[6]] +# set_property PACKAGE_PIN AB12 [get_ports DBA_CPLD_UNUSED[7]] +# set_property PACKAGE_PIN AC12 [get_ports DBA_CPLD_UNUSED[8]] +# set_property PACKAGE_PIN AG17 [get_ports DBA_CPLD_UNUSED[9]] +# set_property PACKAGE_PIN AK12 [get_ports DBA_CPLD_UNUSED[10]] +# set_property PACKAGE_PIN AK13 [get_ports DBA_CPLD_UNUSED[11]] + +set UsrpIoAHpPinsSe [get_ports {DBA_MODULE_PWR_ENABLE \ + DBA_RF_PWR_ENABLE \ + DBA_CPLD_PL_SPI_* \ + DBA_TXLO_SPI_CS_B \ + DBA_RXLO_SPI_CS_B \ + DBA_LODIS_SPI_CS_B \ + DBA_CLKDIST_SYNC \ + DBA_TXRX_SW_CTRL_* \ + DBA_ATR_*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoAHpPinsSe +set_property DRIVE 6 $UsrpIoAHpPinsSe +set_property SLEW SLOW $UsrpIoAHpPinsSe + +set UsrpIoAHrPinsSeDr4 [get_ports {DBA_LED_* \ + DBA_CPLD_JTAG_*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSeDr4 +set_property DRIVE 4 $UsrpIoAHrPinsSeDr4 +set_property SLEW SLOW $UsrpIoAHrPinsSeDr4 + +set UsrpIoAHrPinsSeDr8 [get_ports {DBA_CPLD_PS_SPI_* \ + DBA_PHDAC_SPI_CS_B \ + DBA_CLKDIS_SPI_CS_B \ + DBA_ADC_SPI_CS_B \ + DBA_DAC_SPI_CS_B}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSeDr8 +set_property DRIVE 8 $UsrpIoAHrPinsSeDr8 +set_property SLEW SLOW $UsrpIoAHrPinsSeDr8 + +set UsrpIoAHrPinsDiff [get_ports {DBA_ADC_SYNCB_* \ + DBA_DAC_SYNCB_* \ + DBA_FPGA_CLK_* \ + DBA_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoAHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoAHrPinsDiff + + +## USRP IO B : ########################################################################## +# DBB +######################################################################################### + +set_property PACKAGE_PIN J4 [get_ports DBB_MODULE_PWR_ENABLE] +set_property PACKAGE_PIN G4 [get_ports DBB_RF_PWR_ENABLE] + +set_property PACKAGE_PIN AG21 [get_ports DBB_FPGA_CLK_P] +set_property PACKAGE_PIN AH21 [get_ports DBB_FPGA_CLK_N] + +set_property PACKAGE_PIN W8 [get_ports DBB_MGTCLK_P] +set_property PACKAGE_PIN W7 [get_ports DBB_MGTCLK_N] + +set_property PACKAGE_PIN AE22 [get_ports DBB_FPGA_SYSREF_P] +set_property PACKAGE_PIN AF22 [get_ports DBB_FPGA_SYSREF_N] +set_property IOB TRUE [get_ports DBB_FPGA_SYSREF_*] + +set_property PACKAGE_PIN K6 [get_ports DBB_CPLD_PL_SPI_SCLK] +set_property PACKAGE_PIN F2 [get_ports DBB_TXLO_SPI_CS_B]; # DBB_CPLD_PL_SPI_LE +set_property PACKAGE_PIN G2 [get_ports DBB_CPLD_PL_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[0] +set_property PACKAGE_PIN H4 [get_ports DBB_RXLO_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[1] +set_property PACKAGE_PIN H3 [get_ports DBB_LODIS_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[2] +set_property PACKAGE_PIN J6 [get_ports DBB_CPLD_PL_SPI_MISO] +set_property PACKAGE_PIN D5 [get_ports DBB_CPLD_PL_SPI_MOSI] + +set_property PACKAGE_PIN AG22 [get_ports DBB_CPLD_PS_SPI_SCLK] +set_property PACKAGE_PIN AD23 [get_ports DBB_CPLD_PS_SPI_CS_B]; # DBB_CPLD_PS_SPI_ADDR[0] +set_property PACKAGE_PIN AE23 [get_ports DBB_PHDAC_SPI_CS_B]; # DBB_CPLD_PS_SPI_ADDR[1] +set_property PACKAGE_PIN AB24 [get_ports DBB_CLKDIS_SPI_CS_B]; # DBB_CPLD_PS_SPI_LE +set_property PACKAGE_PIN AJ23 [get_ports DBB_ADC_SPI_CS_B]; # DBB_CPLD_UNUSED[12]] +set_property PACKAGE_PIN AJ24 [get_ports DBB_DAC_SPI_CS_B]; # DBB_CPLD_UNUSED[13]] +set_property PACKAGE_PIN AH22 [get_ports DBB_CPLD_PS_SPI_MISO] +set_property PACKAGE_PIN AA24 [get_ports DBB_CPLD_PS_SPI_MOSI] + +set_property PACKAGE_PIN AH19 [get_ports DBB_CPLD_JTAG_TDI] +set_property PACKAGE_PIN AJ19 [get_ports DBB_CPLD_JTAG_TDO] +set_property PACKAGE_PIN AB21 [get_ports DBB_CPLD_JTAG_TMS] +set_property PACKAGE_PIN AB22 [get_ports DBB_CPLD_JTAG_TCK] + +set_property PACKAGE_PIN D3 [get_ports DBB_CLKDIST_SYNC] + +set_property PACKAGE_PIN E6 [get_ports DBB_ATR_TX] +set_property PACKAGE_PIN J5 [get_ports DBB_ATR_RX] + +set_property PACKAGE_PIN K5 [get_ports DBB_TXRX_SW_CTRL_1] +set_property PACKAGE_PIN G5 [get_ports DBB_TXRX_SW_CTRL_2] + +set_property PACKAGE_PIN AF23 [get_ports DBB_ADC_SYNCB_P] +set_property PACKAGE_PIN AF24 [get_ports DBB_ADC_SYNCB_N] +set_property PACKAGE_PIN AD21 [get_ports DBB_DAC_SYNCB_P] +set_property PACKAGE_PIN AE21 [get_ports DBB_DAC_SYNCB_N] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the AD9695 and the DAC37J82 crossbar settings. +set_property PACKAGE_PIN AC4 [get_ports DBB_RX_P[0]] +set_property PACKAGE_PIN AC3 [get_ports DBB_RX_N[0]] +set_property PACKAGE_PIN AB6 [get_ports DBB_RX_P[1]] +set_property PACKAGE_PIN AB5 [get_ports DBB_RX_N[1]] +set_property PACKAGE_PIN Y6 [get_ports DBB_RX_P[2]] +set_property PACKAGE_PIN Y5 [get_ports DBB_RX_N[2]] +set_property PACKAGE_PIN AA4 [get_ports DBB_RX_P[3]] +set_property PACKAGE_PIN AA3 [get_ports DBB_RX_N[3]] + +set_property PACKAGE_PIN AB2 [get_ports DBB_TX_P[0]] +set_property PACKAGE_PIN AB1 [get_ports DBB_TX_N[0]] +set_property PACKAGE_PIN Y2 [get_ports DBB_TX_P[1]] +set_property PACKAGE_PIN Y1 [get_ports DBB_TX_N[1]] +set_property PACKAGE_PIN W4 [get_ports DBB_TX_P[2]] +set_property PACKAGE_PIN W3 [get_ports DBB_TX_N[2]] +set_property PACKAGE_PIN V2 [get_ports DBB_TX_P[3]] +set_property PACKAGE_PIN V1 [get_ports DBB_TX_N[3]] + +set_property PACKAGE_PIN AK17 [get_ports DBB_LED_RX] +set_property PACKAGE_PIN AK18 [get_ports DBB_LED_RX2] +set_property PACKAGE_PIN AK21 [get_ports DBB_LED_TX] + +# Possibly need to be used. Connected to CPLD. +# set_property PACKAGE_PIN G6 [get_ports DBB_CPLD_UNUSED[0]] +# set_property PACKAGE_PIN H6 [get_ports DBB_CPLD_UNUSED[1]] +# set_property PACKAGE_PIN L3 [get_ports DBB_CPLD_UNUSED[2]] +# set_property PACKAGE_PIN L2 [get_ports DBB_CPLD_UNUSED[3]] +# set_property PACKAGE_PIN D4 [get_ports DBB_CPLD_UNUSED[4]] +# set_property PACKAGE_PIN AC22 [get_ports DBB_CPLD_UNUSED[5]] +# set_property PACKAGE_PIN AC23 [get_ports DBB_CPLD_UNUSED[6]] +# set_property PACKAGE_PIN AC24 [get_ports DBB_CPLD_UNUSED[7]] +# set_property PACKAGE_PIN AD24 [get_ports DBB_CPLD_UNUSED[8]] +# set_property PACKAGE_PIN AE22 [get_ports DBB_CPLD_UNUSED[9]] +# set_property PACKAGE_PIN AK20 [get_ports DBB_CPLD_UNUSED[10]] +# set_property PACKAGE_PIN AJ20 [get_ports DBB_CPLD_UNUSED[11]] + +set UsrpIoBHpPinsSe [get_ports {DBB_MODULE_PWR_ENABLE \ + DBB_RF_PWR_ENABLE \ + DBB_CPLD_PL_SPI_* \ + DBB_TXLO_SPI_CS_B \ + DBB_RXLO_SPI_CS_B \ + DBB_LODIS_SPI_CS_B \ + DBB_CLKDIST_SYNC \ + DBB_TXRX_SW_CTRL_* \ + DBB_ATR_*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe +set_property DRIVE 6 $UsrpIoBHpPinsSe +set_property SLEW SLOW $UsrpIoBHpPinsSe + +set UsrpIoBHrPinsSeDr4 [get_ports {DBB_LED_* \ + DBB_CPLD_JTAG_*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSeDr4 +set_property DRIVE 4 $UsrpIoBHrPinsSeDr4 +set_property SLEW SLOW $UsrpIoBHrPinsSeDr4 + +set UsrpIoBHrPinsSeDr8 [get_ports {DBB_CPLD_PS_SPI_* \ + DBB_PHDAC_SPI_CS_B \ + DBB_CLKDIS_SPI_CS_B \ + DBB_ADC_SPI_CS_B \ + DBB_DAC_SPI_CS_B}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSeDr8 +set_property DRIVE 8 $UsrpIoBHrPinsSeDr8 +set_property SLEW SLOW $UsrpIoBHrPinsSeDr8 + +set UsrpIoBHrPinsDiff [get_ports {DBB_ADC_SYNCB_* \ + DBB_DAC_SYNCB_* \ + DBB_FPGA_CLK_* \ + DBB_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc new file mode 100644 index 000000000..cffbd839a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc @@ -0,0 +1,264 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx". +# See this spreadsheet for more details and explanations. + +#******************************************************************************* +## Asynchronous clock groups + +# MGT reference clocks are also async to everything. +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dba -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dbb -include_generated_clocks] + +# fpga_clk_a and fpga_clk_b are related to one another after synchronization. +# However, we do need to declare that these clocks (both a and b) and their children +# are async to the remainder of the design. Use the wildcard at the end to grab the +# virtual clock as well as the real ones. +set_clock_groups -asynchronous -group [get_clocks {fpga_clk_a* fpga_clk_b*} -include_generated_clocks] + +# The SPI readback and write clocks cannot be active at the same time, as they +# originate from the same pin. +set_clock_groups -physically_exclusive \ + -group [get_clocks pl_spi_rb_clk_a] \ + -group [get_clocks pl_spi_clk_a] +set_clock_groups -physically_exclusive \ + -group [get_clocks pl_spi_rb_clk_b] \ + -group [get_clocks pl_spi_clk_b] + +#******************************************************************************* +## PS SPI: since these lines all come from the PS and I don't have access to the +# driving clock (or anything for that matter), I'm left with constraining the maximum +# and minimum delay on these lines, per a Xilinx AR: +# https://www.xilinx.com/support/answers/62122.html +set CPLD_SPI_OUTS [get_ports {DB*_CPLD_PS_SPI_SCLK \ + DB*_CPLD_PS_SPI_MOSI \ + DB*_CPLD_PS_SPI_CS_B \ + DB*_CLKDIS_SPI_CS_B \ + DB*_PHDAC_SPI_CS_B \ + DB*_ADC_SPI_CS_B \ + DB*_DAC_SPI_CS_B}] + +# The actual min and max path delays before applying constraints were (from report_timing): +# 3.332 ns (Min at Fast Process Corner) +# 10.596 ns (Max at Slow Process Corner) +# Therefore, we round those number to their immediate succesor respectively. +# After implementation, the tools were unable to meet timing when leaving a 11 ns max +# delay value, so it was incremented. +set MIN_OUT_DELAY 3.0 +set MAX_OUT_DELAY 12.0 + +set_max_delay $MAX_OUT_DELAY -to $CPLD_SPI_OUTS +set_min_delay $MIN_OUT_DELAY -to $CPLD_SPI_OUTS + +# report_timing -to $CPLD_SPI_OUTS -max_paths 20 -delay_type min_max -name CpldSpiOutTiming + +# The actual min and max path delays before applying constraints were (from report_timing): +# 2.733 ns (Min at Fast Process Corner) +# 6.071 ns (Max at Slow Process Corner) +# Therefore, we round those number to their immediate succesor respectively. +set MIN_IN_DELAY 2.0 +set MAX_IN_DELAY 10.0 + +set PS_SPI_INPUTS_0 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI0MI"}] +set PS_SPI_INPUTS_1 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI1MI"}] + +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_0 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_0 +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_1 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_1 + +# report_timing -to $PS_SPI_INPUTS_0 -max_paths 30 -delay_type min_max -nworst 30 -name Spi0InTiming +# report_timing -to $PS_SPI_INPUTS_1 -max_paths 30 -delay_type min_max -nworst 30 -name Spi1InTiming + + + +#******************************************************************************* +## PL SPI to the CPLD +# +# All of these lines are driven or received from flops in simple_spi_core. The CPLD +# calculations assume the FPGA has less than 6 ns of skew between the SCK and +# SDI/CS_n. Pretty easy constraint to write! See above for the clock definition. +# Do this for DBA and DBB independently. +set MAX_SKEW 6.0 +set SETUP_SKEW [expr {$MAX_SKEW / 2}] +set HOLD_SKEW [expr {$MAX_SKEW / 2}] +# Do not set the output delay constraint on the clock line! +set PORT_LIST_A [get_ports {DBA_CPLD_PL_SPI_CS_B \ + DBA_CPLD_PL_SPI_MOSI \ + DBA_TXLO_SPI_CS_B \ + DBA_RXLO_SPI_CS_B \ + DBA_LODIS_SPI_CS_B }] +set PORT_LIST_B [get_ports {DBB_CPLD_PL_SPI_CS_B \ + DBB_CPLD_PL_SPI_MOSI \ + DBB_TXLO_SPI_CS_B \ + DBB_RXLO_SPI_CS_B \ + DBB_LODIS_SPI_CS_B }] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -1 +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -1 + +# For SDO input timing (MISO), we need to look at the CPLD's constraints on turnaround +# time plus any board propagation delay. +# CPLD clk-to-q is 20 ns, then add 1.2 ns for board delay (once for clock, once for data) +# For hold time, assume zero delay (likely overconstraining here, due to board delays) +set MISO_INPUT_A [get_ports DBA_CPLD_PL_SPI_MISO] +set MISO_INPUT_B [get_ports DBB_CPLD_PL_SPI_MISO] +set_input_delay -clock [get_clocks pl_spi_rb_clk_a] -clock_fall -max 22.400 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_rb_clk_a] -clock_fall -min 0.000 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_rb_clk_b] -clock_fall -max 22.400 $MISO_INPUT_B +set_input_delay -clock [get_clocks pl_spi_rb_clk_b] -clock_fall -min 0.000 $MISO_INPUT_B + +# Since the input delay span is clearly more than a period of the radio_clk, we need to +# add a multicycle path here as well to define the clock divider ratio. The MISO data +# is driven on the falling edge of the SPI clock and captured on the rising edge, so we +# only have one half of a SPI clock cycle for our setup. Hold is left alone and is OK +# as-is due to the delays in the CPLD and board. +set SETUP_CYCLES [expr {$PL_SPI_RB_DIVIDE_VAL / 2}] +set HOLD_CYCLES 0 +set_multicycle_path -setup -from [get_clocks pl_spi_rb_clk_a] -through $MISO_INPUT_A \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_rb_clk_a] -through $MISO_INPUT_A -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] +set_multicycle_path -setup -from [get_clocks pl_spi_rb_clk_b] -through $MISO_INPUT_B \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_rb_clk_b] -through $MISO_INPUT_B -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] + +#******************************************************************************* +## SYSREF/SYNC JESD Timing +# +# SYNC is async, SYSREF is tightly timed. + +# The SYNC output (to ADC) for both DBs is governed by the JESD cores, which are solely +# driven by DB-A clock... but it is an asynchronous signal so we use the async_out_clk. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_ADC_SYNCB_P] +set_max_delay -to [get_ports DB*_ADC_SYNCB_P] 50.000 +set_min_delay -to [get_ports DB*_ADC_SYNCB_P] 0.000 + +# The SYNC input (from DAC) for both DBs is received by the DB-A clock inside the JESD +# cores... but again, it is asynchronous and therefore uses the async_in_clk. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_DAC_SYNCB_P] +set_max_delay -from [get_ports DB*_DAC_SYNCB_P] 50.000 +set_min_delay -from [get_ports DB*_DAC_SYNCB_P] 0.000 + +# SYSREF is driven by the LMK directly to the FPGA. Timing analysis was performed once +# for the worst-case numbers across both DBs to produce one set of numbers for both DBs. +# Since we easily meet setup and hold in Vivado, then this is an acceptable approach. +# SYSREF is captured by the local clock from each DB, so we have two sets of constraints. +set_input_delay -clock fpga_clk_a_v -min -0.479 [get_ports DBA_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_a_v -max 0.661 [get_ports DBA_FPGA_SYSREF_*] + +set_input_delay -clock fpga_clk_b_v -min -0.479 [get_ports DBB_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_b_v -max 0.661 [get_ports DBB_FPGA_SYSREF_*] + + +#******************************************************************************* +## PPS Timing + +# Due to the N3xx synchronization and clocking structure, the PPS output is driven from +# the Sample Clock domain instead of the input Reference Clock. Constrain the output as +# tightly as possible to accurately mimic the internal Sample Clock timing. +set SETUP_SKEW 2.0 +set HOLD_SKEW -0.5 +set_output_delay -clock [get_clocks fpga_clk_a_v] -max -$SETUP_SKEW [get_ports REF_1PPS_OUT] +set_output_delay -clock [get_clocks fpga_clk_a_v] -min $HOLD_SKEW [get_ports REF_1PPS_OUT] +set_multicycle_path -setup -to [get_ports REF_1PPS_OUT] -start 0 +set_multicycle_path -hold -to [get_ports REF_1PPS_OUT] -1 + +#******************************************************************************* +### Async I/Os +set DB_ASYNC_OUTPUTS [get_ports { + DB*_MODULE_PWR_ENABLE + DB*_RF_PWR_ENABLE + DB*_CLKDIST_SYNC + DB*_ATR_TX + DB*_ATR_RX + DB*_TXRX_SW_CTRL_1 + DB*_TXRX_SW_CTRL_2 + DB*_LED_RX + DB*_LED_RX2 + DB*_LED_TX + QSFP_I2C_* +}] +set_output_delay -clock [get_clocks async_out_clk] 0.000 $DB_ASYNC_OUTPUTS +set_max_delay -to $DB_ASYNC_OUTPUTS 50.000 +set_min_delay -to $DB_ASYNC_OUTPUTS 0.000 + +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports QSFP_I2C_*] +set_max_delay -from [get_ports QSFP_I2C_*] 50.000 +set_min_delay -from [get_ports QSFP_I2C_*] 0.000 + +#******************************************************************************* +## JTAG + +## MAX 10 JTAG TDI setup: 2 ns +## MAX 10 JTAG TMS setup: 3 ns +## MAX 10 JTAG hold: 10 ns +## MAX 10 JTAG clk-to-q: 18 ns +## Board delay: < 1.5 ns +## +## Setup time = Board delay + TMS setup = 3 ns + 1.5 ns = 4.5 ns +## Hold time = Board delay + TMS hold = 1.5 ns + 10 ns = 11.5 ns +## Overconstrain output delay and keep skew to +/- 8 ns +## +## Input delay = 2x Board delay + clk-to-q = 3 ns + 18 ns = 21 ns + +# Constrain outputs for skew, with same latch/launch edge: +set_output_delay -clock [get_clocks dba_jtag_tck] -max -4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dba_jtag_tck] -max -4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dba_jtag_tck] -min 4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dba_jtag_tck] -min 4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dbb_jtag_tck] -max -4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dbb_jtag_tck] -max -4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dbb_jtag_tck] -min 4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dbb_jtag_tck] -min 4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks clk40] -to [get_clocks dba_jtag_tck] -start 0 +set_multicycle_path -hold -from [get_clocks clk40] -to [get_clocks dba_jtag_tck] -1 +set_multicycle_path -setup -from [get_clocks clk40] -to [get_clocks dbb_jtag_tck] -start 0 +set_multicycle_path -hold -from [get_clocks clk40] -to [get_clocks dbb_jtag_tck] -1 + +set_input_delay -clock [get_clocks dba_jtag_tck] -clock_fall -max 21 \ + [get_ports DBA_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dba_jtag_tck] -clock_fall -min 0 \ + [get_ports DBA_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dbb_jtag_tck] -clock_fall -max 21 \ + [get_ports DBB_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dbb_jtag_tck] -clock_fall -min 0 \ + [get_ports DBB_CPLD_JTAG_TDO] +# Inputs have setup checks relative to half a period of TCK (launch on fall, +# latch on rise). Actual latch clock is faster, so push back setup and hold +# checks to match. +set_multicycle_path -setup -from [get_clocks dba_jtag_tck] \ + -through [get_ports DBA_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR / 2}] +set_multicycle_path -end -hold -from [get_clocks dba_jtag_tck] \ + -through [get_ports DBA_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR - 1}] +set_multicycle_path -setup -from [get_clocks dbb_jtag_tck] \ + -through [get_ports DBB_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR / 2}] +set_multicycle_path -end -hold -from [get_clocks dbb_jtag_tck] \ + -through [get_ports DBB_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR - 1}] diff --git a/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx b/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx Binary files differnew file mode 100755 index 000000000..7782ee33c --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx diff --git a/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v new file mode 100644 index 000000000..e697f00d4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v @@ -0,0 +1,3855 @@ +/////////////////////////////////////////////////////////////////// +/// +// Copyright 2018-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx +// Description: +// Top Level for N320, N321 devices +// +////////////////////////////////////////////////////////////////////// + +module n3xx ( + inout [11:0] FPGA_GPIO, + + input FPGA_REFCLK_P, + input FPGA_REFCLK_N, + input REF_1PPS_IN, + input NETCLK_REF_P, + input NETCLK_REF_N, + //input REF_1PPS_IN_MGMT, + output REF_1PPS_OUT, + + //TDC + inout UNUSED_PIN_TDCA_0, + inout UNUSED_PIN_TDCA_1, + inout UNUSED_PIN_TDCA_2, + inout UNUSED_PIN_TDCA_3, + inout UNUSED_PIN_TDCB_0, + inout UNUSED_PIN_TDCB_1, + inout UNUSED_PIN_TDCB_2, + inout UNUSED_PIN_TDCB_3, + +`ifdef NPIO_LANES + input NPIO_RX0_P, + input NPIO_RX0_N, + output NPIO_TX0_P, + output NPIO_TX0_N, + input NPIO_RX1_P, + input NPIO_RX1_N, + output NPIO_TX1_P, + output NPIO_TX1_N, +`endif +`ifdef QSFP_LANES + input [`QSFP_LANES-1:0] QSFP_RX_P, + input [`QSFP_LANES-1:0] QSFP_RX_N, + output [`QSFP_LANES-1:0] QSFP_TX_P, + output [`QSFP_LANES-1:0] QSFP_TX_N, + output QSFP_RESET_B, + output QSFP_LED, + output QSFP_MODSEL_B, + output QSFP_LPMODE, + input QSFP_PRESENT_B, + input QSFP_INT_B, + inout QSFP_I2C_SCL, + inout QSFP_I2C_SDA, +`endif + //TODO: Uncomment when connected here + //input NPIO_0_RXSYNC_0_P, NPIO_0_RXSYNC_1_P, + //input NPIO_0_RXSYNC_0_N, NPIO_0_RXSYNC_1_N, + //output NPIO_0_TXSYNC_0_P, NPIO_0_TXSYNC_1_P, + //output NPIO_0_TXSYNC_0_N, NPIO_0_TXSYNC_1_N, + //input NPIO_1_RXSYNC_0_P, NPIO_1_RXSYNC_1_P, + //input NPIO_1_RXSYNC_0_N, NPIO_1_RXSYNC_1_N, + //output NPIO_1_TXSYNC_0_P, NPIO_1_TXSYNC_1_P, + //output NPIO_1_TXSYNC_0_N, NPIO_1_TXSYNC_1_N, + //input NPIO_2_RXSYNC_0_P, NPIO_2_RXSYNC_1_P, + //input NPIO_2_RXSYNC_0_N, NPIO_2_RXSYNC_1_N, + //output NPIO_2_TXSYNC_0_P, NPIO_2_TXSYNC_1_P, + //output NPIO_2_TXSYNC_0_N, NPIO_2_TXSYNC_1_N, + + //GPS + input GPS_1PPS, + //input GPS_1PPS_RAW, + + //Misc + input ENET0_CLK125, + //inout ENET0_PTP, + //output ENET0_PTP_DIR, + //inout ATSHA204_SDA, + input FPGA_PL_RESETN, // TODO: Add to reset logic + // output reg [1:0] FPGA_TEST, + //input PWR_CLK_FPGA, // TODO: check direction + input FPGA_PUDC_B, + + //White Rabbit + input WB_20MHZ_P, + input WB_20MHZ_N, + output WB_DAC_DIN, + output WB_DAC_NCLR, + output WB_DAC_NLDAC, + output WB_DAC_NSYNC, + output WB_DAC_SCLK, + + //LEDS + output PANEL_LED_GPS, + output PANEL_LED_LINK, + output PANEL_LED_PPS, + output PANEL_LED_REF, + + // ARM Connections (PS) + inout [53:0] MIO, + inout PS_SRSTB, + inout PS_CLK, + inout PS_PORB, + inout DDR_Clk, + inout DDR_Clk_n, + inout DDR_CKE, + inout DDR_CS_n, + inout DDR_RAS_n, + inout DDR_CAS_n, + inout DDR_WEB, + inout [2:0] DDR_BankAddr, + inout [14:0] DDR_Addr, + inout DDR_ODT, + inout DDR_DRSTB, + inout [31:0] DDR_DQ, + inout [3:0] DDR_DM, + inout [3:0] DDR_DQS, + inout [3:0] DDR_DQS_n, + inout DDR_VRP, + inout DDR_VRN, + + + /////////////////////////////////// + // + // High Speed SPF+ signals and clocking + // + /////////////////////////////////// + + // These clock inputs must always be enabled with a buffer regardless of the build + // target to avoid damage to the FPGA. + input NETCLK_P, + input NETCLK_N, + input MGT156MHZ_CLK1_P, + input MGT156MHZ_CLK1_N, + + input SFP_0_RX_P, input SFP_0_RX_N, + output SFP_0_TX_P, output SFP_0_TX_N, + input SFP_1_RX_P, input SFP_1_RX_N, + output SFP_1_TX_P, output SFP_1_TX_N, + + + /////////////////////////////////// + // + // DRAM Interface + // + /////////////////////////////////// + inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_p, + // + output [15:0] ddr3_addr, // Address + output [2:0] ddr3_ba, // Bank Address + output ddr3_ras_n, // Row Address Strobe. + output ddr3_cas_n, // Column address select + output ddr3_we_n, // Write Enable + output ddr3_reset_n, // SDRAM reset pin. + output [0:0] ddr3_ck_p, // Differential clock + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, // Clock Enable + output [0:0] ddr3_cs_n, // Chip Select + output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... + output [0:0] ddr3_odt, // On-Die termination enable. + // + input sys_clk_p, // Differential + input sys_clk_n, // 100MHz clock source to generate DDR3 clocking. + + + /////////////////////////////////// + // + // Supporting I/O for SPF+ interfaces + // (non high speed stuff) + // + /////////////////////////////////// + + //SFP+ 0, Slow Speed, Bank 13 3.3V + input SFP_0_I2C_NPRESENT, + output SFP_0_LED_A, + output SFP_0_LED_B, + input SFP_0_LOS, + output SFP_0_RS0, + output SFP_0_RS1, + output SFP_0_TXDISABLE, + input SFP_0_TXFAULT, + + //SFP+ 1, Slow Speed, Bank 13 3.3V + //input SFP_1_I2C_NPRESENT, + output SFP_1_LED_A, + output SFP_1_LED_B, + input SFP_1_LOS, + output SFP_1_RS0, + output SFP_1_RS1, + output SFP_1_TXDISABLE, + input SFP_1_TXFAULT, + + //USRP IO A + output DBA_MODULE_PWR_ENABLE, + output DBA_RF_PWR_ENABLE, + + output DBA_CPLD_PS_SPI_SCLK, + output DBA_CLKDIS_SPI_CS_B, + output DBA_CPLD_PS_SPI_CS_B, + output DBA_PHDAC_SPI_CS_B, + output DBA_CPLD_PS_SPI_MOSI, + input DBA_CPLD_PS_SPI_MISO, + + output DBA_ATR_RX, + output DBA_ATR_TX, + output DBA_TXRX_SW_CTRL_1, + output DBA_TXRX_SW_CTRL_2, + + output DBA_CPLD_PL_SPI_SCLK, + output DBA_ADC_SPI_CS_B, + output DBA_DAC_SPI_CS_B, + output DBA_TXLO_SPI_CS_B, + output DBA_RXLO_SPI_CS_B, + output DBA_LODIS_SPI_CS_B, + output DBA_CPLD_PL_SPI_CS_B, + output DBA_CPLD_PL_SPI_MOSI, + input DBA_CPLD_PL_SPI_MISO, + + output DBA_ADC_SYNCB_P, + output DBA_ADC_SYNCB_N, + input DBA_DAC_SYNCB_P, + input DBA_DAC_SYNCB_N, + + output DBA_CLKDIST_SYNC, + + inout DBA_CPLD_JTAG_TCK, + inout DBA_CPLD_JTAG_TMS, + inout DBA_CPLD_JTAG_TDI, + input DBA_CPLD_JTAG_TDO, + + input DBA_FPGA_CLK_P, + input DBA_FPGA_CLK_N, + + input DBA_FPGA_SYSREF_P, + input DBA_FPGA_SYSREF_N, + + input DBA_MGTCLK_P, + input DBA_MGTCLK_N, + + input [3:0] DBA_RX_P, + input [3:0] DBA_RX_N, + output [3:0] DBA_TX_P, + output [3:0] DBA_TX_N, + + output DBA_LED_RX, + output DBA_LED_RX2, + output DBA_LED_TX, + + //USRP IO B + output DBB_MODULE_PWR_ENABLE, + output DBB_RF_PWR_ENABLE, + + output DBB_CPLD_PS_SPI_SCLK, + output DBB_CLKDIS_SPI_CS_B, + output DBB_CPLD_PS_SPI_CS_B, + output DBB_PHDAC_SPI_CS_B, + output DBB_CPLD_PS_SPI_MOSI, + input DBB_CPLD_PS_SPI_MISO, + + output DBB_ATR_RX, + output DBB_ATR_TX, + output DBB_TXRX_SW_CTRL_1, + output DBB_TXRX_SW_CTRL_2, + + output DBB_CPLD_PL_SPI_SCLK, + output DBB_ADC_SPI_CS_B, + output DBB_DAC_SPI_CS_B, + output DBB_TXLO_SPI_CS_B, + output DBB_RXLO_SPI_CS_B, + output DBB_LODIS_SPI_CS_B, + output DBB_CPLD_PL_SPI_CS_B, + output DBB_CPLD_PL_SPI_MOSI, + input DBB_CPLD_PL_SPI_MISO, + + output DBB_ADC_SYNCB_P, + output DBB_ADC_SYNCB_N, + input DBB_DAC_SYNCB_P, + input DBB_DAC_SYNCB_N, + + output DBB_CLKDIST_SYNC, + + inout DBB_CPLD_JTAG_TCK, + inout DBB_CPLD_JTAG_TMS, + inout DBB_CPLD_JTAG_TDI, + input DBB_CPLD_JTAG_TDO, + + input DBB_FPGA_CLK_P, + input DBB_FPGA_CLK_N, + + input DBB_FPGA_SYSREF_P, + input DBB_FPGA_SYSREF_N, + + input DBB_MGTCLK_P, + input DBB_MGTCLK_N, + + input [3:0] DBB_RX_P, + input [3:0] DBB_RX_N, + output [3:0] DBB_TX_P, + output [3:0] DBB_TX_N, + + output DBB_LED_RX, + output DBB_LED_RX2, + output DBB_LED_TX +); + + localparam N_AXILITE_SLAVES = 4; + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam QSFP_REG_AWIDTH = 17; // log2(0x20000) + localparam REG_DWIDTH = 32; + localparam FP_GPIO_OFFSET = 32; + localparam FP_GPIO_WIDTH = 12; + + localparam NUM_RADIOS = 2; + localparam NUM_CHANNELS_PER_RADIO = 1; + localparam NUM_DBOARDS = 2; + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam CHANNEL_WIDTH = 32; + + + // Internal connections to PS + // HP0 -- High Performance port 0, FPGA is the master + wire [5:0] S_AXI_HP0_AWID; + wire [31:0] S_AXI_HP0_AWADDR; + wire [2:0] S_AXI_HP0_AWPROT; + wire S_AXI_HP0_AWVALID; + wire S_AXI_HP0_AWREADY; + wire [63:0] S_AXI_HP0_WDATA; + wire [7:0] S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP0_WREADY; + wire [1:0] S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire S_AXI_HP0_BREADY; + wire [5:0] S_AXI_HP0_ARID; + wire [31:0] S_AXI_HP0_ARADDR; + wire [2:0] S_AXI_HP0_ARPROT; + wire S_AXI_HP0_ARVALID; + wire S_AXI_HP0_ARREADY; + wire [63:0] S_AXI_HP0_RDATA; + wire [1:0] S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire S_AXI_HP0_RREADY; + wire S_AXI_HP0_RLAST; + wire [3:0] S_AXI_HP0_ARCACHE; + wire [7:0] S_AXI_HP0_AWLEN; + wire [2:0] S_AXI_HP0_AWSIZE; + wire [1:0] S_AXI_HP0_AWBURST; + wire [3:0] S_AXI_HP0_AWCACHE; + wire S_AXI_HP0_WLAST; + wire [7:0] S_AXI_HP0_ARLEN; + wire [1:0] S_AXI_HP0_ARBURST; + wire [2:0] S_AXI_HP0_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the master + wire [4:0] S_AXI_GP0_AWID; + wire [31:0] S_AXI_GP0_AWADDR; + wire [2:0] S_AXI_GP0_AWPROT; + wire S_AXI_GP0_AWVALID; + wire S_AXI_GP0_AWREADY; + wire [31:0] S_AXI_GP0_WDATA; + wire [3:0] S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP0_WREADY; + wire [1:0] S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire S_AXI_GP0_BREADY; + wire [4:0] S_AXI_GP0_ARID; + wire [31:0] S_AXI_GP0_ARADDR; + wire [2:0] S_AXI_GP0_ARPROT; + wire S_AXI_GP0_ARVALID; + wire S_AXI_GP0_ARREADY; + wire [31:0] S_AXI_GP0_RDATA; + wire [1:0] S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire S_AXI_GP0_RREADY; + wire S_AXI_GP0_RLAST; + wire [3:0] S_AXI_GP0_ARCACHE; + wire [7:0] S_AXI_GP0_AWLEN; + wire [2:0] S_AXI_GP0_AWSIZE; + wire [1:0] S_AXI_GP0_AWBURST; + wire [3:0] S_AXI_GP0_AWCACHE; + wire S_AXI_GP0_WLAST; + wire [7:0] S_AXI_GP0_ARLEN; + wire [1:0] S_AXI_GP0_ARBURST; + wire [2:0] S_AXI_GP0_ARSIZE; + + // HP1 -- High Performance port 1, FPGA is the master + wire [5:0] S_AXI_HP1_AWID; + wire [31:0] S_AXI_HP1_AWADDR; + wire [2:0] S_AXI_HP1_AWPROT; + wire S_AXI_HP1_AWVALID; + wire S_AXI_HP1_AWREADY; + wire [63:0] S_AXI_HP1_WDATA; + wire [7:0] S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP1_WREADY; + wire [1:0] S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire S_AXI_HP1_BREADY; + wire [5:0] S_AXI_HP1_ARID; + wire [31:0] S_AXI_HP1_ARADDR; + wire [2:0] S_AXI_HP1_ARPROT; + wire S_AXI_HP1_ARVALID; + wire S_AXI_HP1_ARREADY; + wire [63:0] S_AXI_HP1_RDATA; + wire [1:0] S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire S_AXI_HP1_RREADY; + wire S_AXI_HP1_RLAST; + wire [3:0] S_AXI_HP1_ARCACHE; + wire [7:0] S_AXI_HP1_AWLEN; + wire [2:0] S_AXI_HP1_AWSIZE; + wire [1:0] S_AXI_HP1_AWBURST; + wire [3:0] S_AXI_HP1_AWCACHE; + wire S_AXI_HP1_WLAST; + wire [7:0] S_AXI_HP1_ARLEN; + wire [1:0] S_AXI_HP1_ARBURST; + wire [2:0] S_AXI_HP1_ARSIZE; + + // GP1 -- General Purpose port 1, FPGA is the master + wire [4:0] S_AXI_GP1_AWID; + wire [31:0] S_AXI_GP1_AWADDR; + wire [2:0] S_AXI_GP1_AWPROT; + wire S_AXI_GP1_AWVALID; + wire S_AXI_GP1_AWREADY; + wire [31:0] S_AXI_GP1_WDATA; + wire [3:0] S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_GP1_WREADY; + wire [1:0] S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire S_AXI_GP1_BREADY; + wire [4:0] S_AXI_GP1_ARID; + wire [31:0] S_AXI_GP1_ARADDR; + wire [2:0] S_AXI_GP1_ARPROT; + wire S_AXI_GP1_ARVALID; + wire S_AXI_GP1_ARREADY; + wire [31:0] S_AXI_GP1_RDATA; + wire [1:0] S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire S_AXI_GP1_RREADY; + wire S_AXI_GP1_RLAST; + wire [3:0] S_AXI_GP1_ARCACHE; + wire [7:0] S_AXI_GP1_AWLEN; + wire [2:0] S_AXI_GP1_AWSIZE; + wire [1:0] S_AXI_GP1_AWBURST; + wire [3:0] S_AXI_GP1_AWCACHE; + wire S_AXI_GP1_WLAST; + wire [7:0] S_AXI_GP1_ARLEN; + wire [1:0] S_AXI_GP1_ARBURST; + wire [2:0] S_AXI_GP1_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the slave + wire M_AXI_GP0_ARVALID; + wire M_AXI_GP0_AWVALID; + wire M_AXI_GP0_BREADY; + wire M_AXI_GP0_RREADY; + wire M_AXI_GP0_WVALID; + wire [11:0] M_AXI_GP0_ARID; + wire [11:0] M_AXI_GP0_AWID; + wire [11:0] M_AXI_GP0_WID; + wire [31:0] M_AXI_GP0_ARADDR; + wire [31:0] M_AXI_GP0_AWADDR; + wire [31:0] M_AXI_GP0_WDATA; + wire [3:0] M_AXI_GP0_WSTRB; + wire M_AXI_GP0_ARREADY; + wire M_AXI_GP0_AWREADY; + wire M_AXI_GP0_BVALID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RVALID; + wire M_AXI_GP0_WREADY; + wire [1:0] M_AXI_GP0_BRESP; + wire [1:0] M_AXI_GP0_RRESP; + wire [31:0] M_AXI_GP0_RDATA; + + wire M_AXI_ETH_DMA0_ARVALID; + wire M_AXI_ETH_DMA0_AWVALID; + wire M_AXI_ETH_DMA0_BREADY; + wire M_AXI_ETH_DMA0_RREADY; + wire M_AXI_ETH_DMA0_WVALID; + wire [11:0] M_AXI_ETH_DMA0_ARID; + wire [11:0] M_AXI_ETH_DMA0_AWID; + wire [11:0] M_AXI_ETH_DMA0_WID; + wire [31:0] M_AXI_ETH_DMA0_ARADDR; + wire [31:0] M_AXI_ETH_DMA0_AWADDR; + wire [31:0] M_AXI_ETH_DMA0_WDATA; + wire [3:0] M_AXI_ETH_DMA0_WSTRB; + wire M_AXI_ETH_DMA0_ARREADY; + wire M_AXI_ETH_DMA0_AWREADY; + wire M_AXI_ETH_DMA0_BVALID; + wire M_AXI_ETH_DMA0_RLAST; + wire M_AXI_ETH_DMA0_RVALID; + wire M_AXI_ETH_DMA0_WREADY; + wire [1:0] M_AXI_ETH_DMA0_BRESP; + wire [1:0] M_AXI_ETH_DMA0_RRESP; + wire [31:0] M_AXI_ETH_DMA0_RDATA; + + wire M_AXI_NET0_ARVALID; + wire M_AXI_NET0_AWVALID; + wire M_AXI_NET0_BREADY; + wire M_AXI_NET0_RREADY; + wire M_AXI_NET0_WVALID; + wire [11:0] M_AXI_NET0_ARID; + wire [11:0] M_AXI_NET0_AWID; + wire [11:0] M_AXI_NET0_WID; + wire [31:0] M_AXI_NET0_ARADDR; + wire [31:0] M_AXI_NET0_AWADDR; + wire [31:0] M_AXI_NET0_WDATA; + wire [3:0] M_AXI_NET0_WSTRB; + wire M_AXI_NET0_ARREADY; + wire M_AXI_NET0_AWREADY; + wire M_AXI_NET0_BVALID; + wire M_AXI_NET0_RLAST; + wire M_AXI_NET0_RVALID; + wire M_AXI_NET0_WREADY; + wire [1:0] M_AXI_NET0_BRESP; + wire [1:0] M_AXI_NET0_RRESP; + wire [31:0] M_AXI_NET0_RDATA; + + wire M_AXI_ETH_DMA1_ARVALID; + wire M_AXI_ETH_DMA1_AWVALID; + wire M_AXI_ETH_DMA1_BREADY; + wire M_AXI_ETH_DMA1_RREADY; + wire M_AXI_ETH_DMA1_WVALID; + wire [11:0] M_AXI_ETH_DMA1_ARID; + wire [11:0] M_AXI_ETH_DMA1_AWID; + wire [11:0] M_AXI_ETH_DMA1_WID; + wire [31:0] M_AXI_ETH_DMA1_ARADDR; + wire [31:0] M_AXI_ETH_DMA1_AWADDR; + wire [31:0] M_AXI_ETH_DMA1_WDATA; + wire [3:0] M_AXI_ETH_DMA1_WSTRB; + wire M_AXI_ETH_DMA1_ARREADY; + wire M_AXI_ETH_DMA1_AWREADY; + wire M_AXI_ETH_DMA1_BVALID; + wire M_AXI_ETH_DMA1_RLAST; + wire M_AXI_ETH_DMA1_RVALID; + wire M_AXI_ETH_DMA1_WREADY; + wire [1:0] M_AXI_ETH_DMA1_BRESP; + wire [1:0] M_AXI_ETH_DMA1_RRESP; + wire [31:0] M_AXI_ETH_DMA1_RDATA; + + wire M_AXI_NET1_ARVALID; + wire M_AXI_NET1_AWVALID; + wire M_AXI_NET1_BREADY; + wire M_AXI_NET1_RREADY; + wire M_AXI_NET1_WVALID; + wire [11:0] M_AXI_NET1_ARID; + wire [11:0] M_AXI_NET1_AWID; + wire [11:0] M_AXI_NET1_WID; + wire [31:0] M_AXI_NET1_ARADDR; + wire [31:0] M_AXI_NET1_AWADDR; + wire [31:0] M_AXI_NET1_WDATA; + wire [3:0] M_AXI_NET1_WSTRB; + wire M_AXI_NET1_ARREADY; + wire M_AXI_NET1_AWREADY; + wire M_AXI_NET1_BVALID; + wire M_AXI_NET1_RLAST; + wire M_AXI_NET1_RVALID; + wire M_AXI_NET1_WREADY; + wire [1:0] M_AXI_NET1_BRESP; + wire [1:0] M_AXI_NET1_RRESP; + wire [31:0] M_AXI_NET1_RDATA; + + wire M_AXI_NET2_ARVALID; + wire M_AXI_NET2_AWVALID; + wire M_AXI_NET2_BREADY; + wire M_AXI_NET2_RREADY; + wire M_AXI_NET2_WVALID; + wire [11:0] M_AXI_NET2_ARID; + wire [11:0] M_AXI_NET2_AWID; + wire [11:0] M_AXI_NET2_WID; + wire [31:0] M_AXI_NET2_ARADDR; + wire [31:0] M_AXI_NET2_AWADDR; + wire [31:0] M_AXI_NET2_WDATA; + wire [3:0] M_AXI_NET2_WSTRB; + wire M_AXI_NET2_ARREADY; + wire M_AXI_NET2_AWREADY; + wire M_AXI_NET2_BVALID; + wire M_AXI_NET2_RLAST; + wire M_AXI_NET2_RVALID; + wire M_AXI_NET2_WREADY; + wire [1:0] M_AXI_NET2_BRESP; + wire [1:0] M_AXI_NET2_RRESP; + wire [31:0] M_AXI_NET2_RDATA; + + wire M_AXI_XBAR_ARVALID; + wire M_AXI_XBAR_AWVALID; + wire M_AXI_XBAR_BREADY; + wire M_AXI_XBAR_RREADY; + wire M_AXI_XBAR_WVALID; + wire [11:0] M_AXI_XBAR_ARID; + wire [11:0] M_AXI_XBAR_AWID; + wire [11:0] M_AXI_XBAR_WID; + wire [31:0] M_AXI_XBAR_ARADDR; + wire [31:0] M_AXI_XBAR_AWADDR; + wire [31:0] M_AXI_XBAR_WDATA; + wire [3:0] M_AXI_XBAR_WSTRB; + wire M_AXI_XBAR_ARREADY; + wire M_AXI_XBAR_AWREADY; + wire M_AXI_XBAR_BVALID; + wire M_AXI_XBAR_RLAST; + wire M_AXI_XBAR_RVALID; + wire M_AXI_XBAR_WREADY; + wire [1:0] M_AXI_XBAR_BRESP; + wire [1:0] M_AXI_XBAR_RRESP; + wire [31:0] M_AXI_XBAR_RDATA; + + wire M_AXI_JESD0_ARVALID; + wire M_AXI_JESD0_AWVALID; + wire M_AXI_JESD0_BREADY; + wire M_AXI_JESD0_RREADY; + wire M_AXI_JESD0_WVALID; + wire [11:0] M_AXI_JESD0_ARID; + wire [11:0] M_AXI_JESD0_AWID; + wire [11:0] M_AXI_JESD0_WID; + wire [31:0] M_AXI_JESD0_ARADDR; + wire [31:0] M_AXI_JESD0_AWADDR; + wire [31:0] M_AXI_JESD0_WDATA; + wire [3:0] M_AXI_JESD0_WSTRB; + wire M_AXI_JESD0_ARREADY; + wire M_AXI_JESD0_AWREADY; + wire M_AXI_JESD0_BVALID; + wire M_AXI_JESD0_RLAST; + wire M_AXI_JESD0_RVALID; + wire M_AXI_JESD0_WREADY; + wire [1:0] M_AXI_JESD0_BRESP; + wire [1:0] M_AXI_JESD0_RRESP; + wire [31:0] M_AXI_JESD0_RDATA; + + wire M_AXI_JESD1_ARVALID; + wire M_AXI_JESD1_AWVALID; + wire M_AXI_JESD1_BREADY; + wire M_AXI_JESD1_RREADY; + wire M_AXI_JESD1_WVALID; + wire [11:0] M_AXI_JESD1_ARID; + wire [11:0] M_AXI_JESD1_AWID; + wire [11:0] M_AXI_JESD1_WID; + wire [31:0] M_AXI_JESD1_ARADDR; + wire [31:0] M_AXI_JESD1_AWADDR; + wire [31:0] M_AXI_JESD1_WDATA; + wire [3:0] M_AXI_JESD1_WSTRB; + wire M_AXI_JESD1_ARREADY; + wire M_AXI_JESD1_AWREADY; + wire M_AXI_JESD1_BVALID; + wire M_AXI_JESD1_RLAST; + wire M_AXI_JESD1_RVALID; + wire M_AXI_JESD1_WREADY; + wire [1:0] M_AXI_JESD1_BRESP; + wire [1:0] M_AXI_JESD1_RRESP; + wire [31:0] M_AXI_JESD1_RDATA; + + // White Rabbit + wire wr_uart_txd; + wire wr_uart_rxd; + wire pps_wr_refclk; + wire wr_ref_clk; + + // AXI bus from PS to WR Core + wire m_axi_wr_clk; + wire [31:0] m_axi_wr_araddr; + wire [0:0] m_axi_wr_arready; + wire [0:0] m_axi_wr_arvalid; + wire [31:0] m_axi_wr_awaddr; + wire [0:0] m_axi_wr_awready; + wire [0:0] m_axi_wr_awvalid; + wire [0:0] m_axi_wr_bready; + wire [1:0] m_axi_wr_bresp; + wire [0:0] m_axi_wr_bvalid; + wire [31:0] m_axi_wr_rdata; + wire [0:0] m_axi_wr_rready; + wire [1:0] m_axi_wr_rresp; + wire [0:0] m_axi_wr_rvalid; + wire [31:0] m_axi_wr_wdata; + wire [0:0] m_axi_wr_wready; + wire [3:0] m_axi_wr_wstrb; + wire [0:0] m_axi_wr_wvalid; + + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_tri; + + wire [15:0] IRQ_F2P; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire clk100; + wire clk40; + wire meas_clk_ref; + wire bus_clk; + wire gige_refclk; + wire gige_refclk_bufg; + wire xgige_refclk; + wire xgige_clk156; + wire xgige_dclk; + + wire global_rst; + wire radio_rst; + wire bus_rst; + wire FCLK_RESET0_N; + wire clk40_rst; + wire clk40_rstn; + + wire [1:0] USB0_PORT_INDCTL; + wire USB0_VBUS_PWRSELECT; + wire USB0_VBUS_PWRFAULT; + + wire ref_clk; + wire wr_refclk_buf; + wire netclk_buf; + wire meas_clk; + wire ddr3_dma_clk; + wire meas_clk_reset; + wire meas_clk_locked; + wire enable_ref_clk_async; + wire pps_radioclk1x_iob; + wire pps_radioclk1x; + wire [3:0] pps_select; + wire pps_out_enb; + wire [1:0] pps_select_sfp; + wire pps_refclk; + wire export_pps_radioclk; + wire radio_clk; + wire radio_clkB; + wire radio_clk_2x; + wire radio_clk_2xB; + + wire qsfp_sda_i; + wire qsfp_sda_o; + wire qsfp_sda_t; + wire qsfp_scl_i; + wire qsfp_scl_o; + wire qsfp_scl_t; + + ///////////////////////////////////////////////////////////////////// + // + // Resets + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); + + // Synchronous reset for the radio_clk domain, based on the global_rst. + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(global_rst), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain, based on the global_rst. + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(global_rst), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + + + ///////////////////////////////////////////////////////////////////// + // + // Timing + // + ////////////////////////////////////////////////////////////////////// + + // Clocks from the PS + // + // These clocks appear to have BUFGs already instantiated by the ip generator. + // Simply rename them here for clarity. + // FCLK_CLK0 : 100 MHz + // FCLK_CLK1 : 40 MHz + // FCLK_CLK2 : 166.6667 MHz + // FCLK_CLK3 : 200 MHz + assign clk100 = FCLK_CLK0; + assign clk40 = FCLK_CLK1; + assign meas_clk_ref = FCLK_CLK2; + assign bus_clk = FCLK_CLK3; + + //If bus_clk freq ever changes, update this paramter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + + n3xx_clocking n3xx_clocking_i ( + .enable_ref_clk_async(enable_ref_clk_async), + .FPGA_REFCLK_P(FPGA_REFCLK_P), + .FPGA_REFCLK_N(FPGA_REFCLK_N), + .ref_clk(ref_clk), + .WB_20MHz_P(WB_20MHZ_P), + .WB_20MHz_N(WB_20MHZ_N), + .wr_refclk_buf(wr_refclk_buf), + .NETCLK_REF_P(NETCLK_REF_P), + .NETCLK_REF_N(NETCLK_REF_N), + .netclk_buf(netclk_buf), + .NETCLK_P(NETCLK_P), + .NETCLK_N(NETCLK_N), + .gige_refclk_buf(gige_refclk), + .MGT156MHZ_CLK1_P(MGT156MHZ_CLK1_P), + .MGT156MHZ_CLK1_N(MGT156MHZ_CLK1_N), + .xgige_refclk_buf(xgige_refclk), + .misc_clks_ref(meas_clk_ref), + .meas_clk(meas_clk), + .ddr3_dma_clk(ddr3_dma_clk), + .misc_clks_reset(meas_clk_reset), + .misc_clks_locked(meas_clk_locked), + .ext_pps_from_pin(REF_1PPS_IN), + .gps_pps_from_pin(GPS_1PPS), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + // Drive the rear panel connector with another controllable copy of the post-TDC PPS + // that SW can enable/disable. The user is free to hack this to be whatever + // they desire. Flop the PPS signal one more time in order that it can be packed into + // an IOB. This extra flop stage matches the additional flop inside DbCore to allow + // pps_radioclk1x and pps_out_radioclk to be in sync with one another. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) pps_export_dsync ( + .clk(radio_clk), .rst(1'b0), .in(pps_out_enb), .out(export_pps_radioclk) + ); + + // The radio_clk rate is between [122.88M, 250M] for all known N3xx variants, + // resulting in approximately [8ns, 4ns] periods. To pulse-extend the PPS output, + // we create a 25 bit-wide counter, creating ~[.262s, .131s] long output high pulses, + // variable depending on our radio_clk rate. Create two of the same output signal + // in order that the PPS_OUT gets packed into an IOB for tight timing. + reg [24:0] pps_out_count = 'b0; + reg pps_out_radioclk = 1'b0; + reg pps_led_radioclk = 1'b0; + + always @(posedge radio_clk) begin + if (export_pps_radioclk) begin + if (pps_radioclk1x_iob) begin + pps_out_radioclk <= 1'b1; + pps_led_radioclk <= 1'b1; + pps_out_count <= {25{1'b1}}; + end else begin + if (pps_out_count > 0) begin + pps_out_count <= pps_out_count - 1'b1; + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + // Local to output. + assign REF_1PPS_OUT = pps_out_radioclk; + assign PANEL_LED_PPS = pps_led_radioclk; + + ///////////////////////////////////////////////////////////////////// + // + // SFP, QSFP and NPIO MGT Connections + // + ////////////////////////////////////////////////////////////////////// + wire reg_wr_req_npio; + wire [REG_AWIDTH-1:0] reg_wr_addr_npio; + wire [REG_DWIDTH-1:0] reg_wr_data_npio; + wire reg_rd_req_npio; + wire [REG_AWIDTH-1:0] reg_rd_addr_npio; + wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; + wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; + + localparam NPIO_REG_BASE = 14'h0200; + + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) npio_resp_mux_i( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio0, reg_rd_resp_npio1}), + .sla_rd_data({reg_rd_data_npio0, reg_rd_data_npio1}), + .mst_rd_resp(reg_rd_resp_npio), .mst_rd_data(reg_rd_data_npio) + ); + + //-------------------------------------------------------------- + // SFP/MGT Reference Clocks + //-------------------------------------------------------------- + + // We support the HG, XG, XA, AA targets, all of which require + // the 156.25MHz reference clock. Instantiate it here. + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + wire qpllreset; + wire qpllreset_sfp0, qpllreset_sfp1, qpllreset_npio0, qpllreset_npio1; + wire qplllock; + wire qplloutclk; + wire qplloutrefclk; + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), //from 2nd sfp + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b101 /*GTSOUTHREFCLK0*/) + ); + + // The quad's QPLL should reset if any of the channels request it + // This should never really happen because we are not changing the reference clock + // source for the QPLL. + assign qpllreset = qpllreset_sfp0 | qpllreset_sfp1 | qpllreset_npio0 | qpllreset_npio1; + + // Use the 156.25MHz reference clock for Aurora + wire aurora_refclk = xgige_refclk; + wire aurora_clk156 = xgige_clk156; + wire aurora_init_clk = xgige_dclk; + + // White Rabbit and 1GbE both use the same clocking +`ifdef SFP0_1GBE + `define SFP0_WR_1GBE +`endif +`ifdef SFP0_WR + `define SFP0_WR_1GBE +`endif + +`ifdef SFP0_WR_1GBE + // HG and WX targets require the 1GbE clock support + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + assign SFP_0_RS0 = 1'b0; + assign SFP_0_RS1 = 1'b0; +`else + assign SFP_0_RS0 = 1'b1; + assign SFP_0_RS1 = 1'b1; +`endif + + // SFP 1 is always set to run at ~10Gbps rates. + assign SFP_1_RS0 = 1'b1; + assign SFP_1_RS1 = 1'b1; + + // SFP port specific reference clocks + wire sfp0_gt_refclk, sfp1_gt_refclk; + wire sfp0_gb_refclk, sfp1_gb_refclk; + wire sfp0_misc_clk, sfp1_misc_clk; + +`ifdef SFP0_10GBE + assign sfp0_gt_refclk = xgige_refclk; + assign sfp0_gb_refclk = xgige_clk156; + assign sfp0_misc_clk = xgige_dclk; +`endif +`ifdef SFP0_WR_1GBE + assign sfp0_gt_refclk = gige_refclk; + assign sfp0_gb_refclk = gige_refclk_bufg; + assign sfp0_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP0_AURORA + assign sfp0_gt_refclk = aurora_refclk; + assign sfp0_gb_refclk = aurora_clk156; + assign sfp0_misc_clk = aurora_init_clk; +`endif + +`ifdef SFP1_10GBE + assign sfp1_gt_refclk = xgige_refclk; + assign sfp1_gb_refclk = xgige_clk156; + assign sfp1_misc_clk = xgige_dclk; +`endif +`ifdef SFP1_1GBE + assign sfp1_gt_refclk = gige_refclk; + assign sfp1_gb_refclk = gige_refclk_bufg; + assign sfp1_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP1_AURORA + assign sfp1_gt_refclk = aurora_refclk; + assign sfp1_gb_refclk = aurora_clk156; + assign sfp1_misc_clk = aurora_init_clk; +`endif + + // Instantiate Aurora MMCM if either of the SFPs + // or NPIOs are Aurora + wire au_tx_clk; + wire au_mmcm_reset; + wire au_user_clk; + wire au_sync_clk; + wire au_mmcm_locked; + wire sfp0_tx_out_clk, sfp1_tx_out_clk; + wire sfp0_gt_pll_lock, sfp1_gt_pll_lock; + wire npio0_tx_out_clk, npio1_tx_out_clk; + wire npio0_gt_pll_lock, npio1_gt_pll_lock; + + //NOTE: need to declare one of these defines in order to enable Aurora on + //any SFP or NPIO lane. +`ifdef SFP1_AURORA + `define SFP_AU_MMCM + assign au_tx_clk = sfp1_tx_out_clk; + assign au_mmcm_reset = ~sfp1_gt_pll_lock; +`elsif NPIO0 + `define SFP_AU_MMCM + assign au_tx_clk = npio0_tx_out_clk; + assign au_mmcm_reset = ~npio0_gt_pll_lock; +`elsif NPIO1 + `define SFP_AU_MMCM + assign au_tx_clk = npio1_tx_out_clk; + assign au_mmcm_reset = ~npio1_gt_pll_lock; +`endif + + +`ifdef SFP_AU_MMCM + aurora_phy_mmcm au_phy_mmcm_i ( + .aurora_tx_clk_unbuf(au_tx_clk), + .mmcm_reset(au_mmcm_reset), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); +`else + assign au_user_clk = 1'b0; + assign au_sync_clk = 1'b0; + assign au_mmcm_locked = 1'b0; +`endif + + //-------------------------------------------------------------- + // NPIO-QSFP MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef QSFP_LANES + localparam NUM_QSFP_LANES = `QSFP_LANES; + + // QSFP wires to the ARM core and the crossbar + // These will only be connected if QSFP is 2x10 GbE + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_tx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_tx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_tx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_rx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_rx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_rx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] v2e_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tready; + + wire [NUM_QSFP_LANES*64-1:0] e2v_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tready; + + wire [NUM_QSFP_LANES-1:0] qsfp_link_up; + + // QSFP quad's specific reference clocks + wire qsfp_gt_refclk; + wire qsfp_gb_refclk; + wire qsfp_misc_clk; + + wire qsfp_qplloutclk; + wire qsfp_qplloutrefclk; + wire qsfp_qplllock; + wire qsfp_qpllreset; + + wire qsfp_gt_tx_out_clk; + wire qsfp_gt_pll_lock; + + wire qsfp_au_user_clk; + wire qsfp_au_sync_clk; + wire qsfp_au_mmcm_locked; + + +`ifdef QSFP_10GBE + assign qsfp_gt_refclk = xgige_refclk; + assign qsfp_gb_refclk = xgige_clk156; + assign qsfp_misc_clk = xgige_dclk; +`endif +`ifdef QSFP_AURORA + assign qsfp_gt_refclk = aurora_refclk; + assign qsfp_gb_refclk = aurora_clk156; + assign qsfp_misc_clk = aurora_init_clk; +`endif + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) qsfp_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qsfp_qpllreset), + .qplllock(qsfp_qplllock), + .qplloutclk(qsfp_qplloutclk), + .qplloutrefclk(qsfp_qplloutrefclk), + .qpllrefclksel(3'b001 /*GTREFCLK0*/) + ); + + `ifdef QSFP_AURORA + aurora_phy_mmcm aurora_phy_mmcm ( + .aurora_tx_clk_unbuf(qsfp_gt_tx_out_clk), + .mmcm_reset(~qsfp_gt_pll_lock), + .user_clk(qsfp_au_user_clk), + .sync_clk(qsfp_au_sync_clk), + .mmcm_locked(qsfp_au_mmcm_locked) + ); + `else + assign qsfp_au_user_clk = 1'b0; + assign qsfp_au_sync_clk = 1'b0; + assign qsfp_au_mmcm_locked = 1'b0; + `endif + + n3xx_mgt_channel_wrapper #( + `ifdef QSFP_10GBE + .PROTOCOL ("10GbE"), + .MDIO_EN (1'b1), + .MDIO_PHYADDR (5'd4), + `elsif QSFP_AURORA + .PROTOCOL ("Aurora"), + .MDIO_EN (1'b0), + `endif + .LANES (NUM_QSFP_LANES), + .GT_COMMON (1), + .PORTNUM_BASE (4), + .REG_DWIDTH (REG_DWIDTH), + .REG_AWIDTH (QSFP_REG_AWIDTH) + ) qsfp_wrapper_i ( + .areset (global_rst), + .gt_refclk (qsfp_gt_refclk), + .gb_refclk (qsfp_gb_refclk), + .misc_clk (qsfp_misc_clk), + .user_clk (qsfp_au_user_clk), + .sync_clk (qsfp_au_sync_clk), + .gt_tx_out_clk_unbuf(qsfp_gt_tx_out_clk), + + .bus_clk (bus_clk), + .bus_rst (bus_rst), + + // GT Common + .qpllrefclklost (), + .qplllock (qsfp_qplllock), + .qplloutclk (qsfp_qplloutclk), + .qplloutrefclk (qsfp_qplloutrefclk), + .qpllreset (qsfp_qpllreset), + + // Aurora MMCM + .mmcm_locked (qsfp_au_mmcm_locked), + .gt_pll_lock (qsfp_gt_pll_lock), + + .txp (QSFP_TX_P), + .txn (QSFP_TX_N), + .rxp (QSFP_RX_P), + .rxn (QSFP_RX_N), + + .mod_present_n (QSFP_PRESENT_B), + .mod_rxlos (1'b0), + .mod_tx_fault (1'b0), + .mod_tx_disable (), + .mod_int_n (QSFP_INT_B), + .mod_reset_n (QSFP_RESET_B), + .mod_lpmode (QSFP_LPMODE), + .mod_sel_n (QSFP_MODSEL_B), + + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_aresetn (clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (M_AXI_NET2_AWADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_awvalid (M_AXI_NET2_AWVALID), + .s_axi_awready (M_AXI_NET2_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (M_AXI_NET2_WDATA), + .s_axi_wstrb (M_AXI_NET2_WSTRB), + .s_axi_wvalid (M_AXI_NET2_WVALID), + .s_axi_wready (M_AXI_NET2_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (M_AXI_NET2_BRESP), + .s_axi_bvalid (M_AXI_NET2_BVALID), + .s_axi_bready (M_AXI_NET2_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (M_AXI_NET2_ARADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_arvalid (M_AXI_NET2_ARVALID), + .s_axi_arready (M_AXI_NET2_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_NET2_RDATA), + .s_axi_rresp (M_AXI_NET2_RRESP), + .s_axi_rvalid (M_AXI_NET2_RVALID), + .s_axi_rready (M_AXI_NET2_RREADY), + + // Ethernet to Vita + .e2v_tdata (e2v_qsfp_tdata), + .e2v_tlast (e2v_qsfp_tlast), + .e2v_tvalid (e2v_qsfp_tvalid), + .e2v_tready (e2v_qsfp_tready), + + // Vita to Ethernet + .v2e_tdata (v2e_qsfp_tdata), + .v2e_tlast (v2e_qsfp_tlast), + .v2e_tvalid (v2e_qsfp_tvalid), + .v2e_tready (v2e_qsfp_tready), + + // Ethernet to CPU + .e2c_tdata (arm_eth_qsfp_rx_tdata_b), + .e2c_tkeep (arm_eth_qsfp_rx_tkeep_b), + .e2c_tlast (arm_eth_qsfp_rx_tlast_b), + .e2c_tvalid (arm_eth_qsfp_rx_tvalid_b), + .e2c_tready (arm_eth_qsfp_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata (arm_eth_qsfp_tx_tdata_b), + .c2e_tkeep (arm_eth_qsfp_tx_tkeep_b), + .c2e_tlast (arm_eth_qsfp_tx_tlast_b), + .c2e_tvalid (arm_eth_qsfp_tx_tvalid_b), + .c2e_tready (arm_eth_qsfp_tx_tready_b), + + // Sideband White Rabbit Control + .wr_reset_n (1'b1), + .wr_refclk (1'b0), + + .wr_dac_sclk (), + .wr_dac_din (), + .wr_dac_clr_n (), + .wr_dac_cs_n (), + .wr_dac_ldac_n (), + + .wr_eeprom_scl_o(), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), + + .wr_uart_rx (1'b0), + .wr_uart_tx (), + + .mod_pps (), + .mod_refclk (), + + // WR AXI Control + .wr_axi_aclk (), + .wr_axi_aresetn (1'b1), + .wr_axi_awaddr (), + .wr_axi_awvalid (), + .wr_axi_awready (), + .wr_axi_wdata (), + .wr_axi_wstrb (), + .wr_axi_wvalid (), + .wr_axi_wready (), + .wr_axi_bresp (), + .wr_axi_bvalid (), + .wr_axi_bready (), + .wr_axi_araddr (), + .wr_axi_arvalid (), + .wr_axi_arready (), + .wr_axi_rdata (), + .wr_axi_rresp (), + .wr_axi_rvalid (), + .wr_axi_rready (), + .wr_axi_rlast (), + + .port_info (), + .device_id (device_id), + + .link_up (qsfp_link_up), + .activity () + ); + + assign QSFP_I2C_SCL = qsfp_scl_t ? 1'bz : qsfp_scl_o; + assign qsfp_scl_i = QSFP_I2C_SCL; + assign QSFP_I2C_SDA = qsfp_sda_t ? 1'bz : qsfp_sda_o; + assign qsfp_sda_i = QSFP_I2C_SDA; + + assign QSFP_LED = |qsfp_link_up; +`else + + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_qsfp ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_NET2_AWADDR), + .s_axi_awvalid(M_AXI_NET2_AWVALID), + .s_axi_awready(M_AXI_NET2_AWREADY), + + .s_axi_wdata(M_AXI_NET2_WDATA), + .s_axi_wvalid(M_AXI_NET2_WVALID), + .s_axi_wready(M_AXI_NET2_WREADY), + + .s_axi_bresp(M_AXI_NET2_BRESP), + .s_axi_bvalid(M_AXI_NET2_BVALID), + .s_axi_bready(M_AXI_NET2_BREADY), + + .s_axi_araddr(M_AXI_NET2_ARADDR), + .s_axi_arvalid(M_AXI_NET2_ARVALID), + .s_axi_arready(M_AXI_NET2_ARREADY), + + .s_axi_rdata(M_AXI_NET2_RDATA), + .s_axi_rresp(M_AXI_NET2_RRESP), + .s_axi_rvalid(M_AXI_NET2_RVALID), + .s_axi_rready(M_AXI_NET2_RREADY) + + ); + + assign qsfp_scl_i = qsfp_scl_t ? 1'b1 : qsfp_scl_o; + assign qsfp_sda_i = qsfp_sda_t ? 1'b1 : qsfp_sda_o; + +`endif + + //-------------------------------------------------------------- + // NPIO MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef NPIO_LANES + + wire [127:0] npio_loopback_tdata; + wire [1:0] npio_loopback_tvalid; + wire [1:0] npio_loopback_tready; + wire [1:0] npio_loopback_tlast; + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h00), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd2), + .MDIO_EN (0) + ) npio_ln_0_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio0_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio0), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX0_P), + .rxn (NPIO_RX0_N), + .txp (NPIO_TX0_P), + .txn (NPIO_TX0_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio0), + .reg_rd_data (reg_rd_data_npio0), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[63:0]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[0]), + .s_axis_tlast (npio_loopback_tlast[0]), + .s_axis_tready (npio_loopback_tready[0]), + .m_axis_tdata (npio_loopback_tdata[63:0]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[0]), + .m_axis_tlast (npio_loopback_tlast[0]), + .m_axis_tready (npio_loopback_tready[0]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio0_gt_pll_lock) + ); + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h40), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd3), + .MDIO_EN (0) + ) npio_ln_1_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio1_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio1), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX1_P), + .rxn (NPIO_RX1_N), + .txp (NPIO_TX1_P), + .txn (NPIO_TX1_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio1), + .reg_rd_data (reg_rd_data_npio1), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[127:64]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[1]), + .s_axis_tlast (npio_loopback_tlast[1]), + .s_axis_tready (npio_loopback_tready[1]), + .m_axis_tdata (npio_loopback_tdata[127:64]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[1]), + .m_axis_tlast (npio_loopback_tlast[1]), + .m_axis_tready (npio_loopback_tready[1]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio1_gt_pll_lock) + ); + +`else + + assign reg_rd_resp_npio0 = 1'b0; + assign reg_rd_data_npio0 = 'h0; + assign reg_rd_resp_npio1 = 1'b0; + assign reg_rd_data_npio1 = 'h0; + assign npio0_gt_pll_lock = 1'b1; + assign npio1_gt_pll_lock = 1'b1; + assign qpllreset_npio0 = 1'b0; + assign qpllreset_npio1 = 1'b0; + +`endif + + + // ARM ethernet 0 bridge signals + wire [63:0] arm_eth0_tx_tdata; + wire arm_eth0_tx_tvalid; + wire arm_eth0_tx_tlast; + wire arm_eth0_tx_tready; + wire [3:0] arm_eth0_tx_tuser; + wire [7:0] arm_eth0_tx_tkeep; + + wire [63:0] arm_eth0_tx_tdata_b; + wire arm_eth0_tx_tvalid_b; + wire arm_eth0_tx_tlast_b; + wire arm_eth0_tx_tready_b; + wire [3:0] arm_eth0_tx_tuser_b; + wire [7:0] arm_eth0_tx_tkeep_b; + + wire [63:0] arm_eth_sfp0_tx_tdata_b; + wire arm_eth_sfp0_tx_tvalid_b; + wire arm_eth_sfp0_tx_tlast_b; + wire arm_eth_sfp0_tx_tready_b; + wire [3:0] arm_eth_sfp0_tx_tuser_b; + wire [7:0] arm_eth_sfp0_tx_tkeep_b; + + wire [63:0] arm_eth0_rx_tdata; + wire arm_eth0_rx_tvalid; + wire arm_eth0_rx_tlast; + wire arm_eth0_rx_tready; + wire [3:0] arm_eth0_rx_tuser; + wire [7:0] arm_eth0_rx_tkeep; + + wire [63:0] arm_eth0_rx_tdata_b; + wire arm_eth0_rx_tvalid_b; + wire arm_eth0_rx_tlast_b; + wire arm_eth0_rx_tready_b; + wire [3:0] arm_eth0_rx_tuser_b; + wire [7:0] arm_eth0_rx_tkeep_b; + + wire [63:0] arm_eth_sfp0_rx_tdata_b; + wire arm_eth_sfp0_rx_tvalid_b; + wire arm_eth_sfp0_rx_tlast_b; + wire arm_eth_sfp0_rx_tready_b; + wire [3:0] arm_eth_sfp0_rx_tuser_b; + wire [7:0] arm_eth_sfp0_rx_tkeep_b; + + wire arm_eth0_rx_irq; + wire arm_eth0_tx_irq; + + // ARM ethernet 1 bridge signals + wire [63:0] arm_eth1_tx_tdata; + wire arm_eth1_tx_tvalid; + wire arm_eth1_tx_tlast; + wire arm_eth1_tx_tready; + wire [3:0] arm_eth1_tx_tuser; + wire [7:0] arm_eth1_tx_tkeep; + + wire [63:0] arm_eth1_tx_tdata_b; + wire arm_eth1_tx_tvalid_b; + wire arm_eth1_tx_tlast_b; + wire arm_eth1_tx_tready_b; + wire [3:0] arm_eth1_tx_tuser_b; + wire [7:0] arm_eth1_tx_tkeep_b; + + wire [63:0] arm_eth_sfp1_tx_tdata_b; + wire arm_eth_sfp1_tx_tvalid_b; + wire arm_eth_sfp1_tx_tlast_b; + wire arm_eth_sfp1_tx_tready_b; + wire [3:0] arm_eth_sfp1_tx_tuser_b; + wire [7:0] arm_eth_sfp1_tx_tkeep_b; + + wire [63:0] arm_eth1_rx_tdata; + wire arm_eth1_rx_tvalid; + wire arm_eth1_rx_tlast; + wire arm_eth1_rx_tready; + wire [3:0] arm_eth1_rx_tuser; + wire [7:0] arm_eth1_rx_tkeep; + + wire [63:0] arm_eth1_rx_tdata_b; + wire arm_eth1_rx_tvalid_b; + wire arm_eth1_rx_tlast_b; + wire arm_eth1_rx_tready_b; + wire [3:0] arm_eth1_rx_tuser_b; + wire [7:0] arm_eth1_rx_tkeep_b; + + wire [63:0] arm_eth_sfp1_rx_tdata_b; + wire arm_eth_sfp1_rx_tvalid_b; + wire arm_eth_sfp1_rx_tlast_b; + wire arm_eth_sfp1_rx_tready_b; + wire [3:0] arm_eth_sfp1_rx_tuser_b; + wire [7:0] arm_eth_sfp1_rx_tkeep_b; + + wire arm_eth1_tx_irq; + wire arm_eth1_rx_irq; + + // Vita to Ethernet + wire [63:0] v2e0_tdata; + wire v2e0_tlast; + wire v2e0_tvalid; + wire v2e0_tready; + + wire [63:0] v2e1_tdata; + wire v2e1_tlast; + wire v2e1_tvalid; + wire v2e1_tready; + + wire [63:0] v2e_sfp0_tdata; + wire v2e_sfp0_tlast; + wire v2e_sfp0_tvalid; + wire v2e_sfp0_tready; + + wire [63:0] v2e_sfp1_tdata; + wire v2e_sfp1_tlast; + wire v2e_sfp1_tvalid; + wire v2e_sfp1_tready; + + // Ethernet to Vita + wire [63:0] e2v0_tdata; + wire e2v0_tlast; + wire e2v0_tvalid; + wire e2v0_tready; + + wire [63:0] e2v1_tdata; + wire e2v1_tlast; + wire e2v1_tvalid; + wire e2v1_tready; + + wire [63:0] e2v_sfp0_tdata; + wire e2v_sfp0_tlast; + wire e2v_sfp0_tvalid; + wire e2v_sfp0_tready; + + wire [63:0] e2v_sfp1_tdata; + wire e2v_sfp1_tlast; + wire e2v_sfp1_tvalid; + wire e2v_sfp1_tready; + + // Ethernet crossover + wire [63:0] e01_tdata, e10_tdata; + wire [3:0] e01_tuser, e10_tuser; + wire e01_tlast, e01_tvalid, e01_tready; + wire e10_tlast, e10_tvalid, e10_tready; + + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // Misc + wire [31:0] sfp_port0_info; + wire [31:0] sfp_port1_info; + wire sfp0_link_up, sfp1_link_up; + wire [15:0] device_id; + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 0: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP0_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `elsif SFP0_1GBE + .PROTOCOL("1GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_WR + .PROTOCOL("WhiteRabbit"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .GT_COMMON(1), + .PORTNUM_BASE(8'd0) + ) sfp_wrapper_0 ( + .areset(global_rst), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp0), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp0_gt_pll_lock), + + .txp(SFP_0_TX_P), + .txn(SFP_0_TX_N), + .rxp(SFP_0_RX_P), + .rxn(SFP_0_RX_N), + + .mod_present_n(SFP_0_I2C_NPRESENT), + .mod_rxlos(SFP_0_LOS), + .mod_tx_fault(SFP_0_TXFAULT), + .mod_tx_disable(SFP_0_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET0_AWVALID), + .s_axi_awready(M_AXI_NET0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET0_WDATA), + .s_axi_wstrb(M_AXI_NET0_WSTRB), + .s_axi_wvalid(M_AXI_NET0_WVALID), + .s_axi_wready(M_AXI_NET0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET0_BRESP), + .s_axi_bvalid(M_AXI_NET0_BVALID), + .s_axi_bready(M_AXI_NET0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET0_ARVALID), + .s_axi_arready(M_AXI_NET0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET0_RDATA), + .s_axi_rresp(M_AXI_NET0_RRESP), + .s_axi_rvalid(M_AXI_NET0_RVALID), + .s_axi_rready(M_AXI_NET0_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp0_tdata), + .e2v_tlast(e2v_sfp0_tlast), + .e2v_tvalid(e2v_sfp0_tvalid), + .e2v_tready(e2v_sfp0_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp0_tdata), + .v2e_tlast(v2e_sfp0_tlast), + .v2e_tvalid(v2e_sfp0_tvalid), + .v2e_tready(v2e_sfp0_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp0_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp0_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), + .e2c_tready(arm_eth_sfp0_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp0_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp0_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), + .c2e_tready(arm_eth_sfp0_tx_tready_b), + + // White Rabbit Specific +`ifdef SFP0_WR + .wr_reset_n (~ps_gpio_out[48]), // reset for WR only + .wr_refclk (wr_refclk_buf), + .wr_dac_sclk (WB_DAC_SCLK), + .wr_dac_din (WB_DAC_DIN), + .wr_dac_clr_n (WB_DAC_NCLR), + .wr_dac_cs_n (WB_DAC_NSYNC), + .wr_dac_ldac_n(WB_DAC_NLDAC), + .wr_eeprom_scl_o(), // storage for delay characterization + .wr_eeprom_scl_i(1'b0), // temp + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), // temp + .wr_uart_rx(wr_uart_rxd), // to/from PS + .wr_uart_tx(wr_uart_txd), + .mod_pps(pps_wr_refclk), // out, reference clock and pps + .mod_refclk(wr_ref_clk), + // WR Slave Port to PS + .wr_axi_aclk(m_axi_wr_clk), // out to PS + .wr_axi_aresetn(1'b1), // in + .wr_axi_awaddr(m_axi_wr_awaddr), + .wr_axi_awvalid(m_axi_wr_awvalid), + .wr_axi_awready(m_axi_wr_awready), + .wr_axi_wdata(m_axi_wr_wdata), + .wr_axi_wstrb(m_axi_wr_wstrb), + .wr_axi_wvalid(m_axi_wr_wvalid), + .wr_axi_wready(m_axi_wr_wready), + .wr_axi_bresp(m_axi_wr_bresp), + .wr_axi_bvalid(m_axi_wr_bvalid), + .wr_axi_bready(m_axi_wr_bready), + .wr_axi_araddr(m_axi_wr_araddr), + .wr_axi_arvalid(m_axi_wr_arvalid), + .wr_axi_arready(m_axi_wr_arready), + .wr_axi_rdata(m_axi_wr_rdata), + .wr_axi_rresp(m_axi_wr_rresp), + .wr_axi_rvalid(m_axi_wr_rvalid), + .wr_axi_rready(m_axi_wr_rready), + .wr_axi_rlast(), +`else + .wr_reset_n(1'b1), + .wr_refclk(1'b0), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_i(1'b0), + .wr_uart_rx(1'b0), +`endif + + // Misc + .port_info(sfp_port0_info), + .device_id(device_id), + + // LED + .link_up(sfp0_link_up), + .activity(SFP_0_LED_A) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; + assign SFP_0_LED_B = sfp0_link_up; + +`ifndef SFP0_WR + assign WB_DAC_SCLK = 1'b0; + assign WB_DAC_DIN = 1'b0; + assign WB_DAC_NCLR = 1'b1; + assign WB_DAC_NSYNC = 1'b1; + assign WB_DAC_NLDAC = 1'b1; + assign pps_wr_refclk = 1'b0; + assign wr_ref_clk = 1'b0; +`endif + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 1: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP1_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP1_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .GT_COMMON(1), + .PORTNUM_BASE(8'd1) + ) sfp_wrapper_1 ( + .areset(global_rst), + + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp1_gt_pll_lock), + + .txp(SFP_1_TX_P), + .txn(SFP_1_TX_N), + .rxp(SFP_1_RX_P), + .rxn(SFP_1_RX_N), + + .mod_rxlos(SFP_1_LOS), + .mod_tx_fault(SFP_1_TXFAULT), + .mod_tx_disable(SFP_1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET1_AWVALID), + .s_axi_awready(M_AXI_NET1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET1_WDATA), + .s_axi_wstrb(M_AXI_NET1_WSTRB), + .s_axi_wvalid(M_AXI_NET1_WVALID), + .s_axi_wready(M_AXI_NET1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET1_BRESP), + .s_axi_bvalid(M_AXI_NET1_BVALID), + .s_axi_bready(M_AXI_NET1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET1_ARVALID), + .s_axi_arready(M_AXI_NET1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET1_RDATA), + .s_axi_rresp(M_AXI_NET1_RRESP), + .s_axi_rvalid(M_AXI_NET1_RVALID), + .s_axi_rready(M_AXI_NET1_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp1_tdata), + .e2v_tlast(e2v_sfp1_tlast), + .e2v_tvalid(e2v_sfp1_tvalid), + .e2v_tready(e2v_sfp1_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp1_tdata), + .v2e_tlast(v2e_sfp1_tlast), + .v2e_tvalid(v2e_sfp1_tvalid), + .v2e_tready(v2e_sfp1_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp1_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp1_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), + .e2c_tready(arm_eth_sfp1_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp1_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp1_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), + .c2e_tready(arm_eth_sfp1_tx_tready_b), + + // Misc + .port_info(sfp_port1_info), + .device_id(device_id), + + // LED + .link_up(sfp1_link_up), + .activity(SFP_1_LED_A) + ); + + assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; + assign SFP_1_LED_B = sfp1_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 0 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth0_rx_irq; + assign IRQ_F2P[1] = arm_eth0_tx_irq; + + assign {S_AXI_HP0_AWID, S_AXI_HP0_ARID} = 12'd0; + assign {S_AXI_GP0_AWID, S_AXI_GP0_ARID} = 10'd0; + +`ifdef QSFP_10GBE + // QSFP+ lanes connect to DMA engines and crossbar + // Connect first QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[0*64 +: 64] = arm_eth0_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[0] = arm_eth0_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[0] = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_qsfp_tx_tready_b[0]; + assign arm_eth_qsfp_tx_tuser_b[0*4 +: 4] = arm_eth0_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[0*8 +: 8] = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[0*64 +: 64]; + assign arm_eth0_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[0]; + assign arm_eth0_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[0]; + assign arm_eth_qsfp_rx_tready_b[0] = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[0*4 +: 4]; + assign arm_eth0_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[0*8 +: 8]; + + // Connect first QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[0*64 +: 64] = v2e0_tdata; + assign v2e_qsfp_tlast[0] = v2e0_tlast; + assign v2e_qsfp_tvalid[0] = v2e0_tvalid; + assign v2e0_tready = v2e_qsfp_tready[0]; + + assign e2v0_tdata = e2v_qsfp_tdata[0*64 +: 64]; + assign e2v0_tlast = e2v_qsfp_tlast[0]; + assign e2v0_tvalid = e2v_qsfp_tvalid[0]; + assign e2v_qsfp_tready[0] = e2v0_tready; + + // Connect second QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[1*64 +: 64] = arm_eth1_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[1] = arm_eth1_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[1] = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_qsfp_tx_tready_b[1]; + assign arm_eth_qsfp_tx_tuser_b[1*4 +: 4] = arm_eth1_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[1*8 +: 8] = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[1*64 +: 64]; + assign arm_eth1_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[1]; + assign arm_eth1_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[1]; + assign arm_eth_qsfp_rx_tready_b[1] = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[1*4 +: 4]; + assign arm_eth1_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[1*8 +: 8]; + + // Connect second QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[1*64 +: 64] = v2e1_tdata; + assign v2e_qsfp_tlast[1] = v2e1_tlast; + assign v2e_qsfp_tvalid[1] = v2e1_tvalid; + assign v2e1_tready = v2e_qsfp_tready[1]; + + assign e2v1_tdata = e2v_qsfp_tdata[1*64 +: 64]; + assign e2v1_tlast = e2v_qsfp_tlast[1]; + assign e2v1_tvalid = e2v_qsfp_tvalid[1]; + assign e2v_qsfp_tready[1] = e2v1_tready; +`else + // SFP+ ports connects to DMA engines and crossbar + // Connect first SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp0_tx_tdata_b = arm_eth0_tx_tdata_b; + assign arm_eth_sfp0_tx_tvalid_b = arm_eth0_tx_tvalid_b; + assign arm_eth_sfp0_tx_tlast_b = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_sfp0_tx_tready_b; + assign arm_eth_sfp0_tx_tuser_b = arm_eth0_tx_tuser_b; + assign arm_eth_sfp0_tx_tkeep_b = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_sfp0_rx_tdata_b; + assign arm_eth0_rx_tvalid_b = arm_eth_sfp0_rx_tvalid_b; + assign arm_eth0_rx_tlast_b = arm_eth_sfp0_rx_tlast_b; + assign arm_eth_sfp0_rx_tready_b = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_sfp0_rx_tuser_b; + assign arm_eth0_rx_tkeep_b = arm_eth_sfp0_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp0_tdata = v2e0_tdata; + assign v2e_sfp0_tlast = v2e0_tlast; + assign v2e_sfp0_tvalid = v2e0_tvalid; + assign v2e0_tready = v2e_sfp0_tready; + + assign e2v0_tdata = e2v_sfp0_tdata; + assign e2v0_tlast = e2v_sfp0_tlast; + assign e2v0_tvalid = e2v_sfp0_tvalid; + assign e2v_sfp0_tready = e2v0_tready; + + // Connect second SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp1_tx_tdata_b = arm_eth1_tx_tdata_b; + assign arm_eth_sfp1_tx_tvalid_b = arm_eth1_tx_tvalid_b; + assign arm_eth_sfp1_tx_tlast_b = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_sfp1_tx_tready_b; + assign arm_eth_sfp1_tx_tuser_b = arm_eth1_tx_tuser_b; + assign arm_eth_sfp1_tx_tkeep_b = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_sfp1_rx_tdata_b; + assign arm_eth1_rx_tvalid_b = arm_eth_sfp1_rx_tvalid_b; + assign arm_eth1_rx_tlast_b = arm_eth_sfp1_rx_tlast_b; + assign arm_eth_sfp1_rx_tready_b = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_sfp1_rx_tuser_b; + assign arm_eth1_rx_tkeep_b = arm_eth_sfp1_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp1_tdata = v2e1_tdata; + assign v2e_sfp1_tlast = v2e1_tlast; + assign v2e_sfp1_tvalid = v2e1_tvalid; + assign v2e1_tready = v2e_sfp1_tready; + + assign e2v1_tdata = e2v_sfp1_tdata; + assign e2v1_tlast = e2v_sfp1_tlast; + assign e2v1_tvalid = e2v_sfp1_tvalid; + assign e2v_sfp1_tready = e2v1_tready; + + // Don't actually instantiate DMA engines if protocols can't use them + `ifdef SFP0_AURORA + `define NO_ETH_DMA_0 + `elsif SFP0_WR + `define NO_ETH_DMA_0 + `endif + + `ifdef SFP1_AURORA + `define NO_ETH_DMA_1 + `endif +`endif + +`ifdef NO_ETH_DMA_0 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_sfp0_eth_dma ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_rready(M_AXI_ETH_DMA0_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP0_AWADDR = 32'h0; + assign S_AXI_GP0_AWLEN = 8'h0; + assign S_AXI_GP0_AWSIZE = 4'h0; + assign S_AXI_GP0_AWBURST = 3'h0; + assign S_AXI_GP0_AWPROT = 3'h0; + assign S_AXI_GP0_AWCACHE = 4'h0; + assign S_AXI_GP0_AWVALID = 1'b0; + //S_AXI_GP0_AWREADY output from PS + assign S_AXI_GP0_WDATA = 32'h0; + assign S_AXI_GP0_WSTRB = 4'h0; + assign S_AXI_GP0_WLAST = 1'b0; + assign S_AXI_GP0_WVALID = 1'b0; + //S_AXI_GP0_WREADY output from PS + //S_AXI_GP0_BRESP + //S_AXI_GP0_BVALID + assign S_AXI_GP0_BREADY = 1'b1; + assign S_AXI_GP0_ARADDR = 32'h0; + assign S_AXI_GP0_ARLEN = 8'h0; + assign S_AXI_GP0_ARSIZE = 3'h0; + assign S_AXI_GP0_ARBURST = 2'h0; + assign S_AXI_GP0_ARPROT = 3'h0; + assign S_AXI_GP0_ARCACHE = 4'h0; + assign S_AXI_GP0_ARVALID = 1'b0; + //S_AXI_GP0_ARREADY + //S_AXI_GP0_RDATA + //S_AXI_GP0_RRESP + //S_AXI_GP0_RLAST + //S_AXI_GP0_RVALID + assign S_AXI_GP0_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP0_ARADDR = 32'h0; + assign S_AXI_HP0_ARLEN = 8'h0; + assign S_AXI_HP0_ARSIZE = 3'h0; + assign S_AXI_HP0_ARBURST = 2'h0; + assign S_AXI_HP0_ARPROT = 3'h0; + assign S_AXI_HP0_ARCACHE = 4'h0; + assign S_AXI_HP0_ARVALID = 1'b0; + //S_AXI_HP0_ARREADY + //S_AXI_HP0_RDATA + //S_AXI_HP0_RRESP + //S_AXI_HP0_RLAST + //S_AXI_HP0_RVALID + assign S_AXI_HP0_RREADY = 1'b1; + assign S_AXI_HP0_AWADDR = 32'h0; + assign S_AXI_HP0_AWLEN = 8'h0; + assign S_AXI_HP0_AWSIZE = 3'h0; + assign S_AXI_HP0_AWBURST = 2'h0; + assign S_AXI_HP0_AWPROT = 3'h0; + assign S_AXI_HP0_AWCACHE = 4'h0; + assign S_AXI_HP0_AWVALID = 1'b0; + //S_AXI_HP0_AWREADY + assign S_AXI_HP0_WDATA = 64'h0; + assign S_AXI_HP0_WSTRB = 8'h0; + assign S_AXI_HP0_WLAST = 1'b0; + assign S_AXI_HP0_WVALID = 1'b0; + //S_AXI_HP0_WREADY + //S_AXI_HP0_BRESP + //S_AXI_HP0_BVALID + assign S_AXI_HP0_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma0 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA0_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP0_AWADDR), + .m_axi_sg_awlen(S_AXI_GP0_AWLEN), + .m_axi_sg_awsize(S_AXI_GP0_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP0_AWBURST), + .m_axi_sg_awprot(S_AXI_GP0_AWPROT), + .m_axi_sg_awcache(S_AXI_GP0_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP0_AWVALID), + .m_axi_sg_awready(S_AXI_GP0_AWREADY), + .m_axi_sg_wdata(S_AXI_GP0_WDATA), + .m_axi_sg_wstrb(S_AXI_GP0_WSTRB), + .m_axi_sg_wlast(S_AXI_GP0_WLAST), + .m_axi_sg_wvalid(S_AXI_GP0_WVALID), + .m_axi_sg_wready(S_AXI_GP0_WREADY), + .m_axi_sg_bresp(S_AXI_GP0_BRESP), + .m_axi_sg_bvalid(S_AXI_GP0_BVALID), + .m_axi_sg_bready(S_AXI_GP0_BREADY), + .m_axi_sg_araddr(S_AXI_GP0_ARADDR), + .m_axi_sg_arlen(S_AXI_GP0_ARLEN), + .m_axi_sg_arsize(S_AXI_GP0_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP0_ARBURST), + .m_axi_sg_arprot(S_AXI_GP0_ARPROT), + .m_axi_sg_arcache(S_AXI_GP0_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP0_ARVALID), + .m_axi_sg_arready(S_AXI_GP0_ARREADY), + .m_axi_sg_rdata(S_AXI_GP0_RDATA), + .m_axi_sg_rresp(S_AXI_GP0_RRESP), + .m_axi_sg_rlast(S_AXI_GP0_RLAST), + .m_axi_sg_rvalid(S_AXI_GP0_RVALID), + .m_axi_sg_rready(S_AXI_GP0_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP0_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP0_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP0_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP0_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP0_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP0_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP0_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP0_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP0_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP0_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP0_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP0_RVALID), + .m_axi_mm2s_rready(S_AXI_HP0_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth0_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth0_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth0_tx_tvalid), + .m_axis_mm2s_tready(arm_eth0_tx_tready), + .m_axis_mm2s_tlast(arm_eth0_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP0_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP0_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP0_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP0_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP0_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP0_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP0_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP0_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP0_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP0_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP0_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP0_WVALID), + .m_axi_s2mm_wready(S_AXI_HP0_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP0_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP0_BVALID), + .m_axi_s2mm_bready(S_AXI_HP0_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth0_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth0_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth0_rx_tvalid), + .s_axis_s2mm_tready(arm_eth0_rx_tready), + .s_axis_s2mm_tlast(arm_eth0_rx_tlast), + + .mm2s_introut(arm_eth0_tx_irq), + .s2mm_introut(arm_eth0_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_0_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth0_tx_tlast, arm_eth0_tx_tkeep, arm_eth0_tx_tdata}), + .i_tvalid(arm_eth0_tx_tvalid), + .i_tready(arm_eth0_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth0_tx_tlast_b, arm_eth0_tx_tkeep_b, arm_eth0_tx_tdata_b}), + .o_tvalid(arm_eth0_tx_tvalid_b), + .o_tready(arm_eth0_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_0_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth0_rx_tlast_b, arm_eth0_rx_tkeep_b, arm_eth0_rx_tdata_b}), + .i_tvalid(arm_eth0_rx_tvalid_b), + .i_tready(arm_eth0_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth0_rx_tlast, arm_eth0_rx_tkeep, arm_eth0_rx_tdata}), + .o_tvalid(arm_eth0_rx_tvalid), + .o_tready(arm_eth0_rx_tready) + ); + +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 1 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[2] = arm_eth1_rx_irq; + assign IRQ_F2P[3] = arm_eth1_tx_irq; + + assign {S_AXI_HP1_AWID, S_AXI_HP1_ARID} = 12'd0; + assign {S_AXI_GP1_AWID, S_AXI_GP1_ARID} = 10'd0; + +`ifdef NO_ETH_DMA_1 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #(.DEC_ERR(1'b0)) inst_axi_dummy_sfp1_eth_dma + ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_rready(M_AXI_ETH_DMA1_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP1_AWADDR = 32'h0; + assign S_AXI_GP1_AWLEN = 8'h0; + assign S_AXI_GP1_AWSIZE = 4'h0; + assign S_AXI_GP1_AWBURST = 3'h0; + assign S_AXI_GP1_AWPROT = 3'h0; + assign S_AXI_GP1_AWCACHE = 4'h0; + assign S_AXI_GP1_AWVALID = 1'b0; + //S_AXI_GP1_AWREADY output from PS + assign S_AXI_GP1_WDATA = 32'h0; + assign S_AXI_GP1_WSTRB = 4'h0; + assign S_AXI_GP1_WLAST = 1'b0; + assign S_AXI_GP1_WVALID = 1'b0; + //S_AXI_GP1_WREADY output from PS + //S_AXI_GP1_BRESP + //S_AXI_GP1_BVALID + assign S_AXI_GP1_BREADY = 1'b1; + assign S_AXI_GP1_ARADDR = 32'h0; + assign S_AXI_GP1_ARLEN = 8'h0; + assign S_AXI_GP1_ARSIZE = 3'h0; + assign S_AXI_GP1_ARBURST = 2'h0; + assign S_AXI_GP1_ARPROT = 3'h0; + assign S_AXI_GP1_ARCACHE = 4'h0; + assign S_AXI_GP1_ARVALID = 1'b0; + //S_AXI_GP1_ARREADY + //S_AXI_GP1_RDATA + //S_AXI_GP1_RRESP + //S_AXI_GP1_RLAST + //S_AXI_GP1_RVALID + assign S_AXI_GP1_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP1_ARADDR = 32'h0; + assign S_AXI_HP1_ARLEN = 8'h0; + assign S_AXI_HP1_ARSIZE = 3'h0; + assign S_AXI_HP1_ARBURST = 2'h0; + assign S_AXI_HP1_ARPROT = 3'h0; + assign S_AXI_HP1_ARCACHE = 4'h0; + assign S_AXI_HP1_ARVALID = 1'b0; + //S_AXI_HP1_ARREADY + //S_AXI_HP1_RDATA + //S_AXI_HP1_RRESP + //S_AXI_HP1_RLAST + //S_AXI_HP1_RVALID + assign S_AXI_HP1_RREADY = 1'b1; + assign S_AXI_HP1_AWADDR = 32'h0; + assign S_AXI_HP1_AWLEN = 8'h0; + assign S_AXI_HP1_AWSIZE = 3'h0; + assign S_AXI_HP1_AWBURST = 2'h0; + assign S_AXI_HP1_AWPROT = 3'h0; + assign S_AXI_HP1_AWCACHE = 4'h0; + assign S_AXI_HP1_AWVALID = 1'b0; + //S_AXI_HP1_AWREADY + assign S_AXI_HP1_WDATA = 64'h0; + assign S_AXI_HP1_WSTRB = 8'h0; + assign S_AXI_HP1_WLAST = 1'b0; + assign S_AXI_HP1_WVALID = 1'b0; + //S_AXI_HP1_WREADY + //S_AXI_HP1_BRESP + //S_AXI_HP1_BVALID + assign S_AXI_HP1_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma1 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA1_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP1_AWADDR), + .m_axi_sg_awlen(S_AXI_GP1_AWLEN), + .m_axi_sg_awsize(S_AXI_GP1_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP1_AWBURST), + .m_axi_sg_awprot(S_AXI_GP1_AWPROT), + .m_axi_sg_awcache(S_AXI_GP1_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP1_AWVALID), + .m_axi_sg_awready(S_AXI_GP1_AWREADY), + .m_axi_sg_wdata(S_AXI_GP1_WDATA), + .m_axi_sg_wstrb(S_AXI_GP1_WSTRB), + .m_axi_sg_wlast(S_AXI_GP1_WLAST), + .m_axi_sg_wvalid(S_AXI_GP1_WVALID), + .m_axi_sg_wready(S_AXI_GP1_WREADY), + .m_axi_sg_bresp(S_AXI_GP1_BRESP), + .m_axi_sg_bvalid(S_AXI_GP1_BVALID), + .m_axi_sg_bready(S_AXI_GP1_BREADY), + .m_axi_sg_araddr(S_AXI_GP1_ARADDR), + .m_axi_sg_arlen(S_AXI_GP1_ARLEN), + .m_axi_sg_arsize(S_AXI_GP1_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP1_ARBURST), + .m_axi_sg_arprot(S_AXI_GP1_ARPROT), + .m_axi_sg_arcache(S_AXI_GP1_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP1_ARVALID), + .m_axi_sg_arready(S_AXI_GP1_ARREADY), + .m_axi_sg_rdata(S_AXI_GP1_RDATA), + .m_axi_sg_rresp(S_AXI_GP1_RRESP), + .m_axi_sg_rlast(S_AXI_GP1_RLAST), + .m_axi_sg_rvalid(S_AXI_GP1_RVALID), + .m_axi_sg_rready(S_AXI_GP1_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP1_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP1_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP1_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP1_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP1_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP1_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP1_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP1_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP1_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP1_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP1_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP1_RVALID), + .m_axi_mm2s_rready(S_AXI_HP1_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth1_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth1_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth1_tx_tvalid), + .m_axis_mm2s_tready(arm_eth1_tx_tready), + .m_axis_mm2s_tlast(arm_eth1_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP1_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP1_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP1_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP1_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP1_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP1_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP1_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP1_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP1_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP1_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP1_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP1_WVALID), + .m_axi_s2mm_wready(S_AXI_HP1_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP1_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP1_BVALID), + .m_axi_s2mm_bready(S_AXI_HP1_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth1_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth1_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth1_rx_tvalid), + .s_axis_s2mm_tready(arm_eth1_rx_tready), + .s_axis_s2mm_tlast(arm_eth1_rx_tlast), + + .mm2s_introut(arm_eth1_tx_irq), + .s2mm_introut(arm_eth1_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_1_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth1_tx_tlast, arm_eth1_tx_tkeep, arm_eth1_tx_tdata}), + .i_tvalid(arm_eth1_tx_tvalid), + .i_tready(arm_eth1_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth1_tx_tlast_b, arm_eth1_tx_tkeep_b, arm_eth1_tx_tdata_b}), + .o_tvalid(arm_eth1_tx_tvalid_b), + .o_tready(arm_eth1_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_1_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth1_rx_tlast_b, arm_eth1_rx_tkeep_b, arm_eth1_rx_tdata_b}), + .i_tvalid(arm_eth1_rx_tvalid_b), + .i_tready(arm_eth1_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth1_rx_tlast, arm_eth1_rx_tkeep, arm_eth1_rx_tdata}), + .o_tvalid(arm_eth1_rx_tvalid), + .o_tready(arm_eth1_rx_tready) + ); +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Processing System + // + ////////////////////////////////////////////////////////////////////// + + wire spi0_sclk; + wire spi0_mosi; + wire spi0_miso; + wire spi0_ss0; + wire spi0_ss1; + wire spi0_ss2; + wire spi1_sclk; + wire spi1_mosi; + wire spi1_miso; + wire spi1_ss0; + wire spi1_ss1; + wire spi1_ss2; + + assign DBA_MODULE_PWR_ENABLE = ps_gpio_out[8]; + assign DBA_RF_PWR_ENABLE = ps_gpio_out[9]; + assign DBB_MODULE_PWR_ENABLE = ps_gpio_out[10]; + assign DBB_RF_PWR_ENABLE = ps_gpio_out[11]; + assign ps_gpio_in[8] = DBA_MODULE_PWR_ENABLE; + assign ps_gpio_in[9] = DBA_RF_PWR_ENABLE; + assign ps_gpio_in[10] = DBB_MODULE_PWR_ENABLE; + assign ps_gpio_in[11] = DBB_RF_PWR_ENABLE; + + // Processing System + n310_ps_bd inst_n310_ps ( + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(spi0_sclk), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(spi0_mosi), + .SPI0_MOSI_T(), + .SPI0_MISO_I(spi0_miso), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(spi0_ss0), + .SPI0_SS1_O(spi0_ss1), + .SPI0_SS2_O(spi0_ss2), + .SPI0_SS_T(), + + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(spi1_sclk), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(spi1_mosi), + .SPI1_MOSI_T(), + .SPI1_MISO_I(spi1_miso), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(spi1_ss0), + .SPI1_SS1_O(spi1_ss1), + .SPI1_SS2_O(spi1_ss2), + .SPI1_SS_T(), + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + + .M_AXI_ETH_DMA0_araddr(M_AXI_ETH_DMA0_ARADDR), + .M_AXI_ETH_DMA0_arprot(), + .M_AXI_ETH_DMA0_arready(M_AXI_ETH_DMA0_ARREADY), + .M_AXI_ETH_DMA0_arvalid(M_AXI_ETH_DMA0_ARVALID), + + .M_AXI_ETH_DMA0_awaddr(M_AXI_ETH_DMA0_AWADDR), + .M_AXI_ETH_DMA0_awprot(), + .M_AXI_ETH_DMA0_awready(M_AXI_ETH_DMA0_AWREADY), + .M_AXI_ETH_DMA0_awvalid(M_AXI_ETH_DMA0_AWVALID), + + .M_AXI_ETH_DMA0_wdata(M_AXI_ETH_DMA0_WDATA), + .M_AXI_ETH_DMA0_wready(M_AXI_ETH_DMA0_WREADY), + .M_AXI_ETH_DMA0_wstrb(M_AXI_ETH_DMA0_WSTRB), + .M_AXI_ETH_DMA0_wvalid(M_AXI_ETH_DMA0_WVALID), + + .M_AXI_ETH_DMA0_rdata(M_AXI_ETH_DMA0_RDATA), + .M_AXI_ETH_DMA0_rready(M_AXI_ETH_DMA0_RREADY), + .M_AXI_ETH_DMA0_rresp(M_AXI_ETH_DMA0_RRESP), + .M_AXI_ETH_DMA0_rvalid(M_AXI_ETH_DMA0_RVALID), + + .M_AXI_ETH_DMA0_bready(M_AXI_ETH_DMA0_BREADY), + .M_AXI_ETH_DMA0_bresp(M_AXI_ETH_DMA0_BRESP), + .M_AXI_ETH_DMA0_bvalid(M_AXI_ETH_DMA0_BVALID), + + .M_AXI_ETH_DMA1_araddr(M_AXI_ETH_DMA1_ARADDR), + .M_AXI_ETH_DMA1_arprot(), + .M_AXI_ETH_DMA1_arready(M_AXI_ETH_DMA1_ARREADY), + .M_AXI_ETH_DMA1_arvalid(M_AXI_ETH_DMA1_ARVALID), + + .M_AXI_ETH_DMA1_awaddr(M_AXI_ETH_DMA1_AWADDR), + .M_AXI_ETH_DMA1_awprot(), + .M_AXI_ETH_DMA1_awready(M_AXI_ETH_DMA1_AWREADY), + .M_AXI_ETH_DMA1_awvalid(M_AXI_ETH_DMA1_AWVALID), + + .M_AXI_ETH_DMA1_bready(M_AXI_ETH_DMA1_BREADY), + .M_AXI_ETH_DMA1_bresp(M_AXI_ETH_DMA1_BRESP), + .M_AXI_ETH_DMA1_bvalid(M_AXI_ETH_DMA1_BVALID), + + .M_AXI_ETH_DMA1_rdata(M_AXI_ETH_DMA1_RDATA), + .M_AXI_ETH_DMA1_rready(M_AXI_ETH_DMA1_RREADY), + .M_AXI_ETH_DMA1_rresp(M_AXI_ETH_DMA1_RRESP), + .M_AXI_ETH_DMA1_rvalid(M_AXI_ETH_DMA1_RVALID), + + .M_AXI_ETH_DMA1_wdata(M_AXI_ETH_DMA1_WDATA), + .M_AXI_ETH_DMA1_wready(M_AXI_ETH_DMA1_WREADY), + .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB), + .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID), + + .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR), + .M_AXI_JESD0_arprot(), + .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY), + .M_AXI_JESD0_arvalid(M_AXI_JESD0_ARVALID), + + .M_AXI_JESD0_awaddr(M_AXI_JESD0_AWADDR), + .M_AXI_JESD0_awprot(), + .M_AXI_JESD0_awready(M_AXI_JESD0_AWREADY), + .M_AXI_JESD0_awvalid(M_AXI_JESD0_AWVALID), + + .M_AXI_JESD0_bready(M_AXI_JESD0_BREADY), + .M_AXI_JESD0_bresp(M_AXI_JESD0_BRESP), + .M_AXI_JESD0_bvalid(M_AXI_JESD0_BVALID), + + .M_AXI_JESD0_rdata(M_AXI_JESD0_RDATA), + .M_AXI_JESD0_rready(M_AXI_JESD0_RREADY), + .M_AXI_JESD0_rresp(M_AXI_JESD0_RRESP), + .M_AXI_JESD0_rvalid(M_AXI_JESD0_RVALID), + + .M_AXI_JESD0_wdata(M_AXI_JESD0_WDATA), + .M_AXI_JESD0_wready(M_AXI_JESD0_WREADY), + .M_AXI_JESD0_wstrb(M_AXI_JESD0_WSTRB), + .M_AXI_JESD0_wvalid(M_AXI_JESD0_WVALID), + + .M_AXI_JESD1_araddr(M_AXI_JESD1_ARADDR), + .M_AXI_JESD1_arprot(), + .M_AXI_JESD1_arready(M_AXI_JESD1_ARREADY), + .M_AXI_JESD1_arvalid(M_AXI_JESD1_ARVALID), + + .M_AXI_JESD1_awaddr(M_AXI_JESD1_AWADDR), + .M_AXI_JESD1_awprot(), + .M_AXI_JESD1_awready(M_AXI_JESD1_AWREADY), + .M_AXI_JESD1_awvalid(M_AXI_JESD1_AWVALID), + + .M_AXI_JESD1_bready(M_AXI_JESD1_BREADY), + .M_AXI_JESD1_bresp(M_AXI_JESD1_BRESP), + .M_AXI_JESD1_bvalid(M_AXI_JESD1_BVALID), + + .M_AXI_JESD1_rdata(M_AXI_JESD1_RDATA), + .M_AXI_JESD1_rready(M_AXI_JESD1_RREADY), + .M_AXI_JESD1_rresp(M_AXI_JESD1_RRESP), + .M_AXI_JESD1_rvalid(M_AXI_JESD1_RVALID), + + .M_AXI_JESD1_wdata(M_AXI_JESD1_WDATA), + .M_AXI_JESD1_wready(M_AXI_JESD1_WREADY), + .M_AXI_JESD1_wstrb(M_AXI_JESD1_WSTRB), + .M_AXI_JESD1_wvalid(M_AXI_JESD1_WVALID), + + .M_AXI_NET0_araddr(M_AXI_NET0_ARADDR), + .M_AXI_NET0_arprot(), + .M_AXI_NET0_arready(M_AXI_NET0_ARREADY), + .M_AXI_NET0_arvalid(M_AXI_NET0_ARVALID), + + .M_AXI_NET0_awaddr(M_AXI_NET0_AWADDR), + .M_AXI_NET0_awprot(), + .M_AXI_NET0_awready(M_AXI_NET0_AWREADY), + .M_AXI_NET0_awvalid(M_AXI_NET0_AWVALID), + + .M_AXI_NET0_bready(M_AXI_NET0_BREADY), + .M_AXI_NET0_bresp(M_AXI_NET0_BRESP), + .M_AXI_NET0_bvalid(M_AXI_NET0_BVALID), + + .M_AXI_NET0_rdata(M_AXI_NET0_RDATA), + .M_AXI_NET0_rready(M_AXI_NET0_RREADY), + .M_AXI_NET0_rresp(M_AXI_NET0_RRESP), + .M_AXI_NET0_rvalid(M_AXI_NET0_RVALID), + + .M_AXI_NET0_wdata(M_AXI_NET0_WDATA), + .M_AXI_NET0_wready(M_AXI_NET0_WREADY), + .M_AXI_NET0_wstrb(M_AXI_NET0_WSTRB), + .M_AXI_NET0_wvalid(M_AXI_NET0_WVALID), + + .M_AXI_NET1_araddr(M_AXI_NET1_ARADDR), + .M_AXI_NET1_arprot(), + .M_AXI_NET1_arready(M_AXI_NET1_ARREADY), + .M_AXI_NET1_arvalid(M_AXI_NET1_ARVALID), + + .M_AXI_NET1_awaddr(M_AXI_NET1_AWADDR), + .M_AXI_NET1_awprot(), + .M_AXI_NET1_awready(M_AXI_NET1_AWREADY), + .M_AXI_NET1_awvalid(M_AXI_NET1_AWVALID), + + .M_AXI_NET1_bready(M_AXI_NET1_BREADY), + .M_AXI_NET1_bresp(M_AXI_NET1_BRESP), + .M_AXI_NET1_bvalid(M_AXI_NET1_BVALID), + + .M_AXI_NET1_rdata(M_AXI_NET1_RDATA), + .M_AXI_NET1_rready(M_AXI_NET1_RREADY), + .M_AXI_NET1_rresp(M_AXI_NET1_RRESP), + .M_AXI_NET1_rvalid(M_AXI_NET1_RVALID), + + .M_AXI_NET1_wdata(M_AXI_NET1_WDATA), + .M_AXI_NET1_wready(M_AXI_NET1_WREADY), + .M_AXI_NET1_wstrb(M_AXI_NET1_WSTRB), + .M_AXI_NET1_wvalid(M_AXI_NET1_WVALID), + + .M_AXI_NET2_araddr(M_AXI_NET2_ARADDR), + .M_AXI_NET2_arprot(), + .M_AXI_NET2_arready(M_AXI_NET2_ARREADY), + .M_AXI_NET2_arvalid(M_AXI_NET2_ARVALID), + + .M_AXI_NET2_awaddr(M_AXI_NET2_AWADDR), + .M_AXI_NET2_awprot(), + .M_AXI_NET2_awready(M_AXI_NET2_AWREADY), + .M_AXI_NET2_awvalid(M_AXI_NET2_AWVALID), + + .M_AXI_NET2_bready(M_AXI_NET2_BREADY), + .M_AXI_NET2_bresp(M_AXI_NET2_BRESP), + .M_AXI_NET2_bvalid(M_AXI_NET2_BVALID), + + .M_AXI_NET2_rdata(M_AXI_NET2_RDATA), + .M_AXI_NET2_rready(M_AXI_NET2_RREADY), + .M_AXI_NET2_rresp(M_AXI_NET2_RRESP), + .M_AXI_NET2_rvalid(M_AXI_NET2_RVALID), + + .M_AXI_NET2_wdata(M_AXI_NET2_WDATA), + .M_AXI_NET2_wready(M_AXI_NET2_WREADY), + .M_AXI_NET2_wstrb(M_AXI_NET2_WSTRB), + .M_AXI_NET2_wvalid(M_AXI_NET2_WVALID), + + .M_AXI_WR_CLK(m_axi_wr_clk), + .M_AXI_WR_RSTn(1'b1), + .M_AXI_WR_araddr(m_axi_wr_araddr), + .M_AXI_WR_arready(m_axi_wr_arready), + .M_AXI_WR_arvalid(m_axi_wr_arvalid), + .M_AXI_WR_arprot(), + .M_AXI_WR_awaddr(m_axi_wr_awaddr), + .M_AXI_WR_awready(m_axi_wr_awready), + .M_AXI_WR_awvalid(m_axi_wr_awvalid), + .M_AXI_WR_awprot(), + .M_AXI_WR_bready(m_axi_wr_bready), + .M_AXI_WR_bresp(m_axi_wr_bresp), + .M_AXI_WR_bvalid(m_axi_wr_bvalid), + .M_AXI_WR_rdata(m_axi_wr_rdata), + .M_AXI_WR_rready(m_axi_wr_rready), + .M_AXI_WR_rresp(m_axi_wr_rresp), + .M_AXI_WR_rvalid(m_axi_wr_rvalid), + .M_AXI_WR_wdata(m_axi_wr_wdata), + .M_AXI_WR_wready(m_axi_wr_wready), + .M_AXI_WR_wstrb(m_axi_wr_wstrb), + .M_AXI_WR_wvalid(m_axi_wr_wvalid), + + .M_AXI_XBAR_araddr(M_AXI_XBAR_ARADDR), + .M_AXI_XBAR_arprot(), + .M_AXI_XBAR_arready(M_AXI_XBAR_ARREADY), + .M_AXI_XBAR_arvalid(M_AXI_XBAR_ARVALID), + + .M_AXI_XBAR_awaddr(M_AXI_XBAR_AWADDR), + .M_AXI_XBAR_awprot(), + .M_AXI_XBAR_awready(M_AXI_XBAR_AWREADY), + .M_AXI_XBAR_awvalid(M_AXI_XBAR_AWVALID), + + .M_AXI_XBAR_bready(M_AXI_XBAR_BREADY), + .M_AXI_XBAR_bresp(M_AXI_XBAR_BRESP), + .M_AXI_XBAR_bvalid(M_AXI_XBAR_BVALID), + + .M_AXI_XBAR_rdata(M_AXI_XBAR_RDATA), + .M_AXI_XBAR_rready(M_AXI_XBAR_RREADY), + .M_AXI_XBAR_rresp(M_AXI_XBAR_RRESP), + .M_AXI_XBAR_rvalid(M_AXI_XBAR_RVALID), + + .M_AXI_XBAR_wdata(M_AXI_XBAR_WDATA), + .M_AXI_XBAR_wready(M_AXI_XBAR_WREADY), + .M_AXI_XBAR_wstrb(M_AXI_XBAR_WSTRB), + .M_AXI_XBAR_wvalid(M_AXI_XBAR_WVALID), + + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR), + .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST), + .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE), + .S_AXI_GP0_arid(S_AXI_GP0_ARID), + .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN), + .S_AXI_GP0_arlock(1'b0), + .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT), + .S_AXI_GP0_arqos(4'b0000), + .S_AXI_GP0_arready(S_AXI_GP0_ARREADY), + .S_AXI_GP0_arregion(4'b0000), + .S_AXI_GP0_arsize(S_AXI_GP0_ARSIZE), + .S_AXI_GP0_arvalid(S_AXI_GP0_ARVALID), + .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR), + .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST), + .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE), + .S_AXI_GP0_awid(S_AXI_GP0_AWID), + .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN), + .S_AXI_GP0_awlock(1'b0), + .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT), + .S_AXI_GP0_awqos(4'b0000), + .S_AXI_GP0_awregion(4'b0000), + .S_AXI_GP0_awready(S_AXI_GP0_AWREADY), + .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE), + .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID), + .S_AXI_GP0_bid(), + .S_AXI_GP0_bready(S_AXI_GP0_BREADY), + .S_AXI_GP0_bresp(S_AXI_GP0_BRESP), + .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID), + .S_AXI_GP0_rdata(S_AXI_GP0_RDATA), + .S_AXI_GP0_rid(), + .S_AXI_GP0_rlast(S_AXI_GP0_RLAST), + .S_AXI_GP0_rready(S_AXI_GP0_RREADY), + .S_AXI_GP0_rresp(S_AXI_GP0_RRESP), + .S_AXI_GP0_rvalid(S_AXI_GP0_RVALID), + .S_AXI_GP0_wdata(S_AXI_GP0_WDATA), + .S_AXI_GP0_wlast(S_AXI_GP0_WLAST), + .S_AXI_GP0_wready(S_AXI_GP0_WREADY), + .S_AXI_GP0_wstrb(S_AXI_GP0_WSTRB), + .S_AXI_GP0_wvalid(S_AXI_GP0_WVALID), + + .S_AXI_GP1_ACLK(clk40), + .S_AXI_GP1_ARESETN(clk40_rstn), + .S_AXI_GP1_araddr(S_AXI_GP1_ARADDR), + .S_AXI_GP1_arburst(S_AXI_GP1_ARBURST), + .S_AXI_GP1_arcache(S_AXI_GP1_ARCACHE), + .S_AXI_GP1_arid(S_AXI_GP1_ARID), + .S_AXI_GP1_arlen(S_AXI_GP1_ARLEN), + .S_AXI_GP1_arlock(1'b0), + .S_AXI_GP1_arprot(S_AXI_GP1_ARPROT), + .S_AXI_GP1_arqos(4'b000), + .S_AXI_GP1_arregion(4'b0000), + .S_AXI_GP1_arready(S_AXI_GP1_ARREADY), + .S_AXI_GP1_arsize(S_AXI_GP1_ARSIZE), + .S_AXI_GP1_arvalid(S_AXI_GP1_ARVALID), + .S_AXI_GP1_awaddr(S_AXI_GP1_AWADDR), + .S_AXI_GP1_awburst(S_AXI_GP1_AWBURST), + .S_AXI_GP1_awcache(S_AXI_GP1_AWCACHE), + .S_AXI_GP1_awid(S_AXI_GP1_AWID), + .S_AXI_GP1_awlen(S_AXI_GP1_AWLEN), + .S_AXI_GP1_awlock(1'b0), + .S_AXI_GP1_awprot(S_AXI_GP1_AWPROT), + .S_AXI_GP1_awqos(4'b0000), + .S_AXI_GP1_awregion(4'b0000), + .S_AXI_GP1_awready(S_AXI_GP1_AWREADY), + .S_AXI_GP1_awsize(S_AXI_GP1_AWSIZE), + .S_AXI_GP1_awvalid(S_AXI_GP1_AWVALID), + .S_AXI_GP1_bid(), + .S_AXI_GP1_bready(S_AXI_GP1_BREADY), + .S_AXI_GP1_bresp(S_AXI_GP1_BRESP), + .S_AXI_GP1_bvalid(S_AXI_GP1_BVALID), + .S_AXI_GP1_rdata(S_AXI_GP1_RDATA), + .S_AXI_GP1_rid(), + .S_AXI_GP1_rlast(S_AXI_GP1_RLAST), + .S_AXI_GP1_rready(S_AXI_GP1_RREADY), + .S_AXI_GP1_rresp(S_AXI_GP1_RRESP), + .S_AXI_GP1_rvalid(S_AXI_GP1_RVALID), + .S_AXI_GP1_wdata(S_AXI_GP1_WDATA), + .S_AXI_GP1_wlast(S_AXI_GP1_WLAST), + .S_AXI_GP1_wready(S_AXI_GP1_WREADY), + .S_AXI_GP1_wstrb(S_AXI_GP1_WSTRB), + .S_AXI_GP1_wvalid(S_AXI_GP1_WVALID), + + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR), + .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST), + .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_arid(S_AXI_HP0_ARID), + .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT), + .S_AXI_HP0_arqos(4'b0000), + .S_AXI_HP0_arready(S_AXI_HP0_ARREADY), + .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID), + .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR), + .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST), + .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_awid(S_AXI_HP0_AWID), + .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT), + .S_AXI_HP0_awqos(4'b0000), + .S_AXI_HP0_awready(S_AXI_HP0_AWREADY), + .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(S_AXI_HP0_BREADY), + .S_AXI_HP0_bresp(S_AXI_HP0_BRESP), + .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID), + .S_AXI_HP0_rdata(S_AXI_HP0_RDATA), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(S_AXI_HP0_RLAST), + .S_AXI_HP0_rready(S_AXI_HP0_RREADY), + .S_AXI_HP0_rresp(S_AXI_HP0_RRESP), + .S_AXI_HP0_rvalid(S_AXI_HP0_RVALID), + .S_AXI_HP0_wdata(S_AXI_HP0_WDATA), + .S_AXI_HP0_wlast(S_AXI_HP0_WLAST), + .S_AXI_HP0_wready(S_AXI_HP0_WREADY), + .S_AXI_HP0_wstrb(S_AXI_HP0_WSTRB), + .S_AXI_HP0_wvalid(S_AXI_HP0_WVALID), + + .S_AXI_HP1_ACLK(clk40), + .S_AXI_HP1_ARESETN(clk40_rstn), + .S_AXI_HP1_araddr(S_AXI_HP1_ARADDR), + .S_AXI_HP1_arburst(S_AXI_HP1_ARBURST), + .S_AXI_HP1_arcache(S_AXI_HP1_ARCACHE), + .S_AXI_HP1_arid(S_AXI_HP1_ARID), + .S_AXI_HP1_arlen(S_AXI_HP1_ARLEN), + .S_AXI_HP1_arlock(1'b0), + .S_AXI_HP1_arprot(S_AXI_HP1_ARPROT), + .S_AXI_HP1_arqos(4'b0000), + .S_AXI_HP1_arready(S_AXI_HP1_ARREADY), + .S_AXI_HP1_arsize(S_AXI_HP1_ARSIZE), + .S_AXI_HP1_arvalid(S_AXI_HP1_ARVALID), + .S_AXI_HP1_awaddr(S_AXI_HP1_AWADDR), + .S_AXI_HP1_awburst(S_AXI_HP1_AWBURST), + .S_AXI_HP1_awcache(S_AXI_HP1_AWCACHE), + .S_AXI_HP1_awid(S_AXI_HP1_AWID), + .S_AXI_HP1_awlen(S_AXI_HP1_AWLEN), + .S_AXI_HP1_awlock(1'b0), + .S_AXI_HP1_awprot(S_AXI_HP1_AWPROT), + .S_AXI_HP1_awqos(4'b0000), + .S_AXI_HP1_awready(S_AXI_HP1_AWREADY), + .S_AXI_HP1_awsize(S_AXI_HP1_AWSIZE), + .S_AXI_HP1_awvalid(S_AXI_HP1_AWVALID), + .S_AXI_HP1_bid(), + .S_AXI_HP1_bready(S_AXI_HP1_BREADY), + .S_AXI_HP1_bresp(S_AXI_HP1_BRESP), + .S_AXI_HP1_bvalid(S_AXI_HP1_BVALID), + .S_AXI_HP1_rdata(S_AXI_HP1_RDATA), + .S_AXI_HP1_rid(), + .S_AXI_HP1_rlast(S_AXI_HP1_RLAST), + .S_AXI_HP1_rready(S_AXI_HP1_RREADY), + .S_AXI_HP1_rresp(S_AXI_HP1_RRESP), + .S_AXI_HP1_rvalid(S_AXI_HP1_RVALID), + .S_AXI_HP1_wdata(S_AXI_HP1_WDATA), + .S_AXI_HP1_wlast(S_AXI_HP1_WLAST), + .S_AXI_HP1_wready(S_AXI_HP1_WREADY), + .S_AXI_HP1_wstrb(S_AXI_HP1_WSTRB), + .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID), + + // ARM DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid), + + // Misc Interrupts, GPIO, clk + .IRQ_F2P(IRQ_F2P), + + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + .JTAG0_TCK(DBA_CPLD_JTAG_TCK), + .JTAG0_TMS(DBA_CPLD_JTAG_TMS), + .JTAG0_TDI(DBA_CPLD_JTAG_TDI), + .JTAG0_TDO(DBA_CPLD_JTAG_TDO), + + .JTAG1_TCK(DBB_CPLD_JTAG_TCK), + .JTAG1_TMS(DBB_CPLD_JTAG_TMS), + .JTAG1_TDI(DBB_CPLD_JTAG_TDI), + .JTAG1_TDO(DBB_CPLD_JTAG_TDO), + + .FCLK_CLK0(FCLK_CLK0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_RESET1_N(), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_RESET2_N(), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET3_N(), + + .WR_UART_txd(wr_uart_rxd), // rx <-> tx + .WR_UART_rxd(wr_uart_txd), // rx <-> tx + + .qsfp_sda_i(qsfp_sda_i), + .qsfp_sda_o(qsfp_sda_o), + .qsfp_sda_t(qsfp_sda_t), + .qsfp_scl_i(qsfp_scl_i), + .qsfp_scl_o(qsfp_scl_o), + .qsfp_scl_t(qsfp_scl_t), + + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + // Outward connections to the pins + .MIO(MIO), + .DDR_cas_n(DDR_CAS_n), + .DDR_cke(DDR_CKE), + .DDR_ck_n(DDR_Clk_n), + .DDR_ck_p(DDR_Clk), + .DDR_cs_n(DDR_CS_n), + .DDR_reset_n(DDR_DRSTB), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_n), + .DDR_we_n(DDR_WEB), + .DDR_ba(DDR_BankAddr), + .DDR_addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_n), + .DDR_dqs_p(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); + + /////////////////////////////////////////////////////////////////////////////////// + // + // Xilinx DDR3 Controller and PHY. + // + /////////////////////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (200MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + + // Instantiate the DDR3 MIG core + // + // The top-level IP block has no parameters defined for some reason. + // Most of configurable parameters are hard-coded in the mig so get + // some additional knobs we pull those out into verilog headers. + // + // Synthesis params: ip/ddr3_32bit/ddr3_32bit_mig_parameters.vh + // Simulation params: ip/ddr3_32bit/ddr3_32bit_mig_sim_parameters.vh + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 200Hz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 200 MHz. + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + + .sys_rst (~global_rst) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL("INTERNAL"), + .XADC_CLK_PERIOD(5000 /* 200MHz clock period in ps */) + ) tempmon_i ( + .clk(bus_clk), .xadc_clk(bus_clk), .rst(bus_rst), + .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) + ); + + /////////////////////////////////////////////////////// + // + // DB PS SPI Connections + // + /////////////////////////////////////////////////////// + wire [NUM_CHANNELS-1:0] rx_atr; + wire [NUM_CHANNELS-1:0] tx_atr; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] rx_atr_reg; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] tx_atr_reg; + + // Radio GPIO control for DSA + wire [16*NUM_CHANNELS-1:0] db_gpio_out; + wire [16*NUM_CHANNELS-1:0] db_gpio_ddr; + wire [16*NUM_CHANNELS-1:0] db_gpio_in; + wire [16*NUM_CHANNELS-1:0] db_gpio_fab; + + // DB A SPI Connections + assign DBA_CPLD_PS_SPI_SCLK = spi0_sclk; + assign DBA_CPLD_PS_SPI_MOSI = spi0_mosi; + + // Assign individual chip selects from PS SPI MASTER 0. + assign DBA_CPLD_PS_SPI_CS_B = spi0_ss0; + assign DBA_CLKDIS_SPI_CS_B = spi0_ss1; + assign DBA_PHDAC_SPI_CS_B = spi0_ss2; + assign DBA_ADC_SPI_CS_B = ps_gpio_out[13]; + assign DBA_DAC_SPI_CS_B = ps_gpio_out[14]; + + // Returned data mux from the SPI interfaces. + assign spi0_miso = DBA_CPLD_PS_SPI_MISO; + + // TODO: How to control? + assign DBA_ATR_RX = rx_atr_reg[0]; + assign DBA_ATR_TX = tx_atr_reg[0]; + assign DBA_TXRX_SW_CTRL_1 = db_gpio_out[16*0+0]; + assign DBA_TXRX_SW_CTRL_2 = db_gpio_out[16*0+1]; + assign DBA_LED_RX = db_gpio_out[16*0+2]; + assign DBA_LED_RX2 = db_gpio_out[16*0+3]; + assign DBA_LED_TX = db_gpio_out[16*0+4]; + + // DB B SPI Connections + assign DBB_CPLD_PS_SPI_SCLK = spi1_sclk; + assign DBB_CPLD_PS_SPI_MOSI = spi1_mosi; + + // Assign individual chip selects from PS SPI MASTER 1. + assign DBB_CPLD_PS_SPI_CS_B = spi1_ss0; + assign DBB_CLKDIS_SPI_CS_B = spi1_ss1; + assign DBB_PHDAC_SPI_CS_B = spi1_ss2; + assign DBB_ADC_SPI_CS_B = ps_gpio_out[15]; + assign DBB_DAC_SPI_CS_B = ps_gpio_out[16]; + + // Returned data mux from the SPI interfaces. + assign spi1_miso = DBB_CPLD_PS_SPI_MISO; + + + // TODO: How to control? + assign DBB_ATR_RX = rx_atr_reg[1]; + assign DBB_ATR_TX = tx_atr_reg[1]; + assign DBB_TXRX_SW_CTRL_1 = db_gpio_out[16*1+0]; + assign DBB_TXRX_SW_CTRL_2 = db_gpio_out[16*1+1]; + assign DBB_LED_RX = db_gpio_out[16*1+2]; + assign DBB_LED_RX2 = db_gpio_out[16*1+3]; + assign DBB_LED_TX = db_gpio_out[16*1+4]; + + + /////////////////////////////////////////////////////// + // + // N320 CORE + // + /////////////////////////////////////////////////////// + + wire [CHANNEL_WIDTH-1:0] rx_db[2*NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] tx_db[2*NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] rx[NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] tx[NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] rx_flat; + wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] tx_flat; + wire [47:0] rx_hb[NUM_CHANNELS-1:0]; + wire [95:0] tx_hb[NUM_CHANNELS-1:0]; + + wire [NUM_CHANNELS-1:0] rx_stb; + wire [NUM_CHANNELS-1:0] tx_stb; + + wire [31:0] build_datestamp; + + /* 2:1 and 1:2 filters to bring sample rates down + */ + genvar i; + generate for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + hb47_1to2 tx_1to2 ( + .aresetn(!radio_rst), + .aclk(radio_clk), + .s_axis_data_tvalid(tx_stb[i]), + .s_axis_data_tready(), + .s_axis_data_tdata(tx[i]), + .m_axis_data_tvalid(), + .m_axis_data_tready(tx_stb[i]), + .m_axis_data_tdata(tx_hb[i]) + ); + + assign tx_db[2*i] = {tx_hb[i][39:24], tx_hb[i][15:0]}; + assign tx_db[2*i+1] = {tx_hb[i][87:72], tx_hb[i][63:48]}; + + hb47_2to1 rx_2to1 ( + .aresetn(!radio_rst), + .aclk(radio_clk), + .s_axis_data_tvalid(rx_stb[i]), + .s_axis_data_tready(), + .s_axis_data_tdata({rx_db[2*i+1], rx_db[2*i]}), + .m_axis_data_tvalid(), + .m_axis_data_tdata(rx_hb[i]) + ); + + assign rx[i] = {rx_hb[i][39:24], rx_hb[i][15:0]}; + end endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH] = rx[i]; + assign tx[i] = tx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH]; + end + endgenerate + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + n3xx_core #( + .REG_AWIDTH(14), + .BUS_CLK_RATE(BUS_CLK_RATE), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .CHANNEL_WIDTH(CHANNEL_WIDTH), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + .NUM_SPI_PER_DBOARD(4), + .USE_CORRECTION(1), + `ifdef USE_REPLAY + .USE_REPLAY(1) + `else + .USE_REPLAY(0) + `endif + ) n3xx_core( + // Clocks and resets +`ifdef NO_DB + .radio_clk(bus_clk), + .radio_rst(bus_rst), +`else + .radio_clk(radio_clk), + .radio_rst(radio_rst), +`endif + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps(pps_radioclk1x), + .pps_select(pps_select), + .pps_out_enb(pps_out_enb), + .pps_select_sfp(pps_select_sfp), + .ref_clk_reset(), + .meas_clk_reset(meas_clk_reset), + .ref_clk_locked(1'b1), + .meas_clk_locked(meas_clk_locked), + .enable_ref_clk_async(enable_ref_clk_async), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_XBAR_AWADDR), + .s_axi_awvalid(M_AXI_XBAR_AWVALID), + .s_axi_awready(M_AXI_XBAR_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_XBAR_WDATA), + .s_axi_wstrb(M_AXI_XBAR_WSTRB), + .s_axi_wvalid(M_AXI_XBAR_WVALID), + .s_axi_wready(M_AXI_XBAR_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_XBAR_BRESP), + .s_axi_bvalid(M_AXI_XBAR_BVALID), + .s_axi_bready(M_AXI_XBAR_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_XBAR_ARADDR), + .s_axi_arvalid(M_AXI_XBAR_ARVALID), + .s_axi_arready(M_AXI_XBAR_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_XBAR_RDATA), + .s_axi_rresp(M_AXI_XBAR_RRESP), + .s_axi_rvalid(M_AXI_XBAR_RVALID), + .s_axi_rready(M_AXI_XBAR_RREADY), + // ps gpio source + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + // FP_GPIO + .fp_gpio_inout(FPGA_GPIO), + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + // Radio GPIO DSA + .db_gpio_out_flat(db_gpio_out), + .db_gpio_in_flat(db_gpio_in), + .db_gpio_ddr_flat(db_gpio_ddr), + .db_gpio_fab_flat(db_gpio_fab), + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + //cpld rx_lo tx_lo spi + .sclk_flat({DBB_CPLD_PL_SPI_SCLK, + DBA_CPLD_PL_SPI_SCLK}), + .sen_flat({DBB_CPLD_PL_SPI_CS_B,DBB_LODIS_SPI_CS_B,DBB_RXLO_SPI_CS_B,DBB_TXLO_SPI_CS_B, + DBA_CPLD_PL_SPI_CS_B,DBA_LODIS_SPI_CS_B,DBA_RXLO_SPI_CS_B,DBA_TXLO_SPI_CS_B}), + .mosi_flat({DBB_CPLD_PL_SPI_MOSI, + DBA_CPLD_PL_SPI_MOSI}), + .miso_flat({DBB_CPLD_PL_SPI_MISO, + DBA_CPLD_PL_SPI_MISO}), + // DRAM signals. + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e0_tdata(v2e0_tdata), + .v2e0_tvalid(v2e0_tvalid), + .v2e0_tlast(v2e0_tlast), + .v2e0_tready(v2e0_tready), + + .v2e1_tdata(v2e1_tdata), + .v2e1_tlast(v2e1_tlast), + .v2e1_tvalid(v2e1_tvalid), + .v2e1_tready(v2e1_tready), + + // Ethernet to VITA + .e2v0_tdata(e2v0_tdata), + .e2v0_tlast(e2v0_tlast), + .e2v0_tvalid(e2v0_tvalid), + .e2v0_tready(e2v0_tready), + + .e2v1_tdata(e2v1_tdata), + .e2v1_tlast(e2v1_tlast), + .e2v1_tvalid(e2v1_tvalid), + .e2v1_tready(e2v1_tready), + + //regport interface to npio + .reg_wr_req_npio(reg_wr_req_npio), + .reg_wr_addr_npio(reg_wr_addr_npio), + .reg_wr_data_npio(reg_wr_data_npio), + .reg_rd_req_npio(reg_rd_req_npio), + .reg_rd_addr_npio(reg_rd_addr_npio), + .reg_rd_resp_npio(reg_rd_resp_npio), + .reg_rd_data_npio(reg_rd_data_npio), + + .build_datestamp(build_datestamp), + .xadc_readback({20'h0, device_temp}), + .sfp_ports_info({sfp_port1_info, sfp_port0_info}), + .device_id(device_id) + ); + + // Register the ATR bits once between sending them out to the CPLD to avoid + // glitches on the outputs! + always @(posedge radio_clk) begin + rx_atr_reg <= rx_atr; + tx_atr_reg <= tx_atr; + end + + // ////////////////////////////////////////////////////////////////////// + // + // Daughterboard Cores + // + // ////////////////////////////////////////////////////////////////////// + + wire sAdcSyncUnusedA; + wire sAdcSyncUnusedB; + wire sDacSyncUnusedA; + wire sDacSyncUnusedB; + wire sSysrefUnusedA; + wire sSysrefUnusedB; + wire rRpTransferUnusedA; + wire rRpTransferUnusedB; + wire sSpTransferUnusedA; + wire sSpTransferUnusedB; + wire rWrRpTransferUnusedA; + wire rWrRpTransferUnusedB; + wire sWrSpTransferUnusedA; + wire sWrSpTransferUnusedB; + wire sPpsUnusedB; + wire sPpsToIobUnusedB; + + wire dba_adc_sync_b; + wire dba_dac_sync_b; + wire dba_dac_sync_b_n; // This is the swapped version coming from the IBUFDS. + wire dbb_adc_sync_b; + wire dbb_dac_sync_b; + + wire [49:0] bRegPortInFlatA; + wire [49:0] bRegPortInFlatB; + wire [33:0] bRegPortOutFlatA; + wire [33:0] bRegPortOutFlatB; + + wire rx_a_valid; + wire rx_b_valid; + wire tx_a_rfi; + wire tx_b_rfi; + +`ifdef BUILD_WR + localparam INCL_WR_TDC = 1'b1; +`else + localparam INCL_WR_TDC = 1'b0; +`endif + + wire reg_portA_rd; + wire reg_portA_wr; + wire [14-1:0] reg_portA_addr; + wire [32-1:0] reg_portA_wr_data; + wire [32-1:0] reg_portA_rd_data; + wire reg_portA_ready; + wire validA_unused; + + OBUFDS dba_adc_sync_buf( + .O(DBA_ADC_SYNCB_P), + .OB(DBA_ADC_SYNCB_N), + .I(dba_adc_sync_b) + ); + + IBUFDS dba_dac_sync_buf( + .I(DBA_DAC_SYNCB_P), + .IB(DBA_DAC_SYNCB_N), + .O(dba_dac_sync_b_n) + ); + + // The differential signals are swapped in the pins, so the SYNC signal + // must be negated after the IBUFDS. + assign dba_dac_sync_b = ~ dba_dac_sync_b_n; + + OBUFDS dbb_adc_sync_buf( + .O(DBB_ADC_SYNCB_P), + .OB(DBB_ADC_SYNCB_N), + .I(dbb_adc_sync_b) + ); + + IBUFDS dbb_dac_sync_buf( + .I(DBB_DAC_SYNCB_P), + .IB(DBB_DAC_SYNCB_N), + .O(dbb_dac_sync_b) + ); + + + assign bRegPortInFlatA = {2'b0, reg_portA_addr, reg_portA_wr_data, reg_portA_rd, reg_portA_wr}; + assign {reg_portA_rd_data, validA_unused, reg_portA_ready} = bRegPortOutFlatA; + + DbCore + # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' + dba_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBA_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBA_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clk), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2x), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatA), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatA), //out std_logic_vector(33:0) + .kSlotId(1'b0), //in std_logic + .sSysRefFpgaLvds_p(DBA_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBA_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBA_CLKDIST_SYNC), //out std_logic + .JesdRefClk_p(DBA_MGTCLK_P), //in std_logic + .JesdRefClk_n(DBA_MGTCLK_N), //in std_logic + .aAdcRx_p(DBA_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(DBA_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(dba_adc_sync_b), //out std_logic + .aDacTx_p(DBA_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(DBA_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(dba_dac_sync_b), //in std_logic + .sAdcDataValid(rx_a_valid), //out std_logic + .sAdcDataSample0I(rx_db[0][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample0Q(rx_db[0][15: 0]), //out std_logic_vector(15:0) + .sAdcDataSample1I(rx_db[1][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample1Q(rx_db[1][15: 0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_a_rfi), //out std_logic + .sDacDataSample0I(tx_db[0][31:16]), //in std_logic_vector(15:0) + .sDacDataSample0Q(tx_db[0][15: 0]), //in std_logic_vector(15:0) + .sDacDataSample1I(tx_db[1][31:16]), //in std_logic_vector(15:0) + .sDacDataSample1Q(tx_db[1][15: 0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCA_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCA_1), //inout std_logic + .sPps(pps_radioclk1x), //out std_logic + .sPpsToIob(pps_radioclk1x_iob), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCA_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCA_3), //inout std_logic + .aPpsSfpSel(pps_select_sfp), //in std_logic_vector(1:0) + .sAdcSync(sAdcSyncUnusedA), //out std_logic + .sDacSync(sDacSyncUnusedA), //out std_logic + .sSysRef(sSysrefUnusedA), //out std_logic + .rRpTransfer(rRpTransferUnusedA), //out std_logic + .sSpTransfer(sSpTransferUnusedA), //out std_logic + .rWrRpTransfer(rWrRpTransferUnusedA), //out std_logic + .sWrSpTransfer(sWrSpTransferUnusedA)); //out std_logic + + + + assign rx_stb[0] = rx_a_valid; + assign tx_stb[0] = tx_a_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportA_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD0_AWADDR), + .s_axi_awvalid(M_AXI_JESD0_AWVALID), + .s_axi_awready(M_AXI_JESD0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD0_WDATA), + .s_axi_wstrb(M_AXI_JESD0_WSTRB), + .s_axi_wvalid(M_AXI_JESD0_WVALID), + .s_axi_wready(M_AXI_JESD0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD0_BRESP), + .s_axi_bvalid(M_AXI_JESD0_BVALID), + .s_axi_bready(M_AXI_JESD0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD0_ARADDR), + .s_axi_arvalid(M_AXI_JESD0_ARVALID), + .s_axi_arready(M_AXI_JESD0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_JESD0_RDATA), + .s_axi_rresp(M_AXI_JESD0_RRESP), + .s_axi_rvalid(M_AXI_JESD0_RVALID), + .s_axi_rready(M_AXI_JESD0_RREADY), + // Register port + .reg_port_in_rd (reg_portA_rd), + .reg_port_in_wt (reg_portA_wr), + .reg_port_in_addr (reg_portA_addr), + .reg_port_in_data (reg_portA_wr_data), + .reg_port_out_data (reg_portA_rd_data), + .reg_port_out_ready(reg_portA_ready) + ); + + wire reg_portB_rd; + wire reg_portB_wr; + wire [14-1:0] reg_portB_addr; + wire [32-1:0] reg_portB_wr_data; + wire [32-1:0] reg_portB_rd_data; + wire reg_portB_ready; + wire validB_unused; + + assign bRegPortInFlatB = {2'b0, reg_portB_addr, reg_portB_wr_data, reg_portB_rd, reg_portB_wr}; + assign {reg_portB_rd_data, validB_unused, reg_portB_ready} = bRegPortOutFlatB; + + DbCore + # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' + dbb_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBB_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBB_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clkB), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2xB), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatB), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatB), //out std_logic_vector(33:0) + .kSlotId(1'b1), //in std_logic + .sSysRefFpgaLvds_p(DBB_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBB_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBB_CLKDIST_SYNC), //out std_logic + .JesdRefClk_p(DBB_MGTCLK_P), //in std_logic + .JesdRefClk_n(DBB_MGTCLK_N), //in std_logic + .aAdcRx_p(DBB_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(DBB_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(dbb_adc_sync_b), //out std_logic + .aDacTx_p(DBB_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(DBB_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(dbb_dac_sync_b), //in std_logic + .sAdcDataValid(rx_b_valid), //out std_logic + .sAdcDataSample0I(rx_db[2][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample0Q(rx_db[2][15: 0]), //out std_logic_vector(15:0) + .sAdcDataSample1I(rx_db[3][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample1Q(rx_db[3][15: 0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_b_rfi), //out std_logic + .sDacDataSample0I(tx_db[2][31:16]), //in std_logic_vector(15:0) + .sDacDataSample0Q(tx_db[2][15: 0]), //in std_logic_vector(15:0) + .sDacDataSample1I(tx_db[3][31:16]), //in std_logic_vector(15:0) + .sDacDataSample1Q(tx_db[3][15: 0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCB_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCB_1), //inout std_logic + .sPps(sPpsUnusedB), //out std_logic + .sPpsToIob(sPpsToIobUnusedB), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCB_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCB_3), //inout std_logic + .aPpsSfpSel(2'd0), //in std_logic_vector(1:0) + .sAdcSync(sAdcSyncUnusedB), //out std_logic + .sDacSync(sDacSyncUnusedB), //out std_logic + .sSysRef(sSysrefUnusedB), //out std_logic + .rRpTransfer(rRpTransferUnusedB), //out std_logic + .sSpTransfer(sSpTransferUnusedB), //out std_logic + .rWrRpTransfer(rWrRpTransferUnusedB), //out std_logic + .sWrSpTransfer(sWrSpTransferUnusedB)); //out std_logic + + + + assign rx_stb[1] = rx_b_valid; + assign tx_stb[1] = tx_b_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportB_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY), + // Register port + .reg_port_in_rd (reg_portB_rd), + .reg_port_in_wt (reg_portB_wr), + .reg_port_in_addr (reg_portB_addr), + .reg_port_in_data (reg_portB_wr_data), + .reg_port_out_data (reg_portB_rd_data), + .reg_port_out_ready(reg_portB_ready) + ); + + + // ////////////////////////////////////////////////////////////////////// + // + // LEDS + // + // ////////////////////////////////////////////////////////////////////// + + assign PANEL_LED_LINK = ps_gpio_out[45]; + assign PANEL_LED_REF = ps_gpio_out[46]; + assign PANEL_LED_GPS = ps_gpio_out[47]; + + + ///////////////////////////////////////////////////////////////////// + // + // PUDC Workaround + // + ////////////////////////////////////////////////////////////////////// + // This is a workaround for a silicon bug in Series 7 FPGA where a + // race condition with the reading of PUDC during the erase of the FPGA + // image cause glitches on output IO pins. + // + // Workaround: + // - Define the PUDC pin in the XDC file with a pullup. + // - Implements an IBUF on the PUDC input and make sure that it does + // not get optimized out. + (* dont_touch = "true" *) wire fpga_pudc_b_buf; + IBUF pudc_ibuf_i ( + .I(FPGA_PUDC_B), + .O(fpga_pudc_b_buf)); + +endmodule |