diff options
Diffstat (limited to 'fpga/usrp3/top/e31x')
| -rw-r--r-- | fpga/usrp3/top/e31x/e310_rfnoc_image_core.v | 62 | ||||
| -rw-r--r-- | fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh | 4 | ||||
| -rw-r--r-- | fpga/usrp3/top/e31x/e310_static_router.hex | 2 |
3 files changed, 35 insertions, 33 deletions
diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v index 81c678400..ac479e2d9 100644 --- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v +++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v @@ -13,9 +13,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-02-07T19:18:27.980096 +// File generated on: 2022-03-29T22:54:33.806116 // Source: e310_rfnoc_image_core.yml -// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc +// Source SHA256: 8e0bdf84e7b65cbc1ad575d1d0a2fdcc33632fe69e8ca22057c0298321d8ad84 // `default_nettype none @@ -38,7 +38,7 @@ module rfnoc_image_core #( // IO ports ///////////////////////// - // ctrlport_radio + // ctrlport output wire [ 0:0] m_ctrlport_req_wr, output wire [ 0:0] m_ctrlport_req_rd, output wire [ 19:0] m_ctrlport_req_addr, @@ -49,19 +49,19 @@ module rfnoc_image_core #( input wire [ 0:0] m_ctrlport_resp_ack, input wire [ 1:0] m_ctrlport_resp_status, input wire [ 31:0] m_ctrlport_resp_data, - // time_keeper + // time input wire [ 63:0] radio_time, - // x300_radio - input wire [ 63:0] radio_rx_data, - input wire [ 1:0] radio_rx_stb, - output wire [ 1:0] radio_rx_running, - output wire [ 63:0] radio_tx_data, - input wire [ 1:0] radio_tx_stb, - output wire [ 1:0] radio_tx_running, + // radio + input wire [ 255:0] radio_rx_data, + input wire [ 7:0] radio_rx_stb, + output wire [ 7:0] radio_rx_running, + output wire [ 255:0] radio_tx_data, + input wire [ 7:0] radio_tx_stb, + output wire [ 7:0] radio_tx_running, // dram input wire [ 0:0] axi_rst, output wire [ 3:0] m_axi_awid, - output wire [ 127:0] m_axi_awaddr, + output wire [ 191:0] m_axi_awaddr, output wire [ 31:0] m_axi_awlen, output wire [ 11:0] m_axi_awsize, output wire [ 7:0] m_axi_awburst, @@ -73,8 +73,8 @@ module rfnoc_image_core #( output wire [ 3:0] m_axi_awuser, output wire [ 3:0] m_axi_awvalid, input wire [ 3:0] m_axi_awready, - output wire [ 255:0] m_axi_wdata, - output wire [ 31:0] m_axi_wstrb, + output wire [2047:0] m_axi_wdata, + output wire [ 255:0] m_axi_wstrb, output wire [ 3:0] m_axi_wlast, output wire [ 3:0] m_axi_wuser, output wire [ 3:0] m_axi_wvalid, @@ -85,7 +85,7 @@ module rfnoc_image_core #( input wire [ 3:0] m_axi_bvalid, output wire [ 3:0] m_axi_bready, output wire [ 3:0] m_axi_arid, - output wire [ 127:0] m_axi_araddr, + output wire [ 191:0] m_axi_araddr, output wire [ 31:0] m_axi_arlen, output wire [ 11:0] m_axi_arsize, output wire [ 7:0] m_axi_arburst, @@ -98,7 +98,7 @@ module rfnoc_image_core #( output wire [ 3:0] m_axi_arvalid, input wire [ 3:0] m_axi_arready, input wire [ 3:0] m_axi_rid, - input wire [ 255:0] m_axi_rdata, + input wire [2047:0] m_axi_rdata, input wire [ 7:0] m_axi_rresp, input wire [ 3:0] m_axi_rlast, input wire [ 3:0] m_axi_ruser, @@ -414,7 +414,7 @@ module rfnoc_image_core #( wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tready, m_radio0_out_0_tready; - // ctrl_port + // ctrlport wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_rd; wire [ 19:0] radio0_m_ctrlport_req_addr; @@ -425,20 +425,22 @@ module rfnoc_image_core #( wire [ 0:0] radio0_m_ctrlport_resp_ack; wire [ 1:0] radio0_m_ctrlport_resp_status; wire [ 31:0] radio0_m_ctrlport_resp_data; - // time_keeper + // time wire [ 63:0] radio0_radio_time; - // x300_radio - wire [ 63:0] radio0_radio_rx_data; - wire [ 1:0] radio0_radio_rx_stb; - wire [ 1:0] radio0_radio_rx_running; - wire [ 63:0] radio0_radio_tx_data; - wire [ 1:0] radio0_radio_tx_stb; - wire [ 1:0] radio0_radio_tx_running; + // radio + wire [ 255:0] radio0_radio_rx_data; + wire [ 7:0] radio0_radio_rx_stb; + wire [ 7:0] radio0_radio_rx_running; + wire [ 255:0] radio0_radio_tx_data; + wire [ 7:0] radio0_radio_tx_stb; + wire [ 7:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (2), .CHDR_W (CHDR_W), .NUM_PORTS (2), + .NIPC (1), + .ITEM_W (32), .MTU (MTU) ) b_radio0_0 ( .rfnoc_chdr_clk (rfnoc_chdr_clk), @@ -490,16 +492,16 @@ module rfnoc_image_core #( assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_radio0_in_0_tready; - assign s_radio0_in_1_tdata = m_ep1_out0_tdata; - assign s_radio0_in_1_tlast = m_ep1_out0_tlast; - assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; - assign m_ep1_out0_tready = s_radio0_in_1_tready; - assign s_ep0_in0_tdata = m_radio0_out_0_tdata; assign s_ep0_in0_tlast = m_radio0_out_0_tlast; assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ep0_in0_tready; + assign s_radio0_in_1_tdata = m_ep1_out0_tdata; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast; + assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio0_in_1_tready; + assign s_ep1_in0_tdata = m_radio0_out_1_tdata; assign s_ep1_in0_tlast = m_radio0_out_1_tlast; assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh index 8ea5b7c45..777378b79 100644 --- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh +++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh @@ -12,9 +12,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-02-07T19:18:28.012652 +// File generated on: 2022-03-29T22:54:33.840276 // Source: e310_rfnoc_image_core.yml -// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc +// Source SHA256: 8e0bdf84e7b65cbc1ad575d1d0a2fdcc33632fe69e8ca22057c0298321d8ad84 // `define CHDR_WIDTH 64 diff --git a/fpga/usrp3/top/e31x/e310_static_router.hex b/fpga/usrp3/top/e31x/e310_static_router.hex index 3a9dfa282..a13f8dc6b 100644 --- a/fpga/usrp3/top/e31x/e310_static_router.hex +++ b/fpga/usrp3/top/e31x/e310_static_router.hex @@ -1,5 +1,5 @@ 00000004 004000c0 -008000c1 00c00040 +008000c1 00c10080 |