1 files changed, 21 insertions, 0 deletions
diff --git a/fpga/usrp3/top/b200/catcap_tb.build b/fpga/usrp3/top/b200/catcap_tb.build
new file mode 100755
index 000000000..827ab0628
--- /dev/null
+++ b/fpga/usrp3/top/b200/catcap_tb.build
@@ -0,0 +1,21 @@
+
+#!/bin/sh
+
+rm -rf isim* 
+rm -rf catcap_tb
+rm -rf fuse*
+\
+#     --sourcelibdir ../../models \
+
+vlogcomp \
+    --sourcelibext .v \
+    --sourcelibdir ../../coregen \
+    --sourcelibdir ../../control_lib \
+    --sourcelibdir . \
+    --sourcelibdir $XILINX/verilog/src \
+    --sourcelibdir $XILINX/verilog/src/unisims \
+    --work work \
+    catcap_tb.v
+
+ 
+fuse -o catcap_tb catcap_tb
+\ No newline at end of file