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Diffstat (limited to 'fpga/usrp3/top/Makefile.common')
| -rw-r--r-- | fpga/usrp3/top/Makefile.common | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/fpga/usrp3/top/Makefile.common b/fpga/usrp3/top/Makefile.common new file mode 100644 index 000000000..e005fcb8a --- /dev/null +++ b/fpga/usrp3/top/Makefile.common @@ -0,0 +1,59 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +################################################## +# Constants +################################################## +ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.) +ifeq ($(ISE_VER),10) + ISE_EXT = ise +else + ISE_EXT = xise +endif +BASE_DIR = $(abspath ..) +ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py +TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py +ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) +BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin +BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit +TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr + +################################################## +# Global Targets +################################################## +all: bin + +proj: $(ISE_FILE) + +check: $(ISE_FILE) + #$(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf + $(ISE_HELPER) "Check Syntax" + +synth: $(ISE_FILE) + $(ISE_HELPER) "Synthesize - XST" + +#bin: check $(BIN_FILE) +bin: $(BIN_FILE) $(BIT_FILE) + $(TIMING_CHECKER) $(TWR_FILE) + +clean: + $(RM) -r $(BUILD_DIR) + +.PHONY: all proj check synth bin mcs clean + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: +$(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "" + +$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "Generate Programming File" 2>&1 | tee $(BUILD_DIR)/build.log + touch $@ + +.EXPORT_ALL_VARIABLES: |