2 files changed, 25 insertions, 4 deletions
diff --git a/fpga/usrp3/tools/scripts/viv_sim_project.tcl b/fpga/usrp3/tools/scripts/viv_sim_project.tcl
index b524e332c..922c1edcc 100644
--- a/fpga/usrp3/tools/scripts/viv_sim_project.tcl
+++ b/fpga/usrp3/tools/scripts/viv_sim_project.tcl
@@ -40,6 +40,15 @@ if [expr ([string equal $simulator "XSim"] == 0) && ([string length $sim_complib
 puts "BUILDER: Creating Vivado simulation project part $part_name"
 create_project -part $part_name -force $project_name/$project_name
 
+# Expand directories to include their contents (needed for HLS outputs)
+foreach src_file $design_srcs {
+    if [expr [file isdirectory $src_file] == 1] {
+        puts "BUILDER: Expanding Directory : $src_file"
+        set dir_contents [glob $src_file/*.*]
+        append design_srcs " " $dir_contents
+    }
+}
+
 foreach src_file $design_srcs {
     set src_ext [file extension $src_file ]
     if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
@@ -60,12 +69,15 @@ foreach src_file $design_srcs {
     } elseif [expr [lsearch {.ngc .edif} $src_ext] >= 0] {
         puts "BUILDER: Adding Netlist : $src_file"
         read_edif $src_file
+    } elseif [expr [lsearch {.dat} $src_ext] >= 0] {
+        puts "BUILDER: Adding Data File : $src_file"
+        add_files -fileset $sim_fileset -norecurse $src_file
     } elseif [expr [lsearch {.bd} $src_ext] >= 0] {
-            puts "BUILDER: Adding Block Diagram: $src_file"
-            add_files -norecurse $src_file
+        puts "BUILDER: Adding Block Diagram: $src_file"
+        add_files -norecurse $src_file
     } elseif [expr [lsearch {.bxml} $src_ext] >= 0] {
-            puts "BUILDER: Adding Block Diagram XML: $src_file"
-            add_files -norecurse $src_file
+        puts "BUILDER: Adding Block Diagram XML: $src_file"
+        add_files -norecurse $src_file
     } else {
         puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
     }
diff --git a/fpga/usrp3/tools/scripts/viv_utils.tcl b/fpga/usrp3/tools/scripts/viv_utils.tcl
index 8f34df6f5..9ced39edf 100644
--- a/fpga/usrp3/tools/scripts/viv_utils.tcl
+++ b/fpga/usrp3/tools/scripts/viv_utils.tcl
@@ -59,6 +59,15 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
         create_project -in_memory -part $g_part_name
     }
 
+    # Expand directories to include their contents (needed for HLS outputs)
+    foreach src_file $g_source_files {
+        if [expr [file isdirectory $src_file] == 1] {
+            puts "BUILDER: Expanding Directory : $src_file"
+            set dir_contents [glob $src_file/*.*]
+            append design_srcs " " $dir_contents
+        }
+    }
+
     foreach src_file $g_source_files {
         set src_ext [file extension $src_file ]
         if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {