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-rw-r--r--fpga/usrp3/tools/scripts/viv_check_syntax.tcl14
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga/usrp3/tools/scripts/viv_check_syntax.tcl b/fpga/usrp3/tools/scripts/viv_check_syntax.tcl
new file mode 100644
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+++ b/fpga/usrp3/tools/scripts/viv_check_syntax.tcl
@@ -0,0 +1,14 @@
+#
+# Copyright 2018 Ettus Research
+#
+
+source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
+
+# STEP#1: Create project, add sources, refresh IP
+vivado_utils::initialize_project
+
+# STEP#2: Run elaboration
+vivado_utils::check_design
+
+# Cleanup
+vivado_utils::close_batch_project