6 files changed, 418 insertions, 0 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak
new file mode 100644
index 000000000..5a54da012
--- /dev/null
+++ b/fpga/usrp3/tools/make/viv_design_builder.mak
@@ -0,0 +1,59 @@
+#
+# Copyright 2014-2015 Ettus Research
+#
+
+include $(BASE_DIR)/../tools/make/viv_preamble.mak
+SIMULATION = 0
+
+# -------------------------------------------------------------------
+# Usage: BUILD_VIVADO_DESIGN
+# Args: $1 = TCL_SCRIPT_NAME
+#       $2 = TOP_MODULE
+#       $3 = ARCH (zynq, kintex7, etc)
+#       $4 = PART_ID (<device>/<package>/<speedgrade>[/<temperaturegrade>[/<silicon_revision>]])
+# Prereqs:
+# - TOOLS_DIR must be defined globally
+# - BUILD_DIR must be defined globally
+# - DESIGN_SRCS must be defined and should contain all source files
+# - VERILOG_DEFS must be defined and should contain all PP defines
+# -------------------------------------------------------------------
+BUILD_VIVADO_DESIGN = \
+	@ \
+	export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \
+	export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \
+	export VIV_TOP_MODULE=$(2); \
+	export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
+	export VIV_MODE=$(VIVADO_MODE); \
+	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
+	export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \
+	cd $(BUILD_DIR); \
+	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
+
+
+# -------------------------------------------------------------------
+# Usage: CHECK_VIVADO_DESIGN
+# Args: $1 = TCL_SCRIPT_NAME
+#       $2 = TOP_MODULE
+#       $3 = ARCH (zynq, kintex7, etc)
+#       $4 = PART_ID (<device>/<package>/<speedgrade>[/<temperaturegrade>[/<silicon_revision>]])
+# Prereqs:
+# - TOOLS_DIR must be defined globally
+# - BUILD_DIR must be defined globally
+# - DESIGN_SRCS must be defined and should contain all source files
+# - VERILOG_DEFS must be defined and should contain all PP defines
+# -------------------------------------------------------------------
+CHECK_VIVADO_DESIGN = \
+	@ \
+	export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \
+	export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \
+	export VIV_TOP_MODULE=$(2); \
+	export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
+	export VIV_MODE=$(VIVADO_MODE); \
+	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
+	export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \
+	cd $(BUILD_DIR); \
+	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
+
+
+# Predeclare RFNOC_OOT_SRCS to make sure it's not recursively expanded
+RFNOC_OOT_SRCS :=
diff --git a/fpga/usrp3/tools/make/viv_hls_ip_builder.mak b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak
new file mode 100644
index 000000000..67b52ed2a
--- /dev/null
+++ b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak
@@ -0,0 +1,33 @@
+#
+# Copyright 2015-2017 Ettus Research
+#
+
+# -------------------------------------------------------------------
+# Usage: BUILD_VIVADO_HLS_IP
+# Args: $1 = HLS_IP_NAME (High level synthsis IP name)
+#       $2 = PART_ID (<device>/<package>/<speedgrade>)
+#       $3 = HLS_IP_SRCS (Absolute paths to the HLS IP source files)
+#       $4 = HLS_IP_SRC_DIR (Absolute path to the top level HLS IP src dir)
+#       $5 = HLS_IP_BUILD_DIR (Absolute path to the top level HLS IP build dir)
+# Prereqs:
+# - TOOLS_DIR must be defined globally
+# -------------------------------------------------------------------
+BUILD_VIVADO_HLS_IP = \
+	@ \
+	echo "========================================================"; \
+	echo "BUILDER: Building HLS IP $(1)"; \
+	echo "========================================================"; \
+	export HLS_IP_NAME=$(1); \
+	export PART_NAME=$(subst /,,$(2)); \
+	export HLS_IP_SRCS='$(3)'; \
+	export HLS_IP_INCLUDES='$(6)'; \
+	echo "BUILDER: Staging HLS IP in build directory..."; \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
+	cp -rf $(4)/$(1)/* $(5)/$(1); \
+	cd $(5); \
+	echo "BUILDER: Building HLS IP..."; \
+	export VIV_ERR=0; \
+	vivado_hls -f $(TOOLS_DIR)/scripts/viv_generate_hls_ip.tcl -l $(1).log || export VIV_ERR=$$?; \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \
+	exit $$(($$VIV_ERR))
+
diff --git a/fpga/usrp3/tools/make/viv_ip_builder.mak b/fpga/usrp3/tools/make/viv_ip_builder.mak
new file mode 100644
index 000000000..2663b5862
--- /dev/null
+++ b/fpga/usrp3/tools/make/viv_ip_builder.mak
@@ -0,0 +1,104 @@
+#
+# Copyright 2014 Ettus Research
+#
+
+ifeq ($(SIMULATION),1)
+SYNTH_IP=0
+else
+SYNTH_IP=1
+endif
+
+# -------------------------------------------------------------------
+# Usage: BUILD_VIVADO_IP
+# Args: $1 = IP_NAME (IP name)
+#       $2 = ARCH (zynq, kintex7, etc)
+#       $3 = PART_ID (<device>/<package>/<speedgrade>[/<tempgrade>[/<silicon revision>]])
+#       $4 = IP_SRC_DIR (Absolute path to the top level ip src dir)
+#       $5 = IP_BUILD_DIR (Absolute path to the top level ip build dir)
+#       $6 = GENERATE_EXAMPLE (0 or 1)
+# Prereqs: 
+# - TOOLS_DIR must be defined globally
+# -------------------------------------------------------------------
+BUILD_VIVADO_IP = \
+	@ \
+	echo "========================================================"; \
+	echo "BUILDER: Building IP $(1)"; \
+	echo "========================================================"; \
+	export XCI_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).xci); \
+	export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \
+	export GEN_EXAMPLE=$(6); \
+	export SYNTH_IP=$(SYNTH_IP); \
+	echo "BUILDER: Staging IP in build directory..."; \
+	rm -rf $(5)/$(1)/*; \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
+	cp -rf $(4)/$(1)/* $(5)/$(1); \
+	echo "BUILDER: Retargeting IP to part $(2)/$(3)..."; \
+	python $(TOOLS_DIR)/scripts/viv_ip_xci_editor.py --output_dir=$(5)/$(1) --target=$(2)/$(3) retarget $(4)/$(1)/$(1).xci; \
+	cd $(5); \
+	echo "BUILDER: Building IP..."; \
+	export VIV_ERR=0; \
+	$(TOOLS_DIR)/scripts/launch_vivado.py -mode batch -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_generate_ip.tcl) -log $(1).log -nojournal || export VIV_ERR=$$?; \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \
+	exit $$VIV_ERR
+
+# -------------------------------------------------------------------
+# Usage: BUILD_VIVADO_BD
+# Args: $1 = BD_NAME (IP name)
+#       $2 = ARCH (zynq, kintex7, etc)
+#       $3 = PART_ID (<device>/<package>/<speedgrade>[/<tempgrade>[/<silicon revision>]])
+#       $4 = BD_SRC_DIR (Absolute path to the top level ip src dir)
+#       $5 = BD_BUILD_DIR (Absolute path to the top level ip build dir)
+# Prereqs: 
+# - TOOLS_DIR must be defined globally
+# -------------------------------------------------------------------
+BUILD_VIVADO_BD = \
+	@ \
+	echo "========================================================"; \
+	echo "BUILDER: Building BD $(1)"; \
+	echo "========================================================"; \
+	export BD_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).bd); \
+	export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \
+	echo "BUILDER: Staging BD in build directory..."; \
+	rm $(5)/$(1)/* -rf; \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
+        cp -rf $(4)/$(1)/* $(5)/$(1); \
+	echo "BUILDER: Retargeting BD to part $(2)/$(3)..."; \
+	cd $(5)/$(1); \
+	echo "BUILDER: Building BD..."; \
+	export VIV_ERR=0; \
+	$(TOOLS_DIR)/scripts/launch_vivado.py -mode batch -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_generate_bd.tcl) -log $(1).log -nojournal || export VIV_ERR=$$?; \
+        $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \
+	exit $$VIV_ERR
+
+# -------------------------------------------------------------------
+# Usage: BUILD_VIVADO_BDTCL
+# Args: $1 = BD_NAME (IP name)
+#       $2 = ARCH (zynq, kintex7, etc)
+#       $3 = PART_ID (<device>/<package>/<speedgrade>[/<tempgrade>[/<silicon revision>]])
+#       $4 = BDTCL_SRC_DIR (Absolute path to the top level ip src dir)
+#       $5 = BDTCL_BUILD_DIR (Absolute path to the top level ip build dir)
+#       $6 = BD_IP_REPOS (space-separated list of absolute paths to IP repos)
+#       $7 = BD_HDL_SRCS (space-separated list of absolute paths to HDL sources)
+# Prereqs: 
+# - TOOLS_DIR must be defined globally
+# -------------------------------------------------------------------
+BUILD_VIVADO_BDTCL = \
+	@ \
+	echo "========================================================"; \
+	echo "BUILDER: Generating BD from Tcl $(1)"; \
+	echo "========================================================"; \
+	export BD_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).tcl); \
+	export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \
+	export BD_IP_REPOS=$(call RESOLVE_PATH,$(6)); \
+	export BD_HDL_SRCS=$(call RESOLVE_PATHS,$(7)); \
+	echo "BUILDER: Staging BD Tcl in build directory..."; \
+	rm $(5)/$(1)/* -rf; \
+	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
+        cp -rf $(4)/$(1)/* $(5)/$(1); \
+	echo "BUILDER: Retargeting BD to part $(2)/$(3)..."; \
+	cd $(5)/$(1); \
+	echo "BUILDER: Generating BD..."; \
+	export VIV_ERR=0; \
+	$(TOOLS_DIR)/scripts/launch_vivado.py -mode batch -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_generate_bd.tcl) -log $(1).log -nojournal || export VIV_ERR=$$?; \
+        $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \
+	exit $$VIV_ERR
diff --git a/fpga/usrp3/tools/make/viv_preamble.mak b/fpga/usrp3/tools/make/viv_preamble.mak
new file mode 100644
index 000000000..208858757
--- /dev/null
+++ b/fpga/usrp3/tools/make/viv_preamble.mak
@@ -0,0 +1,77 @@
+#
+# Copyright 2014-2015 Ettus Research
+#
+
+# -------------------------------------------------------------------
+# Environment Setup
+# -------------------------------------------------------------------
+ifeq ($(VIV_PLATFORM),Cygwin)
+RESOLVE_PATH = $(subst \,/,$(shell cygpath -aw $(1)))
+RESOLVE_PATHS = "$(foreach path,$(1),$(subst \,/,$(shell cygpath -aw $(abspath $(path)))))"
+else
+RESOLVE_PATH = $(1)
+RESOLVE_PATHS = "$(1)"
+endif
+
+# -------------------------------------------------------------------
+# Project Setup
+# -------------------------------------------------------------------
+# Requirement: BASE_DIR must be defined
+
+TOOLS_DIR = $(abspath $(BASE_DIR)/../tools)
+LIB_DIR = $(abspath $(BASE_DIR)/../lib)
+SIMLIB_DIR = $(abspath $(BASE_DIR)/../sim)
+LIB_IP_DIR = $(abspath $(LIB_DIR)/ip)
+HLS_IP_DIR = $(abspath $(LIB_DIR)/hls)
+
+O ?= .
+
+ifdef NAME
+BUILD_DIR = $(abspath $(O)/build-$(NAME))
+else
+BUILD_DIR = $(abspath $(O)/build)
+endif
+
+IP_BUILD_DIR = $(abspath ./build-ip/$(subst /,,$(PART_ID)))
+
+# -------------------------------------------------------------------
+# Git Hash Retrieval
+# -------------------------------------------------------------------
+GIT_HASH=$(shell $(TOOLS_DIR)/scripts/git-hash.sh --hashfile=$(TOOLS_DIR)/../../project.githash)
+GIT_HASH_VERILOG_DEF=$(addprefix GIT_HASH=32'h,$(GIT_HASH))
+
+# -------------------------------------------------------------------
+# GUI Mode switch. Calling with GUI:=1 will launch Vivado GUI for build
+# -------------------------------------------------------------------
+ifeq ($(GUI),1)
+VIVADO_MODE=gui
+else
+VIVADO_MODE=batch
+endif
+
+# -------------------------------------------------------------------
+# Toolchain dependency target
+# -------------------------------------------------------------------
+.check_tool:
+	@echo "BUILDER: Checking tools..."
+	@echo -n "* "; bash --version | grep bash || (echo "ERROR: Bash not found in environment. Please install it"; exit 1;)
+	@echo -n "* "; python --version || (echo "ERROR: Python not found in environment. Please install it"; exit 1;)
+	@echo -n "* "; vivado -version 2>&1 | grep Vivado || (echo "ERROR: Vivado not found in environment. Please run setupenv.sh"; exit 1;)
+
+# -------------------------------------------------------------------
+# Intermediate build dirs 
+# -------------------------------------------------------------------
+.build_dirs:
+	@mkdir -p $(BUILD_DIR)
+	@mkdir -p $(IP_BUILD_DIR)
+
+.prereqs: .check_tool .build_dirs
+
+.PHONY: .check_tool .build_dirs .prereqs
+
+# -------------------------------------------------------------------
+# Validate prerequisites
+# -------------------------------------------------------------------
+ifndef PART_ID
+	$(error PART_ID was empty or not set)
+endif
diff --git a/fpga/usrp3/tools/make/viv_sim_preamble.mak b/fpga/usrp3/tools/make/viv_sim_preamble.mak
new file mode 100644
index 000000000..47ad153f4
--- /dev/null
+++ b/fpga/usrp3/tools/make/viv_sim_preamble.mak
@@ -0,0 +1,60 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+include $(BASE_DIR)/../tools/make/viv_preamble.mak
+SIMULATION = 1
+SIM_RUNTIME_US = 1000000000
+
+# -------------------------------------------------------------------
+# Setup simulation
+# -------------------------------------------------------------------
+# Define part using PART_ID (<device>/<package>/<speedgrade>)
+# and architecture (zynq, kintex7, or artix7)
+# User can override these if needed
+ARCH = kintex7
+PART_ID = xc7k410t/ffg900/-2
+
+# Include makefiles and sources for the DUT and its dependencies
+include $(BASE_DIR)/../lib/sim/Makefile.srcs
+
+DESIGN_SRCS = $(abspath $(SIM_DESIGN_SRCS))
+
+# Include interfaces and classes
+include $(BASE_DIR)/../sim/general/Makefile.srcs
+include $(BASE_DIR)/../sim/axi/Makefile.srcs
+include $(BASE_DIR)/../sim/control/Makefile.srcs
+include $(BASE_DIR)/../sim/rfnoc/Makefile.srcs
+
+INC_SRCS = $(abspath \
+$(SIM_GENERAL_SRCS) \
+$(SIM_AXI_SRCS) \
+$(SIM_CONTROL_SRCS) \
+$(SIM_RFNOC_SRCS) \
+)
+
+# Predeclare RFNOC_OOT_SRCS to make sure it's not recursively expanded
+RFNOC_OOT_SRCS :=
+
+all:
+	$(error "all" or "<empty>" is not a valid target. Run make help for a list of supported targets.)
+
+ipclean:
+	@rm -rf $(abspath ./build-ip)
+
+cleanall: ipclean clean
+
+help::
+	@echo "-----------------"
+	@echo "Supported Targets"
+	@echo "-----------------"
+	@echo "ipclean:    Cleanup all IP intermediate files"
+	@echo "clean:      Cleanup all simulator intermediate files"
+	@echo "cleanall:   Cleanup everything!"
+	@echo "vsim:       Simulate with Modelsim"
+	@echo "vlint:      Lint simulation files with Modelsim's Verilog compiler"
+	@echo "vclean:     Cleanup Modelsim's intermediates files"
+	@echo "xsim:       Simulate with Vivado's XSIM simulator"
+	@echo "xclean:     Cleanup Vivado's XSIM intermediate files"
+
+.PHONY: ipclean cleanall help
diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak
new file mode 100644
index 000000000..add3e651d
--- /dev/null
+++ b/fpga/usrp3/tools/make/viv_simulator.mak
@@ -0,0 +1,85 @@
+#
+# Copyright 2014-2015 Ettus Research
+#
+
+# -------------------------------------------------------------------
+# Mode switches
+# -------------------------------------------------------------------
+
+# Calling with FAST:=1 will switch to using unifast libs
+ifeq ($(FAST),1)
+SIM_FAST=true
+else
+SIM_FAST=false
+endif
+
+# -------------------------------------------------------------------
+# Path variables
+# -------------------------------------------------------------------
+
+ifdef SIM_COMPLIBDIR
+COMPLIBDIR = $(call RESOLVE_PATH,$(SIM_COMPLIBDIR))
+endif
+
+# Parse part name from ID
+PART_NAME=$(subst /,,$(PART_ID))
+
+# -------------------------------------------------------------------
+# Usage: SETUP_AND_LAUNCH_SIMULATION
+# Args: $1 = Simulator Name
+# -------------------------------------------------------------------
+SETUP_AND_LAUNCH_SIMULATION = \
+	@ \
+	export VIV_SIMULATOR=$1; \
+	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
+	export VIV_SIM_SRCS=$(call RESOLVE_PATHS,$(SIM_SRCS)); \
+	export VIV_INC_SRCS=$(call RESOLVE_PATHS,$(INC_SRCS)); \
+	export VIV_SIM_TOP=$(SIM_TOP); \
+	export VIV_SYNTH_TOP="$(SYNTH_DUT)"; \
+	export VIV_PART_NAME=$(PART_NAME); \
+	export VIV_SIM_RUNTIME=$(SIM_RUNTIME_US); \
+	export VIV_SIM_FAST="$(SIM_FAST)"; \
+	export VIV_SIM_COMPLIBDIR=$(COMPLIBDIR); \
+	export VIV_SIM_USER_DO=$(MODELSIM_USER_DO); \
+	export VIV_MODE=$(VIVADO_MODE); \
+	export VIV_SIM_64BIT=$(MODELSIM_64BIT); \
+	$(TOOLS_DIR)/scripts/launch_vivado.sh -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_sim_project.tcl) -log xsim.log -nojournal
+
+.SECONDEXPANSION:
+
+##xsim:       Run the simulation using the Xilinx Vivado Simulator
+xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
+	$(call SETUP_AND_LAUNCH_SIMULATION,XSim)
+
+##xclean:     Cleanup Xilinx Vivado Simulator intermediate files
+xclean:
+	@rm -f xsim*.log
+	@rm -rf xsim_proj
+	@rm -f xvhdl.log
+	@rm -f xvhdl.pba
+	@rm -f xvlog.log
+	@rm -f xvlog.pb
+	@rm -f vivado_pid*.str
+
+##vsim:       Run the simulation using Modelsim
+vsim: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
+	$(call SETUP_AND_LAUNCH_SIMULATION,Modelsim)
+
+##vlint:	  Run verilog compiler to lint files.
+vlint: .check_tool
+	@vlog $(SIM_SRCS) +incdir+$(BASE_DIR)/../sim/axi +incdir+$(BASE_DIR)/../sim/general +incdir+$(BASE_DIR)/../sim/control +incdir+$(BASE_DIR)/../sim/rfnoc +incdir+$(BASE_DIR)/../lib/rfnoc
+
+##vclean:     Cleanup Modelsim intermediate files
+vclean:
+	@rm -f modelsim*.log
+	@rm -rf modelsim_proj
+	@rm -f vivado_pid*.str
+	@rm -rf work
+
+# Use clean with :: to support allow "make clean" to work with multiple makefiles
+clean:: xclean vclean
+
+help::
+	@grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
+
+.PHONY: xsim xsim_hls xclean vsim vlint vclean clean help