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-rw-r--r--fpga/usrp3/tools/make/viv_sim_preamble.mak26
1 files changed, 16 insertions, 10 deletions
diff --git a/fpga/usrp3/tools/make/viv_sim_preamble.mak b/fpga/usrp3/tools/make/viv_sim_preamble.mak
index 47ad153f4..afeca0b3c 100644
--- a/fpga/usrp3/tools/make/viv_sim_preamble.mak
+++ b/fpga/usrp3/tools/make/viv_sim_preamble.mak
@@ -9,11 +9,16 @@ SIM_RUNTIME_US = 1000000000
# -------------------------------------------------------------------
# Setup simulation
# -------------------------------------------------------------------
+
# Define part using PART_ID (<device>/<package>/<speedgrade>)
# and architecture (zynq, kintex7, or artix7)
-# User can override these if needed
-ARCH = kintex7
-PART_ID = xc7k410t/ffg900/-2
+#
+# Most simulations are part agnostic, but the user can override
+# these if needed in the makefile in the simulation directory
+#
+# TODO : Update to set from setupenv.sh
+ARCH ?= kintex7
+PART_ID ?= xc7k410t/ffg900/-2
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/sim/Makefile.srcs
@@ -36,14 +41,18 @@ $(SIM_RFNOC_SRCS) \
# Predeclare RFNOC_OOT_SRCS to make sure it's not recursively expanded
RFNOC_OOT_SRCS :=
+# Debug target
+vars::
+ env
+ @echo "ARCH=$(ARCH)"
+ @echo "PART_ID=$(PART_ID)"
+
all:
$(error "all" or "<empty>" is not a valid target. Run make help for a list of supported targets.)
ipclean:
@rm -rf $(abspath ./build-ip)
-cleanall: ipclean clean
-
help::
@echo "-----------------"
@echo "Supported Targets"
@@ -51,10 +60,7 @@ help::
@echo "ipclean: Cleanup all IP intermediate files"
@echo "clean: Cleanup all simulator intermediate files"
@echo "cleanall: Cleanup everything!"
- @echo "vsim: Simulate with Modelsim"
- @echo "vlint: Lint simulation files with Modelsim's Verilog compiler"
- @echo "vclean: Cleanup Modelsim's intermediates files"
- @echo "xsim: Simulate with Vivado's XSIM simulator"
- @echo "xclean: Cleanup Vivado's XSIM intermediate files"
+
+cleanall: ipclean clean
.PHONY: ipclean cleanall help