diff options
Diffstat (limited to 'fpga/usrp3/tools/make/viv_design_builder.mak')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_design_builder.mak | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 5a54da012..74f1ef034 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -22,7 +22,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \ export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \ export VIV_TOP_MODULE=$(2); \ - export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ + export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ @@ -47,7 +47,7 @@ CHECK_VIVADO_DESIGN = \ export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \ export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \ export VIV_TOP_MODULE=$(2); \ - export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ + export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ |