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-rw-r--r--fpga/usrp3/sim/control/Makefile.srcs10
1 files changed, 10 insertions, 0 deletions
diff --git a/fpga/usrp3/sim/control/Makefile.srcs b/fpga/usrp3/sim/control/Makefile.srcs
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+++ b/fpga/usrp3/sim/control/Makefile.srcs
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+#
+# Copyright 2015 Ettus Research LLC
+#
+
+##################################################
+# Control/Readback simulation libraries
+##################################################
+SIM_CONTROL_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sim/control/, \
+sim_set_rb_lib.svh \
+))