diff options
Diffstat (limited to 'fpga/usrp3/sim/b2x0')
| -rwxr-xr-x | fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim b/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim new file mode 100755 index 000000000..dd9215934 --- /dev/null +++ b/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim @@ -0,0 +1,22 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/b200/coregen \ + --sourcelibdir ../../../top/b200 \ + --sourcelibdir ../../../lib/timing \ + --sourcelibdir ../../../lib/vita \ + --sourcelibdir ../../../lib/packet_proc \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/wishbone \ + --sourcelibdir ../../../lib/gpif2 \ + ../../../top/b200/b200_tb.v + + + +fuse work.b200_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_tb.exe + +# run the simulation scrip +./b200_tb.exe # -gui #-tclbatch simcmds.tcl |