diff options
Diffstat (limited to 'fpga/usrp3/lib')
| -rw-r--r-- | fpga/usrp3/lib/fifo/axi_fifo_2clk.v | 16 | ||||
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v | 45 |
2 files changed, 33 insertions, 28 deletions
diff --git a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v index 1f3eee924..a1af5ee8e 100644 --- a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v +++ b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v @@ -88,14 +88,14 @@ module axi_fifo_2clk #( wire o_ext_tvalid; wire o_ext_tready; - // Ideally the following parameters should be technology - // specific. For now these values have been optimized for - // 7Series FPGAs. They also work for Spartan6 but may not - // be optimal. For future generations, make these values - // depend on the DEVICE parameter. - localparam BASE_WIDTH = 72; - localparam SRL_THRESHOLD = 5; - localparam RAM_THRESHOLD = 9; + // Derive constants based on device. + // First triple of values is for Intel's MAX10 FPGAs. The FIFO generator for + // those devices supports embedded memory only (SRL_THRESHOLD = 0). + // The later triple has been optimized for Xilinx 7Series FPGAs. They also + // work for Spartan6 but may not be optimal. + localparam BASE_WIDTH = (DEVICE == "MAX10") ? 36 : 72; + localparam SRL_THRESHOLD = (DEVICE == "MAX10") ? 0 : 5; + localparam RAM_THRESHOLD = (DEVICE == "MAX10") ? 8 : 9; // How many parallel FIFOs to instantiate to fit WIDTH localparam NUM_FIFOS = ((WIDTH-1)/BASE_WIDTH)+1; diff --git a/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v b/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v index 6aa74c74f..6cd45b86b 100644 --- a/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v +++ b/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v @@ -11,8 +11,9 @@ // -module ctrlport_clk_cross ( - +module ctrlport_clk_cross #( + parameter DEVICE = "7SERIES" // FPGA technology identifier (for optimal FIFO inference) +)( input wire rst, // Can be either clock domain, but must be glitch-free //--------------------------------------------------------------------------- @@ -58,7 +59,7 @@ module ctrlport_clk_cross ( // Slave to Master Clock Crossing (Request) //--------------------------------------------------------------------------- - localparam REQ_W = + localparam REQ_W = 1 + // ctrlport_req_wr 1 + // ctrlport_req_rd 20 + // ctrlport_req_addr @@ -76,22 +77,25 @@ module ctrlport_clk_cross ( wire m_ctrlport_req_wr_tmp; wire m_ctrlport_req_rd_tmp; + // Sort by descreasing order of usage possibility. + // This way instance, which do not need port IDs, time etc. can save the MSBs. assign s_req_flat = { - s_ctrlport_req_wr, - s_ctrlport_req_rd, - s_ctrlport_req_addr, s_ctrlport_req_portid, s_ctrlport_req_rem_epid, s_ctrlport_req_rem_portid, - s_ctrlport_req_data, - s_ctrlport_req_byte_en, s_ctrlport_req_has_time, - s_ctrlport_req_time + s_ctrlport_req_time, + s_ctrlport_req_byte_en, + s_ctrlport_req_data, + s_ctrlport_req_addr, + s_ctrlport_req_wr, + s_ctrlport_req_rd }; axi_fifo_2clk #( - .WIDTH (REQ_W), - .SIZE (3) + .WIDTH (REQ_W), + .SIZE (3), + .DEVICE (DEVICE) ) req_fifo ( .reset (rst), .i_aclk (s_ctrlport_clk), @@ -105,16 +109,16 @@ module ctrlport_clk_cross ( ); assign { - m_ctrlport_req_wr_tmp, - m_ctrlport_req_rd_tmp, - m_ctrlport_req_addr, m_ctrlport_req_portid, m_ctrlport_req_rem_epid, m_ctrlport_req_rem_portid, - m_ctrlport_req_data, - m_ctrlport_req_byte_en, m_ctrlport_req_has_time, - m_ctrlport_req_time + m_ctrlport_req_time, + m_ctrlport_req_byte_en, + m_ctrlport_req_data, + m_ctrlport_req_addr, + m_ctrlport_req_wr_tmp, + m_ctrlport_req_rd_tmp } = m_req_flat; assign m_ctrlport_req_wr = m_ctrlport_req_wr_tmp & m_req_flat_valid; @@ -125,7 +129,7 @@ module ctrlport_clk_cross ( // Master to Slave Clock Crossing (Response) //--------------------------------------------------------------------------- - localparam RESP_W = + localparam RESP_W = 1 + // ctrlport_resp_ack, 2 + // ctrlport_resp_status, 32; // ctrlport_resp_data @@ -142,8 +146,9 @@ module ctrlport_clk_cross ( }; axi_fifo_2clk #( - .WIDTH (RESP_W), - .SIZE (3) + .WIDTH (RESP_W), + .SIZE (3), + .DEVICE (DEVICE) ) resp_fifo ( .reset (rst), .i_aclk (m_ctrlport_clk), |