diff options
Diffstat (limited to 'fpga/usrp3/lib')
6 files changed, 22 insertions, 19 deletions
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv index 8c3d974c9..e6cb7c5d9 100644 --- a/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv +++ b/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv @@ -72,10 +72,12 @@ module chdr_traffic_source_sim #( input [7:0] traffic_patt; input [15:0] last_sid; + logic [31:0] rnum; + if (traffic_patt == TRAFFIC_PATT_UNIFORM) begin gen_dst_sid = $urandom_range('d0, NUM_NODES-'d1); end else if (traffic_patt == TRAFFIC_PATT_UNIFORM_OTHERS) begin - logic [31:0] rnum = $urandom_range('d0, NUM_NODES-'d2); + rnum = $urandom_range('d0, NUM_NODES-'d2); if (rnum < NODE_ID) gen_dst_sid = rnum[15:0]; else @@ -99,7 +101,9 @@ module chdr_traffic_source_sim #( // Generation loop. Push to m_chdr infinitely fast initial begin: gen_blk // Generate infinitely - $srandom(NODE_ID + NUM_NODES); + std::process p; + p = process::self(); + p.srandom(NODE_ID + NUM_NODES); m_chdr.reset(); while (1) begin // A generation session begins on the posedge of start_stb diff --git a/fpga/usrp3/lib/rfnoc/file_source.v b/fpga/usrp3/lib/rfnoc/file_source.v index 160cd9984..87ded79bd 100644 --- a/fpga/usrp3/lib/rfnoc/file_source.v +++ b/fpga/usrp3/lib/rfnoc/file_source.v @@ -35,7 +35,6 @@ module file_source #( end end - wire [31:0] sid; reg [11:0] seqnum; wire [15:0] rate; reg [1:0] state; diff --git a/fpga/usrp3/lib/sim/arm_deframer/Makefile b/fpga/usrp3/lib/sim/arm_deframer/Makefile index eb7231d5e..3075cf3cc 100644 --- a/fpga/usrp3/lib/sim/arm_deframer/Makefile +++ b/fpga/usrp3/lib/sim/arm_deframer/Makefile @@ -33,6 +33,7 @@ SIM_TOP = arm_deframer_tb SIM_SRCS = $(abspath \ $(SIM_PROTORFNOC_SRCS) \ +$(RFNOC_SRCS) \ arm_deframer_tb.sv \ ) diff --git a/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv b/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv index 0b1f4414c..7b1310e9c 100644 --- a/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv +++ b/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv @@ -172,7 +172,7 @@ module axis_width_conv_tb(); // - words: The size of the packet in words // - inst: The instance number of the module to send to // - gaps: If 1 then insert bubble cycles randomly in the stream - task push_test_pkt(input integer words, input integer inst, input logic gaps); + task automatic push_test_pkt(input integer words, input integer inst, input logic gaps); begin logic [(MAX_IN_WORDS*WORD_W)-1:0] data = 0; logic [MAX_IN_WORDS-1:0] keep = 0; @@ -217,7 +217,7 @@ module axis_width_conv_tb(); // - inst: The instance number of the module to send to // - gaps: If 1 then insert bubble cycles randomly in the stream // - ok: If 1 then all sanity checks have passed - task pull_test_pkt(input integer words, input integer inst, input logic gaps, output logic ok); + task automatic pull_test_pkt(input integer words, input integer inst, input logic gaps, output logic ok); begin logic [(MAX_OUT_WORDS*WORD_W)-1:0] pull_data = 0; logic [MAX_OUT_WORDS-1:0] pull_keep = 0; diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv index 53aae3719..e47145088 100644 --- a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv +++ b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv @@ -36,8 +36,7 @@ module cap_pattern_verifier_tb(); .PATTERN("RAMP"), .RAMP_START(14'h0000), .RAMP_STOP(14'h3FFF), - .RAMP_INCR(14'h0001), - .NTH_CYCLE(1) + .RAMP_INCR(14'h0001) ) dut0 ( .clk(clk), .rst(rst), @@ -54,8 +53,7 @@ module cap_pattern_verifier_tb(); .PATTERN("RAMP"), .RAMP_START(14'h0100), .RAMP_STOP(14'h0FFF), - .RAMP_INCR(14'h0001), - .NTH_CYCLE(1) + .RAMP_INCR(14'h0001) ) dut1 ( .clk(clk), .rst(rst), diff --git a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv index 38664c20f..f209820df 100644 --- a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv +++ b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv @@ -29,7 +29,17 @@ module chdr_dechunker_tb(); reg [31:0] o_xfer_count = 0, i_xfer_count = 0; reg [63:0] o_last_tdata = 0; - + reg [63:0] i_tdata; + reg i_tlast; + reg i_tvalid; + wire i_tready; + + wire [63:0] o_tdata; + wire o_tlast, o_tvalid, o_tready; + + reg result; + + always #10 clk = ~clk; initial $dumpfile("chdr_dechunker_tb.vcd"); @@ -106,15 +116,6 @@ module chdr_dechunker_tb(); #100 reset = 0; end - reg [63:0] i_tdata; - reg i_tlast; - reg i_tvalid; - wire i_tready; - - wire [63:0] o_tdata; - wire o_tlast, o_tvalid, o_tready; - - reg result; initial begin quantum <= 8; i_tvalid <= 0; |