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-rw-r--r--fpga/usrp3/lib/wb_spi/Makefile.srcs14
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/wb_spi/Makefile.srcs b/fpga/usrp3/lib/wb_spi/Makefile.srcs
new file mode 100644
index 000000000..43048a126
--- /dev/null
+++ b/fpga/usrp3/lib/wb_spi/Makefile.srcs
@@ -0,0 +1,14 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+
+##################################################
+# Control Lib Sources
+##################################################
+WB_SPI_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/wb_spi/, \
+rtl/verilog/spi_clgen.v \
+rtl/verilog/spi_defines.v \
+rtl/verilog/spi_shift.v \
+rtl/verilog/spi_top16.v \
+rtl/verilog/spi_top.v \
+))