diff options
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/crossbar/synth')
7 files changed, 279 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.tcl b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.tcl new file mode 100644 index 000000000..39440b512 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.tcl @@ -0,0 +1,18 @@ +#!/usr/bin/python3 +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +create_project tmp_proj -part xc7k410tffg900-3 -in_memory +add_files {axis_ctrl_crossbar_nxn_top.v ../axis_ctrl_crossbar_nxn.v ../axis_ctrl_crossbar_2d_mesh.v ../mesh_2d_dor_router_multi_sw.v ../axis_switch.v ../axis_ingress_vc_buff.v ../mesh_node_mapping.vh ../mesh_2d_dor_router_single_sw.v ../torus_2d_dor_router_single_sw.v ../torus_2d_dor_router_multi_sw.v ../axis_port_terminator.v} +add_files {../../../fifo/axi_fifo_flop.v ../../../fifo/axi_fifo_flop2.v ../../../fifo/axi_fifo.v ../../../fifo/axi_mux_select.v ../../../fifo/axi_fifo_bram.v ../../../fifo/axi_fifo_cascade.v ../../../fifo/axi_mux.v ../../../fifo/axi_fifo_short.v ../../../fifo/axi_demux.v ../../../fifo/axi_packet_gate.v ../../../control/map/cam_priority_encoder.v ../../../control/map/cam_srl.v ../../../control/map/cam_bram.v ../../../control/map/cam.v ../../../control/map/kv_map.v ../../../control/map/axis_muxed_kv_map.v ../../../control/ram_2port.v} +set_property top axis_ctrl_crossbar_nxn_top [current_fileset] +synth_design +create_clock -name clk -period 2.0 [get_ports clk] +report_utilization -no_primitives -file axis_ctrl_crossbar_nxn.rpt +report_timing_summary -setup -no_detailed_paths -no_header -datasheet -append -file axis_ctrl_crossbar_nxn.rpt +write_checkpoint -force axis_ctrl_crossbar_nxn.dcp +close_project +exit
\ No newline at end of file diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.v.in b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.v.in new file mode 100644 index 000000000..6805100b9 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/axis_ctrl_crossbar_nxn_top.v.in @@ -0,0 +1,47 @@ +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module axis_ctrl_crossbar_nxn_top( + input clk, + input rst +); + // Router global config + localparam IMPL = "{top}"; + localparam NPORTS = {ports}; + localparam DWIDTH = {dataw}; + localparam MTU = {mtu}; + localparam ROUTING = "{ralloc}"; + + (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ; + (* dont_touch = "true"*) wire [NPORTS-1:0] s_axis_tlast , m_axis_tlast ; + (* dont_touch = "true"*) wire [NPORTS-1:0] s_axis_tvalid, m_axis_tvalid; + (* dont_touch = "true"*) wire [NPORTS-1:0] s_axis_tready, m_axis_tready; + (* dont_touch = "true"*) wire deadlock_detected; + + axis_ctrl_crossbar_nxn #( + .WIDTH (DWIDTH), + .NPORTS (NPORTS), + .TOPOLOGY (IMPL), + .INGRESS_BUFF_SIZE(MTU), + .ROUTER_BUFF_SIZE (MTU), + .ROUTING_ALLOC (ROUTING), + .SWITCH_ALLOC ("ROUND-ROBIN") + ) router_dut_i ( + .clk (clk), + .reset (rst), + .s_axis_tdata (s_axis_tdata ), + .s_axis_tlast (s_axis_tlast ), + .s_axis_tvalid (s_axis_tvalid), + .s_axis_tready (s_axis_tready), + .m_axis_tdata (m_axis_tdata ), + .m_axis_tlast (m_axis_tlast ), + .m_axis_tvalid (m_axis_tvalid), + .m_axis_tready (m_axis_tready), + .deadlock_detected(deadlock_detected) + ); + +endmodule + diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.tcl b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.tcl new file mode 100644 index 000000000..304384aee --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.tcl @@ -0,0 +1,18 @@ +#!/usr/bin/python3 +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +create_project tmp_proj -part xc7k410tffg900-3 -in_memory +add_files {chdr_crossbar_nxn_top.v ../chdr_crossbar_nxn.v ../axis_switch.v ../chdr_xb_ingress_buff.v ../chdr_xb_routing_table.v ../../core/chdr_mgmt_pkt_handler.v ../../core/rfnoc_chdr_utils.vh ../../core/rfnoc_chdr_internal_utils.vh} +add_files {../../../fifo/axi_fifo_flop.v ../../../fifo/axi_fifo_flop2.v ../../../fifo/axi_fifo.v ../../../fifo/axi_mux_select.v ../../../fifo/axi_fifo_bram.v ../../../fifo/axi_fifo_cascade.v ../../../fifo/axi_mux.v ../../../fifo/axi_fifo_short.v ../../../fifo/axi_demux.v ../../../fifo/axi_packet_gate.v ../../../control/map/cam_priority_encoder.v ../../../control/map/cam_srl.v ../../../control/map/cam_bram.v ../../../control/map/cam.v ../../../control/map/kv_map.v ../../../control/map/axis_muxed_kv_map.v ../../../control/ram_2port.v} +set_property top chdr_crossbar_nxn_top [current_fileset] +synth_design +create_clock -name clk -period 2.0 [get_ports clk] +report_utilization -no_primitives -file chdr_crossbar_nxn.rpt +report_timing_summary -setup -no_detailed_paths -no_header -datasheet -append -file chdr_crossbar_nxn.rpt +write_checkpoint -force chdr_crossbar_nxn.dcp +close_project +exit
\ No newline at end of file diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.v.in b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.v.in new file mode 100644 index 000000000..fbf0852a3 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/chdr_crossbar_nxn_top.v.in @@ -0,0 +1,55 @@ +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module chdr_crossbar_nxn_top( + input clk, + input rst +); + // Router global config + localparam NPORTS = {ports}; + localparam DWIDTH = {dataw}; + localparam MTU = {mtu}; + localparam RLUT_SIZE = {rlutsize}; + localparam OPTIMIZE = "{opt}"; + + (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ; + (* dont_touch = "true"*) wire [NPORTS-1:0] s_axis_tlast , m_axis_tlast ; + (* dont_touch = "true"*) wire [NPORTS-1:0] s_axis_tvalid, m_axis_tvalid; + (* dont_touch = "true"*) wire [NPORTS-1:0] s_axis_tready, m_axis_tready; + + chdr_crossbar_nxn #( + .CHDR_W (DWIDTH), + .NPORTS (NPORTS), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (RLUT_SIZE), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE (OPTIMIZE), + .NPORTS_MGMT (NPORTS), + .EXT_RTCFG_PORT (1) + ) router_dut_i ( + // General + .clk (clk), + .reset (rst), + // Inputs + .s_axis_tdata (s_axis_tdata), + .s_axis_tlast (s_axis_tlast), + .s_axis_tvalid (s_axis_tvalid), + .s_axis_tready (s_axis_tready), + // Output + .m_axis_tdata (m_axis_tdata), + .m_axis_tlast (m_axis_tlast), + .m_axis_tvalid (m_axis_tvalid), + .m_axis_tready (m_axis_tready), + // External rtcfg port + .ext_rtcfg_stb (0), + .ext_rtcfg_addr (0), + .ext_rtcfg_data (0), + .ext_rtcfg_ack () + ); + +endmodule + diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_axis_ctrl_crossbar_nxn.py b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_axis_ctrl_crossbar_nxn.py new file mode 100755 index 000000000..4ca6e07fa --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_axis_ctrl_crossbar_nxn.py @@ -0,0 +1,37 @@ +#! /usr/bin/python3 +#!/usr/bin/python3 +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +import argparse +import synth_run + +modname = 'axis_ctrl_crossbar_nxn' + +# Parse command line options +def get_options(): + parser = argparse.ArgumentParser(description='Generate synthesis results for ' + modname) + parser.add_argument('--top', type=str, default='TORUS', help='Topologies (CSV)') + parser.add_argument('--ports', type=str, default='8', help='Number of ports (CSV)') + parser.add_argument('--dataw', type=str, default='32', help='Router datapath width (CSV)') + parser.add_argument('--mtu', type=str, default='5', help='MTU (CSV)') + parser.add_argument('--ralloc', type=str, default='WORMHOLE', help='Router allocation method (CSV)') + return parser.parse_args() + +def main(): + args = get_options() + keys = ['top', 'ports', 'dataw', 'mtu', 'ralloc'] + for top in args.top.strip().split(','): + for ports in args.ports.strip().split(','): + for dataw in args.dataw.strip().split(','): + for mtu in args.mtu.strip().split(','): + for ralloc in args.ralloc.strip().split(','): + # Collect parameters + transform = {'ports':ports, 'dataw':dataw, 'mtu':mtu, 'top':top, 'ralloc':ralloc} + synth_run.synth_run(modname, keys, transform) + +if __name__ == '__main__': + main() diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_chdr_crossbar_nxn.py b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_chdr_crossbar_nxn.py new file mode 100755 index 000000000..668e7a247 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_chdr_crossbar_nxn.py @@ -0,0 +1,37 @@ +#! /usr/bin/python3 +#!/usr/bin/python3 +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +import argparse +import synth_run + +modname = 'chdr_crossbar_nxn' + +# Parse command line options +def get_options(): + parser = argparse.ArgumentParser(description='Generate synthesis results for ' + modname) + parser.add_argument('--opt', type=str, default='AREA', help='Optimization strategies (CSV)') + parser.add_argument('--ports', type=str, default='8', help='Number of ports (CSV)') + parser.add_argument('--dataw', type=str, default='64', help='Router datapath width (CSV)') + parser.add_argument('--mtu', type=str, default='10', help='MTU or Ingress buffer size (CSV)') + parser.add_argument('--rlutsize', type=str, default='6', help='Router lookup table size (CSV)') + return parser.parse_args() + +def main(): + args = get_options() + keys = ['opt', 'ports', 'dataw', 'mtu', 'rlutsize'] + for opt in args.opt.strip().split(','): + for ports in args.ports.strip().split(','): + for dataw in args.dataw.strip().split(','): + for mtu in args.mtu.strip().split(','): + for rlutsize in args.rlutsize.strip().split(','): + # Collect parameters + transform = {'opt':opt, 'ports':ports, 'dataw':dataw, 'mtu':mtu, 'rlutsize':rlutsize} + synth_run.synth_run(modname, keys, transform) + +if __name__ == '__main__': + main() diff --git a/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_run.py b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_run.py new file mode 100644 index 000000000..a9801ac20 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/crossbar/synth/synth_run.py @@ -0,0 +1,67 @@ +#! /usr/bin/python3 +#!/usr/bin/python3 +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +import sys, os +import subprocess +import re + +def synth_run(modname, keys, transform): + prefix = modname + '_' + ('_'.join(['%s%s'%(k,transform[k]) for k in keys])) + print('='*(len(prefix)+2)) + print(' %s '%(prefix)) + print('='*(len(prefix)+2)) + # Write Verilog top-level file + with open(modname + '_top.v.in', 'r') as in_file: + with open(modname + '_top.v', 'w') as out_file: + out_file.write(in_file.read().format(**transform)) + # Run Vivado + exitcode = subprocess.Popen( + 'vivado -mode tcl -source %s_top.tcl -nolog -nojou'%(modname), shell=True + ).wait() + if exitcode != 0: + raise RuntimeError('Error running vivado. Was setupenv.sh run?') + # Extract info + lut = 100.0 + reg = 100.0 + bram = 100.0 + dsp = 100.0 + fmax = 0.0 + with open(modname + '.rpt', 'r') as rpt_file: + rpt = rpt_file.readlines() + for line in rpt: + lm = re.match(r'.*Slice LUTs\*.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line) + if lm is not None: + lut = float(lm.group(1).strip()) + rm = re.match(r'.*Slice Registers.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line) + if rm is not None: + reg = float(rm.group(1).strip()) + bm = re.match(r'.*Block RAM Tile.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line) + if bm is not None: + bram = float(bm.group(1).strip()) + dm = re.match(r'.*DSPs.*\|(.*)\|(.*)\|(.*)\|(.*)\|.*', line) + if dm is not None: + dsp = float(dm.group(1).strip()) + tm = re.match(r'.*clk.*\| clk\s*\|(.*)\|.*\|.*\|.*\|.*\|.*\|.*\|.*\|', line) + if tm is not None: + fmax = 1000.0/float(tm.group(1).strip()) + # Save report + os.rename(modname + '.rpt', prefix + '.rpt') + os.rename(modname + '.dcp', prefix + '.dcp') + try: + os.remove(modname + '_top.v') + os.remove('fsm_encoding.os') + except FileNotFoundError: + pass + # Write summary report line + res_keys = ['lut','reg','bram','dsp','fmax'] + res = {'lut':lut, 'reg':reg, 'bram':bram, 'dsp':dsp, 'fmax':fmax, 'prefix':prefix} + if not os.path.exists(modname + '_summary.csv'): + with open(modname + '_summary.csv', 'w') as summaryf: + summaryf.write((','.join(keys + res_keys)) + '\n') + with open(modname + '_summary.csv', 'a') as summaryf: + summaryf.write((','.join(['%s'%(transform[k]) for k in keys])) + ',' + (','.join(['%.1f'%(res[k]) for k in res_keys])) + '\n') |