diff options
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/Makefile.srcs | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/Makefile.srcs b/fpga/usrp3/lib/rfnoc/Makefile.srcs new file mode 100644 index 000000000..cb97542ce --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/Makefile.srcs @@ -0,0 +1,112 @@ +# +# Copyright 2019 Ettus Research, A National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# RFNoC Includes +################################################## +include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs + +RFNOC_FRAMEWORK_SRCS = $(RFNOC_CORE_SRCS) $(RFNOC_XBAR_SRCS) $(RFNOC_UTIL_SRCS) $(RFNOC_XPORT_SRCS) + +################################################## +# RFNoC Sources +################################################## +RFNOC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/, \ +chdr_fifo_large.v \ +chdr_framer.v \ +chdr_framer_2clk.v \ +chdr_deframer.v \ +chdr_deframer_2clk.v \ +chdr_pkt_types.vh \ +axi_packet_mux.v \ +axi_wrapper.v \ +axi_bit_reduce.v \ +null_source.v \ +split_stream.v \ +split_stream_fifo.v \ +conj.v \ +delay_fifo.v \ +delay_type2.v \ +delay_type3.v \ +delay_type4.v \ +complex_to_magsq.v \ +phase_accum.v \ +complex_invert.v \ +periodic_framer.v \ +moving_sum.v \ +counter.v \ +ram_to_fifo.v \ +const.v \ +const_sreg.v \ +cmul.v \ +cadd.v \ +keep_one_in_n.v \ +vector_iir.v \ +addsub.v \ +packet_resizer.v \ +axi_pipe.v \ +multiply.v \ +mult.v \ +mult_add.v \ +mult_rc.v \ +mult_add_rc.v \ +fft_shift.v \ +axi_pipe_join.v \ +axi_pipe_mac.v \ +axi_round_and_clip_complex.v \ +axi_round_complex.v \ +axi_clip_complex.v \ +axi_join.v \ +axi_sync.v \ +split_complex.v \ +axi_round_and_clip.v \ +join_complex.v \ +axi_round.v \ +axi_clip.v \ +axi_clip_unsigned.v \ +axi_serializer.v \ +axi_deserializer.v \ +axi_packer.v \ +complex_to_mag_approx.v \ +file_source.v \ +fosphor/delay.v \ +fosphor/fifo_srl.v \ +fosphor/rng.v \ +fosphor/f15_avg.v \ +fosphor/f15_binmap.v \ +fosphor/f15_core.v \ +fosphor/f15_eoseq.v \ +fosphor/f15_histo_mem.v \ +fosphor/f15_line_mem.v \ +fosphor/f15_logpwr.v \ +fosphor/f15_maxhold.v \ +fosphor/f15_packetizer.v \ +fosphor/f15_rise_decay.v \ +fosphor/f15_wf_agg.v \ +fosphor/axi_logpwr.v \ +cvita_hdr_parser.v \ +cvita_hdr_encoder.v \ +cvita_hdr_decoder.v \ +cvita_hdr_modify.v \ +axi_async_stream.v \ +axi_rate_change.v \ +axi_tag_time.v \ +axi_drop_partial_packet.v \ +ddc.v \ +duc.v \ +cic_decimate.v \ +cic_interpolate.v \ +axi_fir_filter.v \ +fir_filter_slice.v \ +axi_fir_filter_dec.v \ +addsub.vhd \ +dds_freq_tune.v \ +dds_timed.v \ +datapath_gatekeeper.v \ +)) |