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-rw-r--r--fpga/usrp3/lib/io_cap_gen/Makefile.srcs23
1 files changed, 23 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/io_cap_gen/Makefile.srcs b/fpga/usrp3/lib/io_cap_gen/Makefile.srcs
new file mode 100644
index 000000000..a068103cd
--- /dev/null
+++ b/fpga/usrp3/lib/io_cap_gen/Makefile.srcs
@@ -0,0 +1,23 @@
+#
+# Copyright 2014 Ettus Research LLC
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# IO Capture and Generation Sources
+##################################################
+CAT_CAP_GEN_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/io_cap_gen/, \
+./catcap_ddr_cmos.v \
+./catgen_ddr_cmos.v \
+./catcodec_ddr_cmos.v \
+./cat_input_lvds.v \
+./cat_output_lvds.v \
+./cat_io_lvds.v \
+./cat_io_lvds_dual_mode.v \
+))
+
+CAP_GEN_GENERIC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/io_cap_gen/, \
+./cap_pattern_verifier.v \
+))