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Diffstat (limited to 'fpga/usrp3/lib/dsp/add2_reg.v')
| -rw-r--r-- | fpga/usrp3/lib/dsp/add2_reg.v | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/fpga/usrp3/lib/dsp/add2_reg.v b/fpga/usrp3/lib/dsp/add2_reg.v deleted file mode 100644 index 3ac93ae2e..000000000 --- a/fpga/usrp3/lib/dsp/add2_reg.v +++ /dev/null @@ -1,22 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// - - - -module add2_reg - #(parameter WIDTH=16) - (input clk, - input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output reg [WIDTH-1:0] sum); - - wire [WIDTH-1:0] sum_int; - - add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int)); - - always @(posedge clk) - sum <= sum_int; - -endmodule // add2_reg - |