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Diffstat (limited to 'fpga/usrp3/lib/dsp/add2.v')
| -rw-r--r-- | fpga/usrp3/lib/dsp/add2.v | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/fpga/usrp3/lib/dsp/add2.v b/fpga/usrp3/lib/dsp/add2.v deleted file mode 100644 index 124f9d6ca..000000000 --- a/fpga/usrp3/lib/dsp/add2.v +++ /dev/null @@ -1,16 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// - - - -module add2 - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - assign sum = sum_int[WIDTH:1]; // Note -- will have some bias - -endmodule // add2 |