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-rw-r--r--fpga/usrp3/lib/control/dram_2port.v27
1 files changed, 0 insertions, 27 deletions
diff --git a/fpga/usrp3/lib/control/dram_2port.v b/fpga/usrp3/lib/control/dram_2port.v
deleted file mode 100644
index 186af44e7..000000000
--- a/fpga/usrp3/lib/control/dram_2port.v
+++ /dev/null
@@ -1,27 +0,0 @@
-////////////////////////////////////////////////////////////////////////
-// Copyright Ettus Research LLC
-////////////////////////////////////////////////////////////////////////
-
-module dram_2port
- #(parameter DWIDTH=32,
- parameter AWIDTH=9)
- (input clk,
- input write,
- input [AWIDTH-1:0] raddr,
- input [AWIDTH-1:0] waddr,
- input [DWIDTH-1:0] wdata,
- output [DWIDTH-1:0] rdata);
-
- reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
- integer i;
- initial
- for(i=0;i<(1<<AWIDTH);i=i+1)
- ram[i] <= {DWIDTH{1'b0}};
-
- assign rdata = ram[raddr];
-
- always @(posedge clk) begin
- if (write) ram[waddr] <= wdata;
- end
-
-endmodule //dram_2port