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Diffstat (limited to 'fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv')
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index d312b6f32..647e1dc1c 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -14,6 +14,7 @@ module axi4s_fifo #( int SIZE = 1 // default size set to one to act as a pipe phase ) ( + // Clock domain: i.clk (o.clk is unused) input logic clear=1'b0, interface i, // AxiStreamIf or AxiStreamPacketIf interface o, // AxiStreamIf or AxiStreamPacketIf |