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-rw-r--r--fpga/usrp2/top/Makefile.common2
-rw-r--r--fpga/usrp2/top/u2_rev3/u2_core_udp.v7
2 files changed, 6 insertions, 3 deletions
diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common
index d0435fa1e..4da64ac28 100644
--- a/fpga/usrp2/top/Makefile.common
+++ b/fpga/usrp2/top/Makefile.common
@@ -47,7 +47,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST)
@echo $@
$(ISE_HELPER) ""
-$(BIN_FILE): $(ISE_FILE)
+$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
@echo $@
$(ISE_HELPER) "Generate Programming File"
touch $@
diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
index b79cab5fb..124930c23 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
@@ -423,7 +423,10 @@ module u2_core
cycle_count <= 0;
else
cycle_count <= cycle_count + 1;
-
+
+ //compatibility number -> increment when the fpga has been sufficiently altered
+ localparam compat_num = 32'd1;
+
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
@@ -431,7 +434,7 @@ module u2_core
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+ .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count)
);
// /////////////////////////////////////////////////////////////////////////