diff options
Diffstat (limited to 'fpga/usrp2')
| -rw-r--r-- | fpga/usrp2/top/N2x0/u2plus_core.v | 3 | ||||
| -rw-r--r-- | fpga/usrp2/top/USRP2/u2_core.v | 3 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_chain.v | 24 |
3 files changed, 26 insertions, 4 deletions
diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index 378f212e4..369f01183 100644 --- a/fpga/usrp2/top/N2x0/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -437,12 +437,13 @@ module u2plus_core //compatibility number -> increment when the fpga has been sufficiently altered localparam compat_num = {16'd9, 16'd0}; //major, minor + wire [31:0] churn = status; //tweak churn until timing meets! wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word00(churn),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]), .word11(vita_time[31:0]),.word12(compat_num),.word13({18'b0, button, 1'b0, clk_status, serdes_link_up, 10'b0}), diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index 9b26b98e1..6bf60fe58 100644 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -443,12 +443,13 @@ module u2_core //compatibility number -> increment when the fpga has been sufficiently altered localparam compat_num = {16'd9, 16'd0}; //major, minor + wire [31:0] churn = 0; //tweak churn until timing meets! wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word00(churn),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]), .word11(vita_time[31:0]),.word12(compat_num),.word13({20'b0, clk_status, serdes_link_up, 10'b0}), diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index c57e6cc05..ca2f847bc 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -40,10 +40,10 @@ module vita_rx_chain wire clear; assign clear_o = clear; - + wire clear_int; setting_reg #(.my_addr(BASE+3)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear)); + .in(set_data),.out(),.changed(clear_int)); vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), @@ -89,6 +89,26 @@ module vita_rx_chain .data_i(rx_data_int2), .src_rdy_i(rx_src_rdy_int2), .dst_rdy_o(rx_dst_rdy_int2), .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); + //only clear once a full packet has passed through the output interface + reg xfer_pkt, clear_oneshot; + assign clear = (clear_oneshot)? ~xfer_pkt : 0; + always @(posedge clk) begin + + if (reset || clear) begin + clear_oneshot <= 0; + end + else if (clear_int) begin + clear_oneshot <= 1; + end + + if (reset || clear) begin + xfer_pkt <= 0; + end + else if (rx_src_rdy_o && rx_dst_rdy_i) begin + xfer_pkt <= ~rx_data_o[33]; + end + end + assign debug = vrc_debug; // | vrf_debug; endmodule // vita_rx_chain |