diff options
Diffstat (limited to 'fpga/usrp2')
| -rwxr-xr-x | fpga/usrp2/top/u2plus/u2plus.ucf | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/vita_tx_control.v | 18 |
3 files changed, 18 insertions, 4 deletions
diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/u2plus/u2plus.ucf index 25267a67e..5fbe55c26 100755 --- a/fpga/usrp2/top/u2plus/u2plus.ucf +++ b/fpga/usrp2/top/u2plus/u2plus.ucf @@ -158,7 +158,7 @@ NET "RXD<2>" LOC = "AF15" ; NET "RXD<1>" LOC = "AD12" ; ## AD9510 -NET "CLK_STATUS" LOC = "AD22" ; +NET "clk_status" LOC = "AD22" ; NET "CLK_FUNC" LOC = "AC21" ; NET "clk_sel<0>" LOC = "AE21" ; NET "clk_sel<1>" LOC = "AD21" ; diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v index 270655a8d..5facca298 100644 --- a/fpga/usrp2/top/u2plus/u2plus.v +++ b/fpga/usrp2/top/u2plus/u2plus.v @@ -44,7 +44,7 @@ module u2plus output [1:0] clk_en, output [1:0] clk_sel, input CLK_FUNC, // FIXME is an input to control the 9510 - input CLK_STATUS, + input clk_status, inout SCL, inout SDA, // I2C diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v index 20ad6b995..ab6da8bd0 100644 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ b/fpga/usrp2/vrt/vita_tx_control.v @@ -40,7 +40,21 @@ module vita_tx_control time_compare time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), .late(late), .too_early()); + + reg late_qual, late_del; + + always @(posedge clk) + if(reset | clear) + late_del <= 0; + else + late_del <= late; + always @(posedge clk) + if(reset | clear) + late_qual <= 0; + else + late_qual <= (sample_fifo_src_rdy_i & ~sample_fifo_dst_rdy_o); + localparam IBS_IDLE = 0; localparam IBS_RUN = 1; // FIXME do we need this? localparam IBS_CONT_BURST = 2; @@ -87,7 +101,7 @@ module vita_tx_control end else if(~send_at | now) ibs_state <= IBS_RUN; - else if(late | too_early) + else if((late_qual & late_del) | too_early) begin ibs_state <= IBS_ERROR; error_code <= CODE_TIME_ERROR; @@ -166,7 +180,7 @@ module vita_tx_control else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; - assign debug = { { now,early,late,ack,eop,eob,sob,send_at }, + assign debug = { { now,late_qual,late_del,ack,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; |