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-rw-r--r--fpga/usrp2/control_lib/bootram.v46
-rw-r--r--fpga/usrp2/fifo/fifo_long.v2
-rw-r--r--fpga/usrp2/sdr_lib/rx_dcoffset.v2
-rw-r--r--fpga/usrp2/sdr_lib/rx_frontend.v2
-rw-r--r--fpga/usrp2/sdr_lib/tx_frontend.v2
-rw-r--r--fpga/usrp2/top/N2x0/u2plus_core.v2
-rw-r--r--fpga/usrp2/top/USRP2/u2_core.v2
7 files changed, 29 insertions, 29 deletions
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v
index fb7bd46c8..7821fbc4c 100644
--- a/fpga/usrp2/control_lib/bootram.v
+++ b/fpga/usrp2/control_lib/bootram.v
@@ -83,7 +83,7 @@ module bootram
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
.DIA(32'hffffffff), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -93,7 +93,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB0), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
@@ -112,8 +112,8 @@ module bootram
.DOPA(), // Port A 4-bit Parity Output
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
- .DIA(32'd0), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIA(32'hffffffff), // Port A 32-bit Data Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -123,7 +123,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB1), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
@@ -142,8 +142,8 @@ module bootram
.DOPA(), // Port A 4-bit Parity Output
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
- .DIA(32'd0), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIA(32'hffffffff), // Port A 32-bit Data Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -153,7 +153,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB2), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
@@ -172,8 +172,8 @@ module bootram
.DOPA(), // Port A 4-bit Parity Output
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
- .DIA(32'd0), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIA(32'hffffffff), // Port A 32-bit Data Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -183,7 +183,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB3), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
@@ -202,8 +202,8 @@ module bootram
.DOPA(), // Port A 4-bit Parity Output
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
- .DIA(32'd0), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIA(32'hffffffff), // Port A 32-bit Data Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -213,7 +213,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB4), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
@@ -232,8 +232,8 @@ module bootram
.DOPA(), // Port A 4-bit Parity Output
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
- .DIA(32'd0), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIA(32'hffffffff), // Port A 32-bit Data Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -243,7 +243,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB5), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
@@ -262,8 +262,8 @@ module bootram
.DOPA(), // Port A 4-bit Parity Output
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
- .DIA(32'd0), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIA(32'hffffffff), // Port A 32-bit Data Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -273,7 +273,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB6), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
@@ -292,8 +292,8 @@ module bootram
.DOPA(), // Port A 4-bit Parity Output
.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
.CLKA(clk), // Port A 1-bit Clock
- .DIA(32'd0), // Port A 32-bit Data Input
- .DIPA(4'd0), // Port A 4-bit parity Input
+ .DIA(32'hffffffff), // Port A 32-bit Data Input
+ .DIPA(4'hf), // Port A 4-bit parity Input
.ENA(1'b1), // Port A 1-bit RAM Enable Input
.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
.WEA(1'b0), // Port A 4-bit Write Enable Input
@@ -303,7 +303,7 @@ module bootram
.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
.CLKB(clk), // Port B 1-bit Clock
.DIB(dwb_dat_i), // Port B 32-bit Data Input
- .DIPB(4'd0), // Port-B 4-bit parity Input
+ .DIPB(4'hf), // Port-B 4-bit parity Input
.ENB(ENB7), // Port B 1-bit RAM Enable Input
.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
.WEB(WEB) // Port B 4-bit Write Enable Input
diff --git a/fpga/usrp2/fifo/fifo_long.v b/fpga/usrp2/fifo/fifo_long.v
index e9739ad94..c4f0a1cc2 100644
--- a/fpga/usrp2/fifo/fifo_long.v
+++ b/fpga/usrp2/fifo/fifo_long.v
@@ -71,7 +71,7 @@ module fifo_long
.enb((read_state==PRE_READ)|read),
.web(0),
.addrb(rd_addr),
- .dib(0),
+ .dib({WIDTH{1'b1}}),
.dob(dataout));
always @(posedge clk)
diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset.v b/fpga/usrp2/sdr_lib/rx_dcoffset.v
index e43461261..9840e9e1f 100644
--- a/fpga/usrp2/sdr_lib/rx_dcoffset.v
+++ b/fpga/usrp2/sdr_lib/rx_dcoffset.v
@@ -20,7 +20,7 @@
module rx_dcoffset
#(parameter WIDTH=16,
parameter ADDR=8'd0,
- parameter alpha_shift=16)
+ parameter alpha_shift=20)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [WIDTH-1:0] in, output [WIDTH-1:0] out);
diff --git a/fpga/usrp2/sdr_lib/rx_frontend.v b/fpga/usrp2/sdr_lib/rx_frontend.v
index edfbe62df..5b64737b2 100644
--- a/fpga/usrp2/sdr_lib/rx_frontend.v
+++ b/fpga/usrp2/sdr_lib/rx_frontend.v
@@ -1,7 +1,7 @@
module rx_frontend
#(parameter BASE = 0,
- parameter IQCOMP_EN = 0)
+ parameter IQCOMP_EN = 1)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
diff --git a/fpga/usrp2/sdr_lib/tx_frontend.v b/fpga/usrp2/sdr_lib/tx_frontend.v
index 1e7f0bf31..17a6e35e0 100644
--- a/fpga/usrp2/sdr_lib/tx_frontend.v
+++ b/fpga/usrp2/sdr_lib/tx_frontend.v
@@ -2,7 +2,7 @@
module tx_frontend
#(parameter BASE=0,
parameter WIDTH_OUT=16,
- parameter IQCOMP_EN=0)
+ parameter IQCOMP_EN=1)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [23:0] tx_i, input [23:0] tx_q, input run,
diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v
index 9906daa5f..4d612bfab 100644
--- a/fpga/usrp2/top/N2x0/u2plus_core.v
+++ b/fpga/usrp2/top/N2x0/u2plus_core.v
@@ -427,7 +427,7 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd7, 16'd2}; //major, minor
+ localparam compat_num = {16'd7, 16'd3}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v
index d54d16cf0..7415f68e5 100644
--- a/fpga/usrp2/top/USRP2/u2_core.v
+++ b/fpga/usrp2/top/USRP2/u2_core.v
@@ -432,7 +432,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd7, 16'd2}; //major, minor
+ localparam compat_num = {16'd7, 16'd3}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 12:08:42 +0000