diff options
Diffstat (limited to 'fpga/usrp2')
43 files changed, 3244 insertions, 539 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs index d3bb7e2c8..751b40828 100644 --- a/fpga/usrp2/control_lib/Makefile.srcs +++ b/fpga/usrp2/control_lib/Makefile.srcs @@ -30,6 +30,7 @@ srl.v \ system_control.v \ wb_1master.v \ wb_readback_mux.v \ +wb_readback_mux_16LE.v \ quad_uart.v \ simple_uart.v \ simple_uart_tx.v \ diff --git a/fpga/usrp2/control_lib/wb_readback_mux_16LE.v b/fpga/usrp2/control_lib/wb_readback_mux_16LE.v new file mode 100644 index 000000000..2b01898c1 --- /dev/null +++ b/fpga/usrp2/control_lib/wb_readback_mux_16LE.v @@ -0,0 +1,73 @@ + + +// Note -- clocks must be synchronous (derived from the same source) +// Assumes alt_clk is running at a multiple of wb_clk + +// Note -- assumes that the lower-16 bits will be requested first, +// and that the upper-16 bit request will come immediately after. + +module wb_readback_mux_16LE + (input wb_clk_i, + input wb_rst_i, + input wb_stb_i, + input [15:0] wb_adr_i, + output [15:0] wb_dat_o, + output reg wb_ack_o, + + input [31:0] word00, + input [31:0] word01, + input [31:0] word02, + input [31:0] word03, + input [31:0] word04, + input [31:0] word05, + input [31:0] word06, + input [31:0] word07, + input [31:0] word08, + input [31:0] word09, + input [31:0] word10, + input [31:0] word11, + input [31:0] word12, + input [31:0] word13, + input [31:0] word14, + input [31:0] word15 + ); + + wire ack_next = wb_stb_i & ~wb_ack_o; + + always @(posedge wb_clk_i) + if(wb_rst_i) + wb_ack_o <= 0; + else + wb_ack_o <= ack_next; + + reg [31:0] data; + assign wb_dat_o = data[15:0]; + + always @(posedge wb_clk_i) + if (wb_adr_i[1] & ack_next) begin //upper half + data[15:0] <= data[31:16]; + end + else if (~wb_adr_i[1] & ack_next) begin //lower half + case(wb_adr_i[5:2]) + 0 : data <= word00; + 1 : data <= word01; + 2 : data <= word02; + 3 : data <= word03; + 4 : data <= word04; + 5 : data <= word05; + 6 : data <= word06; + 7 : data <= word07; + 8 : data <= word08; + 9 : data <= word09; + 10: data <= word10; + 11: data <= word11; + 12: data <= word12; + 13: data <= word13; + 14: data <= word14; + 15: data <= word15; + endcase // case(wb_adr_i[5:2]) + end + +endmodule // wb_readback_mux + + diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs deleted file mode 100644 index d946af064..000000000 --- a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs +++ /dev/null @@ -1,15 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- IMPORTANT: This is an internal file that has been generated --> -<!-- by the Xilinx ISE software. Any direct editing or --> -<!-- changes made to this file may result in unpredictable --> -<!-- behavior or data corruption. It is strongly advised that --> -<!-- users do not edit the contents of this file. --> -<!-- --> -<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> - -<messages> -<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file "/home/jblum/uhdpriv/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" into library work</arg> -</msg> - -</messages> - diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf deleted file mode 100644 index e69de29bb..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf +++ /dev/null diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf deleted file mode 100644 index e69de29bb..000000000 --- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf +++ /dev/null diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs index c66979132..f0b5b7bae 100644 --- a/fpga/usrp2/fifo/Makefile.srcs +++ b/fpga/usrp2/fifo/Makefile.srcs @@ -7,7 +7,10 @@ ################################################## FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \ buffer_int.v \ +buffer_int2.v \ buffer_pool.v \ +crossbar36.v \ +dsp_framer36.v \ fifo_2clock.v \ fifo_2clock_cascade.v \ ll8_shortfifo.v \ @@ -22,4 +25,7 @@ fifo36_to_fifo19.v \ fifo19_to_fifo36.v \ fifo36_mux.v \ fifo36_demux.v \ +packet_router.v \ +splitter36.v \ +valve36.v \ )) diff --git a/fpga/usrp2/fifo/buffer_int.v b/fpga/usrp2/fifo/buffer_int.v index b45ed3532..49ded8c8d 100644 --- a/fpga/usrp2/fifo/buffer_int.v +++ b/fpga/usrp2/fifo/buffer_int.v @@ -14,7 +14,6 @@ module buffer_int output done, output error, output idle, - output [1:0] flag, // Buffer Interface output en_o, diff --git a/fpga/usrp2/fifo/buffer_int2.v b/fpga/usrp2/fifo/buffer_int2.v new file mode 100644 index 000000000..765b125fb --- /dev/null +++ b/fpga/usrp2/fifo/buffer_int2.v @@ -0,0 +1,173 @@ + +// FIFO Interface to the 2K buffer RAMs +// Read port is read-acknowledge +// FIXME do we want to be able to interleave reads and writes? + +module buffer_int2 + #(parameter BASE = 0, + parameter BUF_SIZE = 9) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + output [31:0] status, + + // Wishbone interface to RAM + input wb_clk_i, + input wb_rst_i, + input wb_we_i, + input wb_stb_i, + input [15:0] wb_adr_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output reg wb_ack_o, + + // Write FIFO Interface + input [35:0] wr_data_i, + input wr_ready_i, + output wr_ready_o, + + // Read FIFO Interface + output [35:0] rd_data_o, + output rd_ready_o, + input rd_ready_i + ); + + reg [BUF_SIZE-1:0] rd_addr, wr_addr; + wire [31:0] ctrl; + wire wr_done, wr_error, wr_idle; + wire rd_done, rd_error, rd_idle; + wire we, en, go; + + reg [BUF_SIZE-1:0] lastline; + wire read = ctrl[3]; + wire rd_clear = ctrl[2]; + wire write = ctrl[1]; + wire wr_clear = ctrl[0]; + + reg [2:0] rd_state, wr_state; + reg rd_sop, rd_eop; + wire wr_sop, wr_eop; + reg [1:0] rd_occ; + wire [1:0] wr_occ; + + localparam IDLE = 3'd0; + localparam PRE_READ = 3'd1; + localparam READING = 3'd2; + localparam WRITING = 3'd3; + localparam ERROR = 3'd4; + localparam DONE = 3'd5; + + // read state machine + always @(posedge clk) + if(rst | (rd_clear & go)) + begin + rd_state <= IDLE; + rd_sop <= 0; + rd_eop <= 0; + rd_occ <= 0; + end + else + case(rd_state) + IDLE : + if(go & read) + begin + rd_addr <= 0; + rd_state <= PRE_READ; + lastline <= ctrl[15+BUF_SIZE:16]; + end + + PRE_READ : + begin + rd_state <= READING; + rd_addr <= rd_addr + 1; + rd_occ <= 2'b00; + rd_sop <= 1; + rd_eop <= 0; + end + + READING : + if(rd_ready_i) + begin + rd_sop <= 0; + rd_addr <= rd_addr + 1; + if(rd_addr == lastline) + begin + rd_eop <= 1; + // FIXME assign occ here + rd_occ <= 0; + end + else + rd_eop <= 0; + if(rd_eop) + rd_state <= DONE; + end + + endcase // case(rd_state) + + // write state machine + always @(posedge clk) + if(rst | (wr_clear & go)) + wr_state <= IDLE; + else + case(wr_state) + IDLE : + if(go & write) + begin + wr_addr <= 0; + wr_state <= WRITING; + end + + WRITING : + if(wr_ready_i) + begin + wr_addr <= wr_addr + 1; + if(wr_sop & wr_eop) + wr_state <= ERROR; // Should save OCC flags here + else if(wr_eop) + wr_state <= DONE; + end // if (wr_ready_i) + endcase // case(wr_state) + + assign rd_data_o[35:32] = { rd_occ[1:0], rd_eop, rd_sop }; + assign rd_ready_o = (rd_state == READING); + + assign wr_sop = wr_data_i[32]; + assign wr_eop = wr_data_i[33]; + assign wr_occ = wr_data_i[35:34]; + assign wr_ready_o = (wr_state == WRITING); + + assign we = (wr_state == WRITING); // always write to avoid timing issue + assign en = ~((rd_state==READING)& ~rd_ready_i); // FIXME potential critical path + + assign rd_done = (rd_state == DONE); + assign wr_done = (wr_state == DONE); + assign rd_error = (rd_state == ERROR); + assign wr_error = (wr_state == ERROR); + assign rd_idle = (rd_state == IDLE); + assign wr_idle = (wr_state == IDLE); + + ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_in // CPU reads here + (.clka(wb_clk_i),.ena(wb_stb_i),.wea(1'b0), + .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(0),.doa(wb_dat_o), + .clkb(clk),.enb(1'b1),.web(we), + .addrb(wr_addr),.dib(wr_data_i[31:0]),.dob()); + + ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_out // CPU writes here + (.clka(wb_clk_i),.ena(wb_stb_i),.wea(wb_we_i), + .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(wb_dat_i),.doa(), + .clkb(clk),.enb(en),.web(1'b0), + .addrb(rd_addr),.dib(0),.dob(rd_data_o[31:0])); + + always @(posedge wb_clk_i) + if(wb_rst_i) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + setting_reg #(.my_addr(BASE)) + sreg(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data), + .out(ctrl),.changed(go)); + + assign status = { {(16-BUF_SIZE){1'b0}},wr_addr, + 8'b0,1'b0,rd_idle,rd_error,rd_done, 1'b0,wr_idle,wr_error,wr_done}; + +endmodule // buffer_int2 diff --git a/fpga/usrp2/fifo/crossbar36.v b/fpga/usrp2/fifo/crossbar36.v new file mode 100644 index 000000000..2a046d8bf --- /dev/null +++ b/fpga/usrp2/fifo/crossbar36.v @@ -0,0 +1,42 @@ + + +module crossbar36 + (input clk, input reset, input clear, + input cross, + input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o, + input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o, + output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i, + output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i); + + reg cross_int, active0, active1; + wire active0_next = (src0_rdy_i & dst0_rdy_o)? ~data0_i[33] : active0; + wire active1_next = (src1_rdy_i & dst1_rdy_o)? ~data1_i[33] : active1; + + assign data0_o = cross_int ? data1_i : data0_i; + assign data1_o = cross_int ? data0_i : data1_i; + + assign src0_rdy_o = cross_int ? src1_rdy_i : src0_rdy_i; + assign src1_rdy_o = cross_int ? src0_rdy_i : src1_rdy_i; + + assign dst0_rdy_o = cross_int ? dst1_rdy_i : dst0_rdy_i; + assign dst1_rdy_o = cross_int ? dst0_rdy_i : dst1_rdy_i; + + always @(posedge clk) + if(reset | clear) + active0 <= 0; + else + active0 <= active0_next; + + always @(posedge clk) + if(reset | clear) + active1 <= 0; + else + active1 <= active1_next; + + always @(posedge clk) + if(reset | clear) + cross_int <= 0; + else if(~active0_next & ~active1_next) + cross_int <= cross; + +endmodule // crossbar36 diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v new file mode 100644 index 000000000..34a05d91e --- /dev/null +++ b/fpga/usrp2/fifo/dsp_framer36.v @@ -0,0 +1,98 @@ + +// Frame DSP packets with a header line to be handled by the protocol machine + +module dsp_framer36 + #(parameter BUF_SIZE = 9) + ( + input clk, input rst, input clr, + input [35:0] inp_data, input inp_valid, output inp_ready, + output [35:0] out_data, output out_valid, input out_ready + ); + + localparam DSP_FRM_STATE_WAIT_SOF = 0; + localparam DSP_FRM_STATE_WAIT_EOF = 1; + localparam DSP_FRM_STATE_WRITE_HDR = 2; + localparam DSP_FRM_STATE_WRITE = 3; + + reg [1:0] dsp_frm_state; + reg [BUF_SIZE-1:0] dsp_frm_addr; + reg [BUF_SIZE-1:0] dsp_frm_count; + wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1; + + //DSP input stream ready in the following states + assign inp_ready = ( + dsp_frm_state == DSP_FRM_STATE_WAIT_SOF || + dsp_frm_state == DSP_FRM_STATE_WAIT_EOF + )? 1'b1 : 1'b0; + + //DSP framer output data mux (header or BRAM): + //The header is generated here from the count. + wire [31:0] dsp_frm_data_bram; + wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; + assign out_data = + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( + (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( + {4'b0000, dsp_frm_data_bram})); + assign out_valid = ( + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) || + (dsp_frm_state == DSP_FRM_STATE_WRITE) + )? 1'b1 : 1'b0; + + RAMB16_S36_S36 dsp_frm_buff( + //port A = DSP input interface (writes to BRAM) + .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0), + .ENA(inp_ready & inp_valid),.SSRA(0),.WEA(inp_ready & inp_valid), + //port B = DSP framer interface (reads from BRAM) + .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), + .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) + ); + + always @(posedge clk) + if(rst | clr) begin + dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; + dsp_frm_addr <= 0; + end + else begin + case(dsp_frm_state) + DSP_FRM_STATE_WAIT_SOF: begin + if (inp_ready & inp_valid & inp_data[32]) begin + dsp_frm_addr <= dsp_frm_addr_next; + dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF; + end + end + + DSP_FRM_STATE_WAIT_EOF: begin + if (inp_ready & inp_valid) begin + if (inp_data[33]) begin + dsp_frm_count <= dsp_frm_addr_next; + dsp_frm_addr <= 0; + dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR; + end + else begin + dsp_frm_addr <= dsp_frm_addr_next; + end + end + end + + DSP_FRM_STATE_WRITE_HDR: begin + if (out_ready & out_valid) begin + dsp_frm_addr <= dsp_frm_addr_next; + dsp_frm_state <= DSP_FRM_STATE_WRITE; + end + end + + DSP_FRM_STATE_WRITE: begin + if (out_ready & out_valid) begin + if (out_data[33]) begin + dsp_frm_addr <= 0; + dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; + end + else begin + dsp_frm_addr <= dsp_frm_addr_next; + end + end + end + endcase //dsp_frm_state + end + +endmodule //dsp_framer36 diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v new file mode 100644 index 000000000..161b59016 --- /dev/null +++ b/fpga/usrp2/fifo/packet_router.v @@ -0,0 +1,535 @@ +module packet_router + #( + parameter BUF_SIZE = 9, + parameter UDP_BASE = 0, + parameter CTRL_BASE = 0 + ) + ( + //wishbone interface for memory mapped CPU frames + input wb_clk_i, + input wb_rst_i, + input wb_we_i, + input wb_stb_i, + input [15:0] wb_adr_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output wb_ack_o, + output wb_err_o, + output wb_rty_o, + + //setting register interface + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input stream_clk, + input stream_rst, + input stream_clr, + + //output status register + output [31:0] status, + + output sys_int_o, //want an interrupt? + + output [31:0] debug, + + // Input Interfaces (in to router) + input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready, + input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready, + input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready, + input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready, + + // Output Interfaces (out of router) + output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready, + output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready, + output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready + ); + + assign wb_err_o = 1'b0; // Unused for now + assign wb_rty_o = 1'b0; // Unused for now + + //////////////////////////////////////////////////////////////////// + // CPU interface to this packet router + //////////////////////////////////////////////////////////////////// + wire [35:0] cpu_inp_data, cpu_out_data; + wire cpu_inp_valid, cpu_out_valid; + wire cpu_inp_ready, cpu_out_ready; + + //////////////////////////////////////////////////////////////////// + // Communication interfaces + //////////////////////////////////////////////////////////////////// + wire [35:0] com_inp_data, com_out_data, udp_out_data; + wire com_inp_valid, com_out_valid, udp_out_valid; + wire com_inp_ready, com_out_ready, udp_out_ready; + + //////////////////////////////////////////////////////////////////// + // Control signals (setting registers and status signals) + // - handshake lines for the CPU communication + // - setting registers to program the inspector + //////////////////////////////////////////////////////////////////// + + //setting register for mode control + wire [31:0] _sreg_mode_ctrl; + setting_reg #(.my_addr(CTRL_BASE+0), .width(1)) sreg_mode_ctrl( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out(master_mode_flag),.changed() + ); + + //setting register to program the IP address + wire [31:0] my_ip_addr; + setting_reg #(.my_addr(CTRL_BASE+1)) sreg_ip_addr( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out(my_ip_addr),.changed() + ); + + //setting register to program the UDP data ports + wire [15:0] dsp0_udp_port, dsp1_udp_port; + setting_reg #(.my_addr(CTRL_BASE+2)) sreg_data_ports( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out({dsp1_udp_port, dsp0_udp_port}),.changed() + ); + + //assign status output signals + wire [31:0] cpu_iface_status; + assign status = { + cpu_iface_status[31:9], master_mode_flag, cpu_iface_status[7:0] + }; + + //////////////////////////////////////////////////////////////////// + // Communication input source crossbar + // When in master mode: + // - serdes input -> comm output combiner + // - ethernet input -> comm input inspector + // When in slave mode: + // - serdes input -> comm input inspector + // - ethernet input -> null sink + //////////////////////////////////////////////////////////////////// + + //streaming signals from the crossbar to the combiner + wire [35:0] ext_inp_data; + wire ext_inp_valid; + wire ext_inp_ready; + + //dummy signals for valve/xbar below + wire [35:0] _eth_inp_data; + wire _eth_inp_valid; + wire _eth_inp_ready; + + valve36 eth_inp_valve ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag), + .data_i(eth_inp_data), .src_rdy_i(eth_inp_valid), .dst_rdy_o(eth_inp_ready), + .data_o(_eth_inp_data), .src_rdy_o(_eth_inp_valid), .dst_rdy_i(_eth_inp_ready) + ); + + crossbar36 com_inp_xbar ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), + .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready), + .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), + .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready), + .data1_o(ext_inp_data), .src1_rdy_o(ext_inp_valid), .dst1_rdy_i(ext_inp_ready) + ); + + //////////////////////////////////////////////////////////////////// + // Communication output sink crossbar + // When in master mode: + // - comm output -> ethernet output + // - insp output -> serdes output + // When in slave mode: + // - com output -> serdes output + // - insp output -> null sink + //////////////////////////////////////////////////////////////////// + + //streaming signals from the inspector to the crossbar + wire [35:0] ext_out_data; + wire ext_out_valid; + wire ext_out_ready; + + //dummy signals for valve/xbar below + wire [35:0] _eth_out_data; + wire _eth_out_valid; + wire _eth_out_ready; + + crossbar36 com_out_xbar ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), + .data0_i(com_out_data), .src0_rdy_i(com_out_valid), .dst0_rdy_o(com_out_ready), + .data1_i(ext_out_data), .src1_rdy_i(ext_out_valid), .dst1_rdy_o(ext_out_ready), + .data0_o(_eth_out_data), .src0_rdy_o(_eth_out_valid), .dst0_rdy_i(_eth_out_ready), + .data1_o(ser_out_data), .src1_rdy_o(ser_out_valid), .dst1_rdy_i(ser_out_ready) + ); + + valve36 eth_out_valve ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag), + .data_i(_eth_out_data), .src_rdy_i(_eth_out_valid), .dst_rdy_o(_eth_out_ready), + .data_o(eth_out_data), .src_rdy_o(eth_out_valid), .dst_rdy_i(eth_out_ready) + ); + + //////////////////////////////////////////////////////////////////// + // Communication output source combiner (feeds UDP proto machine) + // - DSP framer + // - CPU input + // - ERR input + //////////////////////////////////////////////////////////////////// + + //streaming signals from the dsp framer to the combiner + wire [35:0] dsp_frm_data; + wire dsp_frm_valid; + wire dsp_frm_ready; + + //dummy signals to join the the muxes below + wire [35:0] _combiner0_data, _combiner1_data; + wire _combiner0_valid, _combiner1_valid; + wire _combiner0_ready, _combiner1_ready; + + fifo36_mux _com_output_combiner0( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), + .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready), + .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready) + ); + + fifo36_mux _com_output_combiner1( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(32'b0), .src0_rdy_i(1'b0), .dst0_rdy_o(), //mux out from dsp1 can go here + .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), + .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) + ); + + fifo36_mux com_output_source( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready), + .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready), + .data_o(udp_out_data), .src_rdy_o(udp_out_valid), .dst_rdy_i(udp_out_ready) + ); + + //////////////////////////////////////////////////////////////////// + // Interface CPU to memory mapped wishbone + //////////////////////////////////////////////////////////////////// + buffer_int2 #(.BASE(CTRL_BASE+3), .BUF_SIZE(BUF_SIZE)) cpu_to_wb( + .clk(stream_clk), .rst(stream_rst | stream_clr), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(cpu_iface_status), + // Wishbone interface to RAM + .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), + .wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), + .wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), .wb_ack_o(wb_ack_o), + // Write FIFO Interface (from PR and into WB) + .wr_data_i(cpu_out_data), + .wr_ready_i(cpu_out_valid), + .wr_ready_o(cpu_out_ready), + // Read FIFO Interface (from WB and into PR) + .rd_data_o(cpu_inp_data), + .rd_ready_o(cpu_inp_valid), + .rd_ready_i(cpu_inp_ready) + ); + + //////////////////////////////////////////////////////////////////// + // Communication input inspector + // - inspect com input and send it to DSP, EXT, CPU, or BOTH + //////////////////////////////////////////////////////////////////// + localparam COM_INSP_STATE_READ_COM_PRE = 0; + localparam COM_INSP_STATE_READ_COM = 1; + localparam COM_INSP_STATE_WRITE_REGS = 2; + localparam COM_INSP_STATE_WRITE_LIVE = 3; + + localparam COM_INSP_DEST_DSP = 0; + localparam COM_INSP_DEST_EXT = 1; + localparam COM_INSP_DEST_CPU = 2; + localparam COM_INSP_DEST_BOF = 3; + + localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr + localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at + + //output inspector interfaces + wire [35:0] com_insp_out_dsp_data; + wire com_insp_out_dsp_valid; + wire com_insp_out_dsp_ready; + + wire [35:0] com_insp_out_ext_data; + wire com_insp_out_ext_valid; + wire com_insp_out_ext_ready; + + wire [35:0] com_insp_out_cpu_data; + wire com_insp_out_cpu_valid; + wire com_insp_out_cpu_ready; + + wire [35:0] com_insp_out_bof_data; + wire com_insp_out_bof_valid; + wire com_insp_out_bof_ready; + + //connect this fast-path signals directly to the DSP out + assign dsp_out_data = com_insp_out_dsp_data; + assign dsp_out_valid = com_insp_out_dsp_valid; + assign com_insp_out_dsp_ready = dsp_out_ready; + + reg [1:0] com_insp_state; + reg [1:0] com_insp_dest; + reg [3:0] com_insp_dreg_count; //data registers to buffer headers + wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1; + wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0; + reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; + + //extract various packet components: + wire [47:0] com_insp_dregs_eth_dst_mac = {com_insp_dregs[0][15:0], com_insp_dregs[1][31:0]}; + wire [15:0] com_insp_dregs_eth_type = com_insp_dregs[3][15:0]; + wire [7:0] com_insp_dregs_ipv4_proto = com_insp_dregs[6][23:16]; + wire [31:0] com_insp_dregs_ipv4_dst_addr = com_insp_dregs[8][31:0]; + wire [15:0] com_insp_dregs_udp_dst_port = com_insp_dregs[9][15:0]; + wire [15:0] com_insp_dregs_vrt_size = com_inp_data[15:0]; + + //Inspector output flags special case: + //Inject SOF into flags at first DSP line. + wire [3:0] com_insp_out_flags = ( + (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) && + (com_insp_dest == COM_INSP_DEST_DSP) + )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32]; + + //The communication inspector ouput data and valid signals: + //Mux between com input and data registers based on the state. + wire [35:0] com_insp_out_data = (com_insp_state == COM_INSP_STATE_WRITE_REGS)? + {com_insp_out_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data + ; + wire com_insp_out_valid = + (com_insp_state == COM_INSP_STATE_WRITE_REGS)? 1'b1 : ( + (com_insp_state == COM_INSP_STATE_WRITE_LIVE)? com_inp_valid : ( + 1'b0)); + + //The communication inspector ouput ready signal: + //Mux between the various destination ready signals. + wire com_insp_out_ready = + (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_dsp_ready : ( + (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_ext_ready : ( + (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_cpu_ready : ( + (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_bof_ready : ( + 1'b0)))); + + //Always connected output data lines. + assign com_insp_out_dsp_data = com_insp_out_data; + assign com_insp_out_ext_data = com_insp_out_data; + assign com_insp_out_cpu_data = com_insp_out_data; + assign com_insp_out_bof_data = com_insp_out_data; + + //Destination output valid signals: + //Comes from inspector valid when destination is selected, and otherwise low. + assign com_insp_out_dsp_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0; + assign com_insp_out_ext_valid = (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_valid : 1'b0; + assign com_insp_out_cpu_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0; + assign com_insp_out_bof_valid = (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_valid : 1'b0; + + //The communication inspector ouput ready signal: + //Always ready when storing to data registers, + //comes from inspector ready output when live, + //and otherwise low. + assign com_inp_ready = + (com_insp_state == COM_INSP_STATE_READ_COM_PRE) ? 1'b1 : ( + (com_insp_state == COM_INSP_STATE_READ_COM) ? 1'b1 : ( + (com_insp_state == COM_INSP_STATE_WRITE_LIVE) ? com_insp_out_ready : ( + 1'b0))); + + always @(posedge stream_clk) + if(stream_rst | stream_clr) begin + com_insp_state <= COM_INSP_STATE_READ_COM_PRE; + com_insp_dreg_count <= 0; + end + else begin + case(com_insp_state) + COM_INSP_STATE_READ_COM_PRE: begin + if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin + com_insp_state <= COM_INSP_STATE_READ_COM; + com_insp_dreg_count <= com_insp_dreg_count_next; + com_insp_dregs[com_insp_dreg_count] <= com_inp_data; + end + end + + COM_INSP_STATE_READ_COM: begin + if (com_inp_ready & com_inp_valid) begin + com_insp_dregs[com_insp_dreg_count] <= com_inp_data; + if (com_insp_dreg_counter_done | com_inp_data[33]) begin + com_insp_state <= COM_INSP_STATE_WRITE_REGS; + com_insp_dreg_count <= 0; + + //---------- begin inspection decision -----------// + //EOF or bcast or not IPv4 or not UDP: + if ( + com_inp_data[33] || (com_insp_dregs_eth_dst_mac == 48'hffffffffffff) || + (com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11) + ) begin + com_insp_dest <= COM_INSP_DEST_BOF; + end + + //not my IP address: + else if (com_insp_dregs_ipv4_dst_addr != my_ip_addr) begin + com_insp_dest <= COM_INSP_DEST_EXT; + end + + //UDP data port and VRT: + else if ((com_insp_dregs_udp_dst_port == dsp0_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin + com_insp_dest <= COM_INSP_DEST_DSP; + com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; + end + + //other: + else begin + com_insp_dest <= COM_INSP_DEST_CPU; + end + //---------- end inspection decision -------------// + + end + else begin + com_insp_dreg_count <= com_insp_dreg_count_next; + end + end + end + + COM_INSP_STATE_WRITE_REGS: begin + if (com_insp_out_ready & com_insp_out_valid) begin + if (com_insp_out_data[33]) begin + com_insp_state <= COM_INSP_STATE_READ_COM_PRE; + com_insp_dreg_count <= 0; + end + else if (com_insp_dreg_counter_done) begin + com_insp_state <= COM_INSP_STATE_WRITE_LIVE; + com_insp_dreg_count <= 0; + end + else begin + com_insp_dreg_count <= com_insp_dreg_count_next; + end + end + end + + COM_INSP_STATE_WRITE_LIVE: begin + if (com_insp_out_ready & com_insp_out_valid & com_insp_out_data[33]) begin + com_insp_state <= COM_INSP_STATE_READ_COM_PRE; + end + end + + endcase //com_insp_state + end + + //////////////////////////////////////////////////////////////////// + // Splitter and output muxes for the bof packets + // - split the bof packets into two streams + // - mux split packets into cpu out and ext out + //////////////////////////////////////////////////////////////////// + + //dummy signals to join the the splitter and muxes below + wire [35:0] _split_to_ext_data, _split_to_cpu_data, _cpu_out_data; + wire _split_to_ext_valid, _split_to_cpu_valid, _cpu_out_valid; + wire _split_to_ext_ready, _split_to_cpu_ready, _cpu_out_ready; + + splitter36 bof_out_splitter( + .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), + .inp_data(com_insp_out_bof_data), .inp_valid(com_insp_out_bof_valid), .inp_ready(com_insp_out_bof_ready), + .out0_data(_split_to_ext_data), .out0_valid(_split_to_ext_valid), .out0_ready(_split_to_ext_ready), + .out1_data(_split_to_cpu_data), .out1_valid(_split_to_cpu_valid), .out1_ready(_split_to_cpu_ready) + ); + + fifo36_mux ext_out_mux( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(com_insp_out_ext_data), .src0_rdy_i(com_insp_out_ext_valid), .dst0_rdy_o(com_insp_out_ext_ready), + .data1_i(_split_to_ext_data), .src1_rdy_i(_split_to_ext_valid), .dst1_rdy_o(_split_to_ext_ready), + .data_o(ext_out_data), .src_rdy_o(ext_out_valid), .dst_rdy_i(ext_out_ready) + ); + + fifo36_mux cpu_out_mux( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(com_insp_out_cpu_data), .src0_rdy_i(com_insp_out_cpu_valid), .dst0_rdy_o(com_insp_out_cpu_ready), + .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready), + .data_o(_cpu_out_data), .src_rdy_o(_cpu_out_valid), .dst_rdy_i(_cpu_out_ready) + ); + + fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) cpu_out_fifo ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .datain(_cpu_out_data), .src_rdy_i(_cpu_out_valid), .dst_rdy_o(_cpu_out_ready), + .dataout(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready) + ); + + //////////////////////////////////////////////////////////////////// + // DSP input framer + //////////////////////////////////////////////////////////////////// + + dsp_framer36 #(.BUF_SIZE(BUF_SIZE)) dsp0_framer36( + .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), + .inp_data(dsp_inp_data), .inp_valid(dsp_inp_valid), .inp_ready(dsp_inp_ready), + .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready) + ); + + //////////////////////////////////////////////////////////////////// + // UDP TX Protocol machine + //////////////////////////////////////////////////////////////////// + + //dummy signals to connect the components below + wire [18:0] _udp_r2s_data, _udp_s2p_data, _udp_p2s_data, _udp_s2r_data; + wire _udp_r2s_valid, _udp_s2p_valid, _udp_p2s_valid, _udp_s2r_valid; + wire _udp_r2s_ready, _udp_s2p_ready, _udp_p2s_ready, _udp_s2r_ready; + + wire [35:0] _com_out_data; + wire _com_out_valid, _com_out_ready; + + fifo36_to_fifo19 udp_fifo36_to_fifo19 + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), + .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) ); + + fifo_short #(.WIDTH(19)) udp_shortfifo19_inp + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready), + .dataout(_udp_s2p_data), .src_rdy_o(_udp_s2p_valid), .dst_rdy_i(_udp_s2p_ready), + .space(), .occupied() ); + + prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .datain(_udp_s2p_data), .src_rdy_i(_udp_s2p_valid), .dst_rdy_o(_udp_s2p_ready), + .dataout(_udp_p2s_data), .src_rdy_o(_udp_p2s_valid), .dst_rdy_i(_udp_p2s_ready) ); + + fifo_short #(.WIDTH(19)) udp_shortfifo19_out + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .datain(_udp_p2s_data), .src_rdy_i(_udp_p2s_valid), .dst_rdy_o(_udp_p2s_ready), + .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready), + .space(), .occupied() ); + + fifo19_to_fifo36 udp_fifo19_to_fifo36 + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), + .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + + fifo36_mux com_out_mux( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(ext_inp_data), .src0_rdy_i(ext_inp_valid), .dst0_rdy_o(ext_inp_ready), + .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready), + .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) + ); + + //////////////////////////////////////////////////////////////////// + // Assign debugs + //////////////////////////////////////////////////////////////////// + + assign debug = { + //inputs to the router (8) + dsp_inp_ready, dsp_inp_valid, + ser_inp_ready, ser_inp_valid, + eth_inp_ready, eth_inp_valid, + cpu_inp_ready, cpu_inp_valid, + + //outputs from the router (8) + dsp_out_ready, dsp_out_valid, + ser_out_ready, ser_out_valid, + eth_out_ready, eth_out_valid, + cpu_out_ready, cpu_out_valid, + + //inspector interfaces (8) + com_insp_out_dsp_ready, com_insp_out_dsp_valid, + com_insp_out_ext_ready, com_insp_out_ext_valid, + com_insp_out_cpu_ready, com_insp_out_cpu_valid, + com_insp_out_bof_ready, com_insp_out_bof_valid, + + //other interfaces (8) + ext_inp_ready, ext_inp_valid, + com_out_ready, com_out_valid, + ext_out_ready, ext_out_valid, + com_inp_ready, com_inp_valid + }; + +endmodule // packet_router diff --git a/fpga/usrp2/fifo/splitter36.v b/fpga/usrp2/fifo/splitter36.v new file mode 100644 index 000000000..ed998b4f5 --- /dev/null +++ b/fpga/usrp2/fifo/splitter36.v @@ -0,0 +1,68 @@ + +// Split packets from a fifo based interface so it goes out identically on two interfaces + +module splitter36 + ( + input clk, input rst, input clr, + input [35:0] inp_data, input inp_valid, output inp_ready, + output [35:0] out0_data, output out0_valid, input out0_ready, + output [35:0] out1_data, output out1_valid, input out1_ready + ); + + localparam STATE_COPY_BOTH = 0; + localparam STATE_COPY_ZERO = 1; + localparam STATE_COPY_ONE = 2; + + reg [1:0] state; + reg [35:0] data_reg; + + assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; + assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; + + assign out0_valid = + (state == STATE_COPY_BOTH)? inp_valid : ( + (state == STATE_COPY_ZERO)? 1'b1 : ( + 1'b0)); + + assign out1_valid = + (state == STATE_COPY_BOTH)? inp_valid : ( + (state == STATE_COPY_ONE)? 1'b1 : ( + 1'b0)); + + assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0; + + always @(posedge clk) + if (rst | clr) begin + state <= STATE_COPY_BOTH; + end + else begin + case (state) + + STATE_COPY_BOTH: begin + if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin + state <= STATE_COPY_ONE; + end + else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin + state <= STATE_COPY_ZERO; + end + data_reg <= inp_data; + end + + STATE_COPY_ZERO: begin + if (out0_valid & out0_ready) begin + state <= STATE_COPY_BOTH; + end + end + + STATE_COPY_ONE: begin + if (out1_valid & out1_ready) begin + state <= STATE_COPY_BOTH; + end + end + + endcase //state + end + + + +endmodule //splitter36 diff --git a/fpga/usrp2/fifo/valve36.v b/fpga/usrp2/fifo/valve36.v new file mode 100644 index 000000000..d45eee497 --- /dev/null +++ b/fpga/usrp2/fifo/valve36.v @@ -0,0 +1,29 @@ + + +module valve36 + (input clk, input reset, input clear, + input shutoff, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + reg shutoff_int, active; + wire active_next = (src_rdy_i & dst_rdy_o)? ~data_i[33] : active; + + assign data_o = data_i; + + assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i; + assign src_rdy_o = shutoff_int ? 1'b0 : src_rdy_i; + + always @(posedge clk) + if(reset | clear) + active <= 0; + else + active <= active_next; + + always @(posedge clk) + if(reset | clear) + shutoff_int <= 0; + else if(~active_next) + shutoff_int <= shutoff; + +endmodule // valve36 diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs index 284578b39..838b1b813 100644 --- a/fpga/usrp2/opencores/Makefile.srcs +++ b/fpga/usrp2/opencores/Makefile.srcs @@ -25,4 +25,12 @@ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ spi/rtl/verilog/spi_top.v \ spi/rtl/verilog/spi_top16.v \ +zpu/zpu_top_pkg.vhd \ +zpu/zpu_wb_top.vhd \ +zpu/wishbone/wishbone_pkg.vhd \ +zpu/wishbone/zpu_system.vhd \ +zpu/wishbone/zpu_wb_bridge.vhd \ +zpu/core/zpu_config.vhd \ +zpu/core/zpu_core.vhd \ +zpu/core/zpupkg.vhd \ )) diff --git a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd new file mode 100644 index 000000000..b7e894232 --- /dev/null +++ b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd @@ -0,0 +1,15 @@ +library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+ -- generate trace output or not.
+ constant Generate_Trace : boolean := false;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 15;
+end zpu_config;
diff --git a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd new file mode 100644 index 000000000..24586b2f6 --- /dev/null +++ b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd @@ -0,0 +1,949 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_Interrupt, +State_InsnFetch +); + +type StateType is +( +State_Idle, -- using first state first on the list out of paranoia +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult6, +State_Mult4, +State_BinaryOpResult +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; +signal mem_busy : std_logic; +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +signal out_mem_req : std_logic; + +signal inInterrupt : std_logic; + +-- state machine. + +begin + + zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; + zpu_status(31) <= '1'; + zpu_status(39 downto 32) <= trace_opcode; + zpu_status(40) <= '1' when (state = State_Idle) else '0'; + zpu_status(62) <= '1'; + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + mem_req <= out_mem_req; + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= stack_start(maxAddrBitIncIO downto minAddrBit); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_we <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + out_mem_req <= '0'; + mem_addr <= (others => DontCareValue); + mem_write <= (others => DontCareValue); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + -- we terminate the requeset as soon as we get acknowledge + if mem_ack = '1' then + out_mem_req <= '0'; + mem_we <= '0'; + end if; + + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if mem_busy='0' then + mem_addr <= sp; + out_mem_req <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + else + insn <= insn; + end if; + when State_StoreSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + else + insn <= insn; + end if; + + + when State_LoadSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_Emulate => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Callpcrel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Call => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_AddSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + out_mem_req <= '1'; + mem_addr <= sp+spOffset; + else + insn <= insn; + end if; + when State_PushSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_PopPC => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopPCRel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_Add => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Sub => + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + when State_Pop => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + else + insn <= insn; + end if; + when State_PopDown => + if mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Or => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_And => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Eq => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthanorequal => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthanorequal => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Load => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when State_Dup => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_DupStackB => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_Store => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= incIncSp; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + else + insn <= insn; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + when State_Storeb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when others => +-- sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if mem_busy='0' then + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if mem_busy='0' then + state <= State_LoadSP3; + out_mem_req <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + out_mem_req <= '1'; + mem_we <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if mem_busy='0' then + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt + inInterrupt <= '1'; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + + report "ZPU jumped to interrupt!" severity note; + else + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + stackA <= multResult3; + state <= State_Mult6; + when State_Mult6 => + if mem_busy='0' then + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + if mem_busy='0' then + -- NB!!!! we know that the memory isn't busy at this point!!!! + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult; + state <= State_Popped; + end if; + when State_Popped => + if mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => +-- sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd new file mode 100644 index 000000000..eee967a09 --- /dev/null +++ b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd @@ -0,0 +1,169 @@ +library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+library work;
+use work.zpu_config.all;
+
+package zpupkg is
+
+ -- This bit is set for read/writes to IO
+ -- FIX!!! eventually this should be set to wordSize-1 so as to
+ -- to make the address of IO independent of amount of memory
+ -- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+ -- libraries.
+
+ constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
+ constant maxAddrBit : integer := maxAddrBitIncIO-1;
+ constant ioBit : integer := maxAddrBit+1;
+ constant wordSize : integer := 2**wordPower;
+ constant wordBytes : integer := wordSize/8;
+ constant minAddrBit : integer := byteBits;
+ -- configurable internal stack size. Probably going to be 16 after toolchain is done
+ constant stack_bits : integer := 5;
+ constant stack_size : integer := 2**stack_bits;
+
+ component dualport_ram is
+ port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+ end component;
+
+ component dram is
+ port (clk : in std_logic;
+ areset : in std_logic;
+ mem_writeEnable : in std_logic;
+ mem_readEnable : in std_logic;
+ mem_addr : in std_logic_vector(maxAddrBit downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_busy : out std_logic;
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+ end component;
+
+
+ component trace is
+ port(
+ clk : in std_logic;
+ begin_inst : in std_logic;
+ pc : in std_logic_vector(maxAddrBitIncIO downto 0);
+ opcode : in std_logic_vector(7 downto 0);
+ sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+ memA : in std_logic_vector(wordSize-1 downto 0);
+ memB : in std_logic_vector(wordSize-1 downto 0);
+ busy : in std_logic;
+ intSp : in std_logic_vector(stack_bits-1 downto 0)
+ );
+ end component;
+
+ component zpu_core is
+ port ( clk : in std_logic;
+ areset : in std_logic;
+ enable : in std_logic;
+ mem_req : out std_logic;
+ mem_we : out std_logic;
+ mem_ack : in std_logic;
+ mem_read : in std_logic_vector(wordSize-1 downto 0);
+ mem_write : out std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+ mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+ stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
+ interrupt : in std_logic;
+ break : out std_logic;
+ zpu_status : out std_logic_vector(63 downto 0));
+ end component;
+
+
+
+ component timer is
+ port(
+ clk : in std_logic;
+ areset : in std_logic;
+ sample : in std_logic;
+ reset : in std_logic;
+ counter : out std_logic_vector(63 downto 0));
+ end component;
+
+ component zpuio is
+ port ( areset : in std_logic;
+ cpu_clk : in std_logic;
+ clk_status : in std_logic_vector(2 downto 0);
+ cpu_din : in std_logic_vector(15 downto 0);
+ cpu_a : in std_logic_vector(20 downto 0);
+ cpu_we : in std_logic_vector(1 downto 0);
+ cpu_re : in std_logic;
+ cpu_dout : inout std_logic_vector(15 downto 0));
+ end component;
+
+
+
+
+ -- opcode decode constants
+ constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
+ constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
+ constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
+ constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
+ constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
+ constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
+
+ constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
+ constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
+ constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
+ constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011";
+
+ constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
+ constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
+ constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
+ constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
+
+ constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
+ constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
+ constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
+ constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
+
+ constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
+ constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
+ constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110";
+ constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111";
+
+ constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
+ constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
+ constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
+ constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
+
+ constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
+ constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
+
+ constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
+ constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
+ constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
+ constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
+
+ constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
+ constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
+
+ constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
+ constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
+ constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
+
+ constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
+ constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
+ constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
+
+ constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
+ constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
+ constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
+
+
+
+ constant OpCode_Size : integer := 8;
+
+
+
+end zpupkg;
diff --git a/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd b/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd new file mode 100644 index 000000000..375c9ac7e --- /dev/null +++ b/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd @@ -0,0 +1,86 @@ +-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+ type wishbone_bus_in is record
+ adr : std_logic_vector(15 downto 0);
+ sel : std_logic_vector(3 downto 0);
+ we : std_logic;
+ dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we'
+ cyc : std_logic;
+ stb : std_logic;
+ end record;
+
+ type wishbone_bus_out is record
+ dat : std_logic_vector(31 downto 0);
+ ack : std_logic;
+ end record;
+
+ type wishbone_bus is record
+ insig : wishbone_bus_in;
+ outsig : wishbone_bus_out;
+ end record;
+
+ component atomic32_access is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from CPU interface
+ wb_16_i : in wishbone_bus_in;
+ wb_16_o : out wishbone_bus_out;
+ -- Wishbone to FPGA registers and ethernet core
+ wb_32_i : in wishbone_bus_out;
+ wb_32_o : out wishbone_bus_in);
+ end component;
+
+ component eth_access_corr is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from Wishbone MUX
+ eth_raw_o : out wishbone_bus_out;
+ eth_raw_i : in wishbone_bus_in;
+
+ -- Wishbone ethernet core
+ eth_slave_i : in wishbone_bus_out;
+ eth_slave_o : out wishbone_bus_in);
+ end component;
+
+
+end wishbone_pkg;
diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd new file mode 100644 index 000000000..8af678b6a --- /dev/null +++ b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd @@ -0,0 +1,106 @@ +-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+library work;
+use work.zpu_top_pkg.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_system is
+ generic(
+ simulate : boolean := false);
+ port ( areset : in std_logic;
+ cpu_clk : in std_logic;
+
+ -- ZPU Control signals
+ enable : in std_logic;
+ interrupt : in std_logic;
+ stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
+ zpu_status : out std_logic_vector(63 downto 0);
+
+ -- wishbone interfaces
+ zpu_wb_i : in wishbone_bus_out;
+ zpu_wb_o : out wishbone_bus_in);
+end zpu_system;
+
+architecture behave of zpu_system is
+
+signal mem_req : std_logic;
+signal mem_we : std_logic;
+signal mem_ack : std_logic;
+signal mem_read : std_logic_vector(wordSize-1 downto 0);
+signal mem_write : std_logic_vector(wordSize-1 downto 0);
+signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+
+begin
+
+ my_zpu_core:
+ zpu_core port map (
+ clk => cpu_clk,
+ areset => areset,
+ enable => enable,
+ mem_req => mem_req,
+ mem_we => mem_we,
+ mem_ack => mem_ack,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => out_mem_addr,
+ mem_writeMask => mem_writeMask,
+ stack_start => stack_start,
+ interrupt => interrupt,
+ zpu_status => zpu_status,
+ break => open);
+
+ my_zpu_wb_bridge:
+ zpu_wb_bridge port map (
+ clk => cpu_clk,
+ areset => areset,
+ mem_req => mem_req,
+ mem_we => mem_we,
+ mem_ack => mem_ack,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => out_mem_addr,
+ mem_writeMask => mem_writeMask,
+ zpu_wb_i => zpu_wb_i,
+ zpu_wb_o => zpu_wb_o);
+
+end behave;
diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd new file mode 100644 index 000000000..104ee10b8 --- /dev/null +++ b/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd @@ -0,0 +1,83 @@ +-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_top_pkg.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_wb_bridge is
+ port ( -- Native ZPU interface
+ clk : in std_logic;
+ areset : in std_logic;
+
+ mem_req : in std_logic;
+ mem_we : in std_logic;
+ mem_ack : out std_logic;
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0);
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0);
+
+ -- Wishbone from ZPU
+ zpu_wb_i : in wishbone_bus_out;
+ zpu_wb_o : out wishbone_bus_in);
+
+end zpu_wb_bridge;
+
+architecture behave of zpu_wb_bridge is
+
+begin
+
+ mem_read <= zpu_wb_i.dat;
+ mem_ack <= zpu_wb_i.ack;
+
+ zpu_wb_o.adr <= out_mem_addr;
+ zpu_wb_o.dat <= mem_write;
+ zpu_wb_o.sel <= mem_writeMask;
+ zpu_wb_o.stb <= mem_req;
+ zpu_wb_o.cyc <= mem_req;
+ zpu_wb_o.we <= mem_we;
+
+end behave;
+
+
+
+
+
diff --git a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd new file mode 100644 index 000000000..a158ab9c0 --- /dev/null +++ b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd @@ -0,0 +1,46 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpupkg.all; +use work.zpu_config.all; +use work.wishbone_pkg.all; + +package zpu_top_pkg is + component zpu_wb_bridge is + port ( -- Native ZPU interface + clk : in std_logic; + areset : in std_logic; + + mem_req : in std_logic; + mem_we : in std_logic; + mem_ack : out std_logic; + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0); + + -- Wishbone from ZPU + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); + end component; + + component zpu_system is + generic( + simulate : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + + -- ZPU Control signals + enable : in std_logic; + interrupt : in std_logic; + stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); + zpu_status : out std_logic_vector(63 downto 0); + + -- wishbone interfaces + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); + end component; + +end zpu_top_pkg; diff --git a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd new file mode 100644 index 000000000..9735c4b54 --- /dev/null +++ b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -0,0 +1,76 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_top_pkg.all; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +------------------------------------------------------------------------ +-- Top level ZPU + wishbone componenent to use in a verilog design: +-- zpu_wb_top wraps around the zpu_system component. +-- All IO lines are exposed as std_logic for verilog. +------------------------------------------------------------------------ +entity zpu_wb_top is + generic ( + dat_w: integer := 32; + adr_w: integer := 16; + sel_w: integer := 4 + ); + port ( + clk: in std_logic; + rst: in std_logic; + enb: in std_logic; + + -- wishbone interface + dat_i: in std_logic_vector(dat_w-1 downto 0); + ack_i: in std_logic; + adr_o: out std_logic_vector(adr_w-1 downto 0); + sel_o: out std_logic_vector(sel_w-1 downto 0); + we_o: out std_logic; + dat_o: out std_logic_vector(dat_w-1 downto 0); + cyc_o: out std_logic; + stb_o: out std_logic; + + -- misc zpu signals + interrupt: in std_logic; + stack_start: in std_logic_vector(adr_w-1 downto 0); + zpu_status: out std_logic_vector(63 downto 0) + ); + +end zpu_wb_top; + +architecture syn of zpu_wb_top is + +--wishbone interface (records) +signal zpu_wb_i: wishbone_bus_out; +signal zpu_wb_o: wishbone_bus_in; + +begin + +--assign wishbone signals to records +zpu_wb_i.dat <= dat_i; +zpu_wb_i.ack <= ack_i; + +adr_o <= zpu_wb_o.adr; +sel_o <= zpu_wb_o.sel; +we_o <= zpu_wb_o.we; +dat_o <= zpu_wb_o.dat; +cyc_o <= zpu_wb_o.cyc; +stb_o <= zpu_wb_o.stb; + +--instantiate the zpu system +zpu_system0: zpu_system port map( + cpu_clk => clk, + areset => rst, + enable => enb, + interrupt => interrupt, + stack_start => stack_start, + zpu_status => zpu_status, + zpu_wb_i => zpu_wb_i, + zpu_wb_o => zpu_wb_o +); + +end architecture syn; diff --git a/fpga/usrp2/simple_gemac/Makefile.srcs b/fpga/usrp2/simple_gemac/Makefile.srcs index 6480cd5a4..b82e64208 100644 --- a/fpga/usrp2/simple_gemac/Makefile.srcs +++ b/fpga/usrp2/simple_gemac/Makefile.srcs @@ -17,6 +17,7 @@ delay_line.v \ flow_ctrl_tx.v \ flow_ctrl_rx.v \ address_filter.v \ +address_filter_promisc.v \ ll8_to_txmac.v \ rxmac_to_ll8.v \ miim/eth_miim.v \ diff --git a/fpga/usrp2/simple_gemac/address_filter_promisc.v b/fpga/usrp2/simple_gemac/address_filter_promisc.v new file mode 100644 index 000000000..6047e7c93 --- /dev/null +++ b/fpga/usrp2/simple_gemac/address_filter_promisc.v @@ -0,0 +1,32 @@ + + +module address_filter_promisc + (input clk, + input reset, + input go, + input [7:0] data, + output match, + output done); + + reg [2:0] af_state; + + always @(posedge clk) + if(reset) + af_state <= 0; + else + if(go) + af_state <= (data[0] == 1'b0) ? 1 : 7; + else + case(af_state) + 1 : af_state <= 2; + 2 : af_state <= 3; + 3 : af_state <= 4; + 4 : af_state <= 5; + 5 : af_state <= 6; + 6, 7 : af_state <= 0; + endcase // case (af_state) + + assign match = (af_state==6); + assign done = (af_state==6)|(af_state==7); + +endmodule // address_filter_promisc diff --git a/fpga/usrp2/simple_gemac/eth_tasks_f36.v b/fpga/usrp2/simple_gemac/eth_tasks_f36.v index efd72778b..dc64971d4 100644 --- a/fpga/usrp2/simple_gemac/eth_tasks_f36.v +++ b/fpga/usrp2/simple_gemac/eth_tasks_f36.v @@ -4,11 +4,11 @@ task SendFlowCtrl; input [15:0] fc_len; begin $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time); - pause_time <= fc_len; + //pause_time <= fc_len; @(posedge eth_clk); - pause_req <= 1; + //pause_req <= 1; @(posedge eth_clk); - pause_req <= 0; + //pause_req <= 0; $display("Sent Flow Control"); end endtask // SendFlowCtrl diff --git a/fpga/usrp2/simple_gemac/simple_gemac_rx.v b/fpga/usrp2/simple_gemac/simple_gemac_rx.v index b02bb0758..32f517bb3 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_rx.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_rx.v @@ -56,10 +56,10 @@ module simple_gemac_rx else rx_ack <= (rx_state == RX_GOODFRAME); - wire is_ucast, is_bcast, is_mcast, is_pause; - wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | - (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all; - + wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast; + wire keep_packet = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | + (pass_bcast & is_bcast) | (pass_pause & is_pause); + assign rx_data = rxd_del; assign rx_error = (rx_state == RX_ERROR); @@ -79,6 +79,8 @@ module simple_gemac_rx .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done()); address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), .address(48'h0180_c200_0001), .match(is_pause), .done()); + address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), + .match(is_any_ucast), .done()); always @(posedge rx_clk) go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5); diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wb.v b/fpga/usrp2/simple_gemac/simple_gemac_wb.v index 6df277e3e..1ef38be11 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wb.v @@ -1,16 +1,17 @@ module wb_reg #(parameter ADDR=0, - parameter DEFAULT=0) + parameter DEFAULT=0, + parameter WIDTH=32) (input clk, input rst, input [5:0] adr, input wr_acc, - input [31:0] dat_i, output reg [31:0] dat_o); + input [31:0] dat_i, output reg [WIDTH-1:0] dat_o); always @(posedge clk) if(rst) dat_o <= DEFAULT; else if(wr_acc & (adr == ADDR)) - dat_o <= dat_i; + dat_o <= dat_i[WIDTH-1:0]; endmodule // wb_reg @@ -41,19 +42,19 @@ module simple_gemac_wb wire [6:0] misc_settings; assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; - wb_reg #(.ADDR(0),.DEFAULT(7'b0111001)) + wb_reg #(.ADDR(0),.DEFAULT(7'b0111011),.WIDTH(7)) wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(misc_settings) ); - wb_reg #(.ADDR(1),.DEFAULT(0)) + wb_reg #(.ADDR(1),.DEFAULT(0),.WIDTH(16)) wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) ); - wb_reg #(.ADDR(2),.DEFAULT(0)) + wb_reg #(.ADDR(2),.DEFAULT(0),.WIDTH(32)) wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) ); - wb_reg #(.ADDR(3),.DEFAULT(0)) + wb_reg #(.ADDR(3),.DEFAULT(0),.WIDTH(16)) wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) ); - wb_reg #(.ADDR(4),.DEFAULT(0)) + wb_reg #(.ADDR(4),.DEFAULT(0),.WIDTH(32)) wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) ); @@ -80,15 +81,15 @@ module simple_gemac_wb reg [15:0] MIIRX_DATA; wire [2:0] MIISTATUS; - wb_reg #(.ADDR(5),.DEFAULT(0)) + wb_reg #(.ADDR(5),.DEFAULT(0),.WIDTH(9)) wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) ); - wb_reg #(.ADDR(6),.DEFAULT(0)) + wb_reg #(.ADDR(6),.DEFAULT(0),.WIDTH(13)) wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(MIIADDRESS) ); - wb_reg #(.ADDR(7),.DEFAULT(0)) + wb_reg #(.ADDR(7),.DEFAULT(0),.WIDTH(16)) wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(CtrlData) ); @@ -133,11 +134,11 @@ module simple_gemac_wb .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); - wb_reg #(.ADDR(11),.DEFAULT(0)) + wb_reg #(.ADDR(11),.DEFAULT(0),.WIDTH(16)) wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(pause_time) ); - wb_reg #(.ADDR(12),.DEFAULT(0)) + wb_reg #(.ADDR(12),.DEFAULT(0),.WIDTH(16)) wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(pause_thresh) ); diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build index 30f65ab17..9293deca6 100755 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v +iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build index 4be0aac1f..b9475baa2 100755 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v +iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v index 7d57542dc..b61d60d30 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v @@ -44,12 +44,12 @@ module simple_gemac_wrapper19_tb; reg wb_stb=0, wb_cyc=0, wb_we=0; wire wb_ack; - reg [18:0] tx_f19_data=0; + reg [19:0] tx_f19_data=0; reg tx_f19_src_rdy = 0; wire tx_f19_dst_rdy; - wire [35:0] rx_f36_data; - wire rx_f36_src_rdy; - wire rx_f36_dst_rdy = 1; + wire [35:0] rx_f19_data; + wire rx_f19_src_rdy; + wire rx_f19_dst_rdy = 1; simple_gemac_wrapper19 simple_gemac_wrapper19 (.clk125(eth_clk), .reset(reset), @@ -59,7 +59,7 @@ module simple_gemac_wrapper19_tb; .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), //.pause_req(pause_req), .pause_time(pause_time), - .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), + .sys_clk(sys_clk), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we), diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v index 26a471a49..0aadc7e93 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v @@ -24,9 +24,6 @@ module simple_gemac_wrapper_tb; wire [7:0] rx_data, tx_data; - reg [15:0] pause_time; - reg pause_req = 0; - wire GMII_RX_CLK = GMII_GTX_CLK; reg [7:0] FORCE_DAT_ERR = 0; @@ -47,7 +44,7 @@ module simple_gemac_wrapper_tb; reg [35:0] tx_f36_data=0; reg tx_f36_src_rdy = 0; wire tx_f36_dst_rdy; - wire rx_f36_data; + wire [35:0] rx_f36_data; wire rx_f36_src_rdy; wire rx_f36_dst_rdy = 1; @@ -57,7 +54,6 @@ module simple_gemac_wrapper_tb; .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy), diff --git a/fpga/usrp2/timing/time_64bit.v b/fpga/usrp2/timing/time_64bit.v index 33eb2b25a..8122cc6ea 100644 --- a/fpga/usrp2/timing/time_64bit.v +++ b/fpga/usrp2/timing/time_64bit.v @@ -6,7 +6,9 @@ module time_64bit (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, input pps, - output [63:0] vita_time, output pps_int, + output [63:0] vita_time, + output reg [63:0] vita_time_pps, + output pps_int, input exp_time_in, output exp_time_out, output [31:0] debug ); @@ -74,6 +76,10 @@ module time_64bit pps_del <= {pps_del[0],pps_reg}; assign pps_edge = pps_del[0] & ~pps_del[1]; + + always @(posedge clk) + if(pps_edge) + vita_time_pps <= vita_time; always @(posedge clk) if(rst) diff --git a/fpga/usrp2/timing/time_receiver.v b/fpga/usrp2/timing/time_receiver.v index fd8651d29..897f71186 100644 --- a/fpga/usrp2/timing/time_receiver.v +++ b/fpga/usrp2/timing/time_receiver.v @@ -11,9 +11,14 @@ module time_receiver reg [3:0] bit_count; wire [8:0] dataout; reg [8:0] dataout_reg; - + + reg exp_time_in_reg, exp_time_in_reg2; + + always @(posedge clk) exp_time_in_reg <= exp_time_in; + always @(posedge clk) exp_time_in_reg2 <= exp_time_in_reg; + always @(posedge clk) - shiftreg <= {exp_time_in, shiftreg[9:1]}; + shiftreg <= {exp_time_in_reg2, shiftreg[9:1]}; localparam COMMA_0 = 10'h283; localparam COMMA_1 = 10'h17c; @@ -65,7 +70,9 @@ module time_receiver localparam TAIL = 9'h1F7; reg [3:0] state; - + reg [63:0] vita_time_pre; + reg sync_rcvd_pre; + always @(posedge clk) if(rst) state <= STATE_IDLE; @@ -79,42 +86,42 @@ module time_receiver state <= STATE_T0; STATE_T0 : begin - vita_time[63:56] <= dataout_reg[7:0]; + vita_time_pre[63:56] <= dataout_reg[7:0]; state <= STATE_T1; end STATE_T1 : begin - vita_time[55:48] <= dataout_reg[7:0]; + vita_time_pre[55:48] <= dataout_reg[7:0]; state <= STATE_T2; end STATE_T2 : begin - vita_time[47:40] <= dataout_reg[7:0]; + vita_time_pre[47:40] <= dataout_reg[7:0]; state <= STATE_T3; end STATE_T3 : begin - vita_time[39:32] <= dataout_reg[7:0]; + vita_time_pre[39:32] <= dataout_reg[7:0]; state <= STATE_T4; end STATE_T4 : begin - vita_time[31:24] <= dataout_reg[7:0]; + vita_time_pre[31:24] <= dataout_reg[7:0]; state <= STATE_T5; end STATE_T5 : begin - vita_time[23:16] <= dataout_reg[7:0]; + vita_time_pre[23:16] <= dataout_reg[7:0]; state <= STATE_T6; end STATE_T6 : begin - vita_time[15:8] <= dataout_reg[7:0]; + vita_time_pre[15:8] <= dataout_reg[7:0]; state <= STATE_T7; end STATE_T7 : begin - vita_time[7:0] <= dataout_reg[7:0]; + vita_time_pre[7:0] <= dataout_reg[7:0]; state <= STATE_TAIL; end STATE_TAIL : @@ -123,8 +130,11 @@ module time_receiver always @(posedge clk) if(rst) - sync_rcvd <= 0; + sync_rcvd_pre <= 0; else - sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); + sync_rcvd_pre <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); + + always @(posedge clk) sync_rcvd <= sync_rcvd_pre; + always @(posedge clk) vita_time <= vita_time_pre; endmodule // time_sender diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v index e7e798b34..d590b4fb1 100644 --- a/fpga/usrp2/top/u1e/u1e_core.v +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -36,13 +36,13 @@ module u1e_core localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs - wire [7:0] COMPAT_NUM = 8'd2; + wire [7:0] COMPAT_NUM = 8'd3; wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; wire pps_int; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; wire [7:0] set_addr; @@ -299,7 +299,6 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -427,13 +426,26 @@ module u1e_core .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + // ///////////////////////////////////////////////////////////////////////// + // Readback mux 32 -- Slave #7 + + wb_readback_mux_16LE readback_mux_32 + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), + .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + + .word00(vita_time[63:32]), .word01(vita_time[31:0]), + .word02(vita_time_pps[63:32]),.word03(vita_time_pps[31:0]), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(32'b0),.word09(32'b0),.word10(32'b0),.word11(32'b0), + .word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) + ); // ///////////////////////////////////////////////////////////////////////// // VITA Timing time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v index 30b47b818..ab2ed49f0 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/u2_rev3/u2_core.v @@ -3,7 +3,7 @@ // //////////////////////////////////////////////////////////////////////////////// module u2_core - #(parameter RAM_SIZE=32768) + #(parameter RAM_SIZE=16384, parameter RAM_AW=14) (// Clocks input dsp_clk, input wb_clk, @@ -163,7 +163,7 @@ module u2_core wire ram_loader_rst, wb_rst, dsp_rst; assign dsp_rst = wb_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; @@ -180,7 +180,7 @@ module u2_core wire serdes_link_up; wire epoch; wire [31:0] irq; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; wire run_rx, run_tx; reg run_rx_d1; @@ -197,14 +197,14 @@ module u2_core wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; wb_1master #(.decode_w(6), .s0_addr(6'b0000_00),.s0_mask(6'b100000), @@ -257,8 +257,9 @@ module u2_core .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + ////////////////////////////////////////////////////////////////////////////////////////// // Reset Controller system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), @@ -286,13 +287,11 @@ module u2_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, if_dat; + wire [31:0] ram_loader_dat; wire [15:0] ram_loader_adr; - wire [14:0] if_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), @@ -308,36 +307,34 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; + .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone // I-port connects directly to processor and ram loader wire flush_icache; - ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), - .if_adr(if_adr), - .if_data(if_dat), + .if_adr(16'b0), .if_data(), - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), .flush_icache(flush_icache)); @@ -359,34 +356,33 @@ module u2_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 spi_top shared_spi @@ -419,31 +415,25 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd3; + localparam compat_num = 32'd4; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) ); // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), @@ -459,37 +449,39 @@ module u2_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] udp_tx_data, udp_rx_data; - wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; - - udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), - .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), - .debug(debug_udp) ); + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - wire [35:0] tx_err_data, udp1_tx_data; - wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), - .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -691,7 +683,8 @@ module u2_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), @@ -721,13 +714,13 @@ module u2_core // VITA Timing wire [31:0] debug_sync; - + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .debug(debug_sync)); - + // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v index f2bba6c50..759f7b7b8 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.v +++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v @@ -471,7 +471,7 @@ module u2_rev3 // - u2_core #(.RAM_SIZE(32768)) + u2_core #(.RAM_SIZE(16384), .RAM_AW(14)) u2_core(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi index 7c15699db..a7d051630 100644 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -1,231 +1,231 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b808175c_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081764; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401e70_31a01e98_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40668_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8601e78_80000000_99fc2000_f8601e78_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01e8c_bc030010_30600000_b0000000_30630004_be24ffec; -defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01e8c_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01e90_bc030014_30800000_b0000000_e8601e90; -defparam bootram.RAM0.INIT_09=256'h06463800_20e01e98_20c01e98_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; -defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f415f8_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401c8_20e00000_20c00000_80000000_b9f41778_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f415c4_80000000_b9f41780; -defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; -defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; -defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; -defparam bootram.RAM0.INIT_11=256'hb9f4062c_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; -defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01984_10b30000_b9f40da4_10d60000_10b30000; -defparam bootram.RAM0.INIT_13=256'h30a01984_bc120040_aa430001_30a0194c_e061001c_10a30000_be520034_16439003; -defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406c0_b800ffb4_80000000_b9f406cc; -defparam bootram.RAM0.INIT_15=256'h80000000_b9f40694_b800ff88_80000000_b9f406a0_30a0194c_80000000_b9f4155c; -defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f40678_30a01950_80000000_b9f411e8_30a08000_b0000000; -defparam bootram.RAM0.INIT_17=256'hbe030020_30a00050_31000001_30e1001c_30c000f7_f9e10000_a46500ff_3021ffe0; -defparam bootram.RAM0.INIT_18=256'hb810ffe8_30210020_b60f0008_e9e10000_80000000_b9f40330_f081001c_3080005e; -defparam bootram.RAM0.INIT_19=256'h31000001_b9f40280_f9e10000_30e1001c_30c000f7_30a00050_3021ffe0_308000dc; -defparam bootram.RAM0.INIT_1A=256'h3021ffdc_30210020_b60f0008_6463001f_3063ffff_a863005e_e9e10000_e061001c; -defparam bootram.RAM0.INIT_1B=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c_f9e10000; -defparam bootram.RAM0.INIT_1C=256'hb9f40ea8_80000000_b9f4082c_f800200c_80000000_b9f4fe74_f860200c_306000ff; -defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ff6c_80000000_b9f4059c_30a01988_80000000_b9f409ec_80000000; -defparam bootram.RAM0.INIT_1E=256'h30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000_be23017c; -defparam bootram.RAM0.INIT_1F=256'hb0000000_80000000_b9f40558_30a01b04_12c30000_be030068_80000000_b9f41180; -defparam bootram.RAM0.INIT_20=256'hb9f41094_30a08000_b0000000_30c07c00_b9f40e70_30a00000_b0000030_30e08000; -defparam bootram.RAM0.INIT_21=256'he9e10000_30600001_10a00000_b9f41244_80000000_b9f40524_30a01b30_80000000; -defparam bootram.RAM0.INIT_22=256'hb000003f_80000000_b9f404f8_30a01b6c_30210024_b60f0008_eac10020_ea61001c; -defparam bootram.RAM0.INIT_23=256'h80000000_b9f404d4_30a019f8_12630000_be230024_80000000_b9f410fc_30a00000; -defparam bootram.RAM0.INIT_24=256'h30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000_b9f4fd9c; -defparam bootram.RAM0.INIT_25=256'hb9f40490_30a019bc_80000000_b9f41000_30a08000_b0000000_30c07c00_b9f40ddc; -defparam bootram.RAM0.INIT_26=256'h80000000_b9f40474_30a01a50_30600001_b810ff70_10b60000_b9f411b0_80000000; -defparam bootram.RAM0.INIT_27=256'h80000000_b9f40454_30a01ab4_bc230098_80000000_b9f41000_30a00000_b0000018; -defparam bootram.RAM0.INIT_28=256'h80000000_b9f41048_30a00000_b000003f_80000000_b9f40444_30a0199c_b800fed8; -defparam bootram.RAM0.INIT_29=256'hb9f4fda4_b800fe9c_80000000_b9f4fcec_80000000_b9f40424_30a019f8_bc230028; -defparam bootram.RAM0.INIT_2A=256'h30c07c00_b9f40d24_30a00000_b000003f_30e08000_b0000000_b800fe84_10a00000; -defparam bootram.RAM0.INIT_2B=256'hb9f410f8_80000000_b9f403d8_30a019bc_80000000_b9f40f48_30a08000_b0000000; -defparam bootram.RAM0.INIT_2C=256'hb9f4fc60_30a00001_b9f4fd4c_80000000_b9f403c0_30a01a7c_b800fe50_10b30000; -defparam bootram.RAM0.INIT_2D=256'hfa610020_3021ffd4_b800ff40_80000000_b9f410c8_30a00000_b0000018_30a07530; -defparam bootram.RAM0.INIT_2E=256'hfac10024_30e00001_30c1001c_12e70000_f0c1001c_fae10028_10b30000_a66500ff; -defparam bootram.RAM0.INIT_2F=256'h10b30000_10f60000_10d70000_10830000_be030030_12c80000_b9f40898_f9e10000; -defparam bootram.RAM0.INIT_30=256'h10640000_a8830001_6463001f_3063ffff_80000000_b9f407d0_30800001_be76001c; -defparam bootram.RAM0.INIT_31=256'hfac10024_3021ffcc_3021002c_b60f0008_eae10028_eac10024_ea610020_e9e10000; -defparam bootram.RAM0.INIT_32=256'hf9e10000_12c80000_12e70000_13250000_13060000_fb210030_fb01002c_fae10028; -defparam bootram.RAM0.INIT_33=256'h32d6ffff_e0770000_f301001c_30e00002_be76005c_30c1001c_10b90000_fa610020; -defparam bootram.RAM0.INIT_34=256'hbe33ffcc_32f70001_b9f4089c_30a0000a_12630000_33180001_b9f407f8_f061001d; -defparam bootram.RAM0.INIT_35=256'heb210030_eb01002c_eae10028_eac10024_ea610020_e9e10000_10730000_10b90000; -defparam bootram.RAM0.INIT_36=256'h80000000_b9f4f998_f9e10000_3021ffe4_30600001_b810ffe0_30210034_b60f0008; -defparam bootram.RAM0.INIT_37=256'h12660000_fb21002c_fb010028_fae10024_fa61001c_3021ffd0_80000000_b60f0008; -defparam bootram.RAM0.INIT_38=256'haa43ffff_12c00000_b810001c_f9e10000_fac10020_13260000_12e70000_13050000; -defparam bootram.RAM0.INIT_39=256'h10960000_90630060_10b80000_b9f405ec_32730001_bcb2002c_16572001_bc120030; -defparam bootram.RAM0.INIT_3A=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffd4_aa43000a_f0730000; -defparam bootram.RAM0.INIT_3B=256'h3021ffd0_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; -defparam bootram.RAM0.INIT_3C=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; -defparam bootram.RAM0.INIT_3D=256'hb9f4051c_32730001_bcb2002c_16572001_12c00000_b8100014_f9e10000_fac10020; -defparam bootram.RAM0.INIT_3E=256'h14999800_32d60001_be32ffdc_aa43000a_f0730000_10960000_90630060_10b80000; -defparam bootram.RAM0.INIT_3F=256'heb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000_10640000_f0130000; -defparam bootram.RAM1.INIT_00=256'h12e60000_12c50000_fae10024_fac10020_fa61001c_3021ffd8_30210030_b60f0008; -defparam bootram.RAM1.INIT_01=256'hbe32ffec_aa43000a_f0730000_90630060_10b60000_b9f404b0_12660000_f9e10000; -defparam bootram.RAM1.INIT_02=256'heae10024_eac10020_ea61001c_e9e10000_10770000_f0130000_3273ffff_32730001; -defparam bootram.RAM1.INIT_03=256'he9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4_10c50000_30210028_b60f0008; -defparam bootram.RAM1.INIT_04=256'hb60f0008_e9e10000_80000000_b9f40448_f9e10000_3021ffe4_3021001c_b60f0008; -defparam bootram.RAM1.INIT_05=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc_f9e10000_3021ffe4_3021001c; -defparam bootram.RAM1.INIT_06=256'hbe060024_90c30060_12660000_e0660000_f9e10000_fac10020_fa61001c_3021ffdc; -defparam bootram.RAM1.INIT_07=256'h10b60000_be26fff0_90c30060_e0730000_32730001_b9f40324_10b60000_12c50000; -defparam bootram.RAM1.INIT_08=256'hfac1001c_3021ffe0_30210024_b60f0008_10600000_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_09=256'heac1001c_e9e10000_30c0000a_b9f402dc_10b60000_12c50000_b9f4ff9c_f9e10000; -defparam bootram.RAM1.INIT_0A=256'h10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000_30210020_b60f0008_10600000; -defparam bootram.RAM1.INIT_0B=256'h10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000_3021001c_b60f0008_e9e10000; -defparam bootram.RAM1.INIT_0C=256'he9e10000_30c0000a_b9f40278_f9e10000_3021ffe4_3021001c_b60f0008_e9e10000; -defparam bootram.RAM1.INIT_0D=256'hb9f40250_f9e10000_10a00000_12c50000_fac1001c_3021ffe0_3021001c_b60f0008; -defparam bootram.RAM1.INIT_0E=256'hfac1001c_3021ffe0_30210020_b60f0008_eac1001c_e9e10000_10760000_10d60000; -defparam bootram.RAM1.INIT_0F=256'h30210020_b60f0008_eac1001c_e9e10000_10760000_12c60000_b9f40228_f9e10000; -defparam bootram.RAM1.INIT_10=256'h94e08001_3021001c_b60f0008_e9e10000_80000000_b9f401b8_f9e10000_3021ffe4; -defparam bootram.RAM1.INIT_11=256'h80633000_84632000_84c62800_a866ffff_e880f81c_b0000000_9404c001_ac870002; -defparam bootram.RAM1.INIT_12=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f81c_b0000000_f860200c; -defparam bootram.RAM1.INIT_13=256'h88a52000_e880f81c_b0000000_9406c001_acc30002_94608001_80000000_b60f0008; -defparam bootram.RAM1.INIT_14=256'h9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c_b0000000_f8a0200c; -defparam bootram.RAM1.INIT_15=256'ha866ffff_e880f820_b0000000_9404c001_ac870002_94e08001_80000000_b60f0008; -defparam bootram.RAM1.INIT_16=256'h94808001_a4e70002_f860f820_b0000000_f8602020_80633000_84632000_84c62800; -defparam bootram.RAM1.INIT_17=256'hfae10024_fa61001c_3021ffd4_80000000_b60f0008_9404c001_80843800_ac840002; -defparam bootram.RAM1.INIT_18=256'hbe060040_90c30060_13050000_12e60000_e0660000_fac10020_f9e10000_fb010028; -defparam bootram.RAM1.INIT_19=256'h10730000_be120028_16569800_32c70001_b8100014_32600001_be670038_12660000; -defparam bootram.RAM1.INIT_1A=256'h10730000_3273ffff_32730001_be26ffe4_90c30060_c0779800_10b80000_b9f400cc; -defparam bootram.RAM1.INIT_1B=256'h3021ffe4_3021002c_b60f0008_eb010028_eae10024_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_1C=256'hf0c51e7c_3021001c_b60f0008_e9e10000_30c0000a_b9f40084_f9e10000_10a00000; -defparam bootram.RAM1.INIT_1D=256'h80000000_b60f0008_f8653700_64a50405_e4661bac_10c63000_80000000_b60f0008; -defparam bootram.RAM1.INIT_1E=256'h90c60060_b9f4ffc4_10b30000_e0d31e7c_12600000_f9e10000_fa61001c_3021ffe0; -defparam bootram.RAM1.INIT_1F=256'he9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc_32730001_10b30000_e0d31ba8; -defparam bootram.RAM1.INIT_20=256'h12c60000_f9e10000_fac10020_fa61001c_3021ffdc_30210020_b60f0008_ea61001c; -defparam bootram.RAM1.INIT_21=256'hfac5000c_bc03fffc_e8650004_30a33700_64730405_12650000_be120030_aa46000a; -defparam bootram.RAM1.INIT_22=256'hbc32ffd0_aa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_23=256'hf9e10000_fac10020_fa61001c_3021ffdc_64730405_b810ffc8_30c0000d_b9f4ffac; -defparam bootram.RAM1.INIT_24=256'hbc040008_e8830004_30633700_64730405_12650000_be120030_aa46000a_12c60000; -defparam bootram.RAM1.INIT_25=256'haa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000_fac3000c; -defparam bootram.RAM1.INIT_26=256'h30a53700_64a50405_64730405_b810ffc4_80000000_b9f4ff44_30c0000d_be32ffd0; -defparam bootram.RAM1.INIT_27=256'he8650008_30a53700_64a50405_80000000_b60f0008_e8650010_bc03fffc_e8650008; -defparam bootram.RAM1.INIT_28=256'h64a50405_80000000_b60f0008_90630060_be24fff8_e8850008_e8650010_bc030014; -defparam bootram.RAM1.INIT_29=256'h32600001_be230040_e8760008_32c53700_fa61001c_f9e10000_fac10020_3021ffdc; -defparam bootram.RAM1.INIT_2A=256'hbe03ffe8_e8760008_30a00001_b9f401e0_3060ffff_be120034_aa53012d_b8000010; -defparam bootram.RAM1.INIT_2B=256'he9e10000_e8760010_3060ffff_be52000c_16539001_3240012b_3273ffff_32730001; -defparam bootram.RAM1.INIT_2C=256'h32400004_a463000f_e8603324_f8003108_30210024_b60f0008_eac10020_ea61001c; -defparam bootram.RAM1.INIT_2D=256'ha46300ff_64a30008_e4641bb8_10831800_30600004_10831800_beb20010_16439001; -defparam bootram.RAM1.INIT_2E=256'ha4a500ff_be070088_80000000_b60f0008_f8603108_30600080_f8a03104_f8603100; -defparam bootram.RAM1.INIT_2F=256'hf8803110_30800090_f860310c_a0630001_10652800_be23fff8_a4630040_e8603110; -defparam bootram.RAM1.INIT_30=256'haa470001_10800000_be230058_a4630080_e8603110_bc23fff8_a4630002_e8603110; -defparam bootram.RAM1.INIT_31=256'h30e7ffff_e860310c_bc23fff8_a4630002_e8603110_f8603110_30600020_be120038; -defparam bootram.RAM1.INIT_32=256'h30600068_b810ffd0_30600020_be32ffd8_aa470001_30c60001_be07001c_f0660000; -defparam bootram.RAM1.INIT_33=256'ha4a500ff_10640000_b60f0008_f8603110_30600040_10640000_b60f0008_30800001; -defparam bootram.RAM1.INIT_34=256'h306000d0_30600090_be27000c_f860310c_10652800_be23fff8_a4630040_e8603110; -defparam bootram.RAM1.INIT_35=256'h10800000_be23005c_a4630080_e8603110_bc23fff8_a4630002_e8603110_f8603110; -defparam bootram.RAM1.INIT_36=256'hf8803110_bc120030_aa470001_f860310c_30800010_e0660000_30800001_be070068; -defparam bootram.RAM1.INIT_37=256'hbe070028_30e7ffff_be23001c_a4630080_e8603110_bc23fff8_a4630002_e8603110; -defparam bootram.RAM1.INIT_38=256'hb60f0008_f8603110_30600040_10800000_30800050_b810ffd4_b800ffc4_30c60001; -defparam bootram.RAM1.INIT_39=256'hbc260054_a4c30000_b0008000_e8603324_10640000_b60f0008_30800001_10640000; -defparam bootram.RAM1.INIT_3A=256'h80000000_10800000_bc660030_e8c01e80_10660000_be650048_bc430054_e8601e80; -defparam bootram.RAM1.INIT_3B=256'h16443000_30840001_80000000_80000000_80000000_80000000_80000000_80000000; -defparam bootram.RAM1.INIT_3C=256'ha4630007_e8603324_80000000_b60f0008_bc32ffc8_16432800_30630001_bc32ffdc; -defparam bootram.RAM1.INIT_3D=256'h16459001_3240005a_3065ffa9_90a50060_b800ff9c_f8801e80_e4831bc4_10631800; -defparam bootram.RAM1.INIT_3E=256'h3085ffd0_be52000c_16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024; -defparam bootram.RAM1.INIT_3F=256'hf9e10000_fb610034_13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff; -defparam bootram.RAM2.INIT_00=256'haa43003a_13660000_e0790000_fb410030_fb010028_fae10024_fac10020_fa61001c; -defparam bootram.RAM2.INIT_01=256'heb010028_eae10024_eac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034; -defparam bootram.RAM2.INIT_02=256'hc085c800_30a00001_e8c01e84_30210038_b60f0008_eb610034_eb410030_eb21002c; -defparam bootram.RAM2.INIT_03=256'hb810ffac_bc23ffe4_a4630044_c0662000_a4a300ff_be04001c_90840060_30650001; -defparam bootram.RAM2.INIT_04=256'h12761800_66c30404_b9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe; -defparam bootram.RAM2.INIT_05=256'he0b90005_30a0fffd_be38ff74_93040060_e083000b_10791800_fa7b0004_10739800; -defparam bootram.RAM2.INIT_06=256'h66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0; -defparam bootram.RAM2.INIT_07=256'he0b90007_fafb0008_12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006; -defparam bootram.RAM2.INIT_08=256'hbe130060_f07b0000_1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0; -defparam bootram.RAM2.INIT_09=256'hb9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000; -defparam bootram.RAM2.INIT_0A=256'he8fb0004_ea7b000c_d0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000; -defparam bootram.RAM2.INIT_0B=256'headb0008_a74300ff_be52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001; -defparam bootram.RAM2.INIT_0C=256'h107a1800_12c7b000_10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000; -defparam bootram.RAM2.INIT_0D=256'ha6d600ff_1063c000_16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10; -defparam bootram.RAM2.INIT_0E=256'ha4630100_e8603b10_10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff; -defparam bootram.RAM2.INIT_0F=256'ha4a500ff_80884800_a1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8; -defparam bootram.RAM2.INIT_10=256'ha0840100_f8603b18_a46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10; -defparam bootram.RAM2.INIT_11=256'hb60f0008_e8603b00_bc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10; -defparam bootram.RAM2.INIT_12=256'h31200400_31000008_10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000; -defparam bootram.RAM2.INIT_13=256'h3021ffc4_3021001c_b60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001; -defparam bootram.RAM2.INIT_14=256'hb9f4ff3c_fae10034_13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030; -defparam bootram.RAM2.INIT_15=256'hfac03b00_f8603b04_3060000b_66d60408_f8603b10_f8003b18_30600400_12670000; -defparam bootram.RAM2.INIT_16=256'h80000000_b9f4ff00_f8603b10_30600528_f8803b10_30800428_f8603b18_30600001; -defparam bootram.RAM2.INIT_17=256'hf8803b10_30800500_f8603b10_30600400_3261001c_12e00000_12d30000_be18009c; -defparam bootram.RAM2.INIT_18=256'he8803b04_f8610020_e8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8; -defparam bootram.RAM2.INIT_19=256'h30a00010_10800000_beb20034_16459003_22400010_f8610028_e8603b00_f8810024; -defparam bootram.RAM2.INIT_1A=256'hbeb20020_1658b803_12f72800_bc32fff0_16442800_30840001_d0762000_c0732000; -defparam bootram.RAM2.INIT_1B=256'hf8003b18_12d62800_be52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800; -defparam bootram.RAM2.INIT_1C=256'hb0009f00_3021003c_b60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000; -defparam bootram.RAM2.INIT_1D=256'h31200400_b9f4fe34_f9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000; -defparam bootram.RAM2.INIT_1E=256'h3021ffe4_e860f828_b0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000; -defparam bootram.RAM2.INIT_1F=256'h64830008_80000000_b9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000; -defparam bootram.RAM2.INIT_20=256'h16439001_32400015_80000000_b9f40330_a46300ff_be120010_aa440020_a48400ff; -defparam bootram.RAM2.INIT_21=256'hb0000000_b800ffb0_f860f828_b0000000_bc52ffe4_16439001_32400018_bcb2fff0; -defparam bootram.RAM2.INIT_22=256'hb9f4ff40_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824; -defparam bootram.RAM2.INIT_23=256'h80000000_b9f402c8_a4a300ff_be120010_aa440020_a48400ff_64830008_80000000; -defparam bootram.RAM2.INIT_24=256'hb0000000_e0651bbe_bc52ffe4_16459001_32400018_bcb2fff0_16459001_32400015; -defparam bootram.RAM2.INIT_25=256'h10c50000_12c00000_fac1001c_3021ffe0_b800ffa4_f860f824_b0000000_f8a0f828; -defparam bootram.RAM2.INIT_26=256'heac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40334_f9e10000_10b60000; -defparam bootram.RAM2.INIT_27=256'hb810001c_30e1001c_b9f4fd88_f9e10000_30c00040_3021ffa4_30210020_b60f0008; -defparam bootram.RAM2.INIT_28=256'he063001c_10612800_10600000_be520044_16459001_3240003e_30a50001_10a00000; -defparam bootram.RAM2.INIT_29=256'haa440099_e083001c_10612800_30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff; -defparam bootram.RAM2.INIT_2A=256'h3021005c_b60f0008_e9e10000_3021005c_b60f0008_e9e10000_30600001_be32ffc8; -defparam bootram.RAM2.INIT_2B=256'h10b60000_30c00006_b9f4fd08_f9e10000_10f60000_32c1001c_fac10028_3021ffd4; -defparam bootram.RAM2.INIT_2C=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8_30c01bd8; -defparam bootram.RAM2.INIT_2D=256'h65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008_6464001f; -defparam bootram.RAM2.INIT_2E=256'ha4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407_65240405; -defparam bootram.RAM2.INIT_2F=256'h81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800_10842000; -defparam bootram.RAM2.INIT_30=256'h64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008_80634800; -defparam bootram.RAM2.INIT_31=256'ha4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407_65050405; -defparam bootram.RAM2.INIT_32=256'h81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000_10a52800; -defparam bootram.RAM2.INIT_33=256'hb00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff_81294000; -defparam bootram.RAM2.INIT_34=256'h30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000_a6c5ffff; -defparam bootram.RAM2.INIT_35=256'h30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99_b9f4ff6c; -defparam bootram.RAM2.INIT_36=256'h30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008_b9f4ff4c; -defparam bootram.RAM2.INIT_37=256'h30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b_b9f4ff2c; -defparam bootram.RAM2.INIT_38=256'h10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000_b9f4ff0c; -defparam bootram.RAM2.INIT_39=256'h30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020_b9f4feec; -defparam bootram.RAM2.INIT_3A=256'hb6110000_30a0ffff_b9f4e91c_80000000_b9f4f220_f9e10000_3021ffe4_30a01be0; -defparam bootram.RAM2.INIT_3B=256'h22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000_80000000; -defparam bootram.RAM2.INIT_3C=256'h16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c_16479003; -defparam bootram.RAM2.INIT_3D=256'h30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc_bc320040; -defparam bootram.RAM2.INIT_3E=256'h30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028_aa47ffff; -defparam bootram.RAM2.INIT_3F=256'h2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff_30e7ffff; -defparam bootram.RAM3.INIT_00=256'hbc070024_11050000_be030034_a4630003_80662800_10850000_beb20018_16479003; -defparam bootram.RAM3.INIT_01=256'h30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000_11040000; -defparam bootram.RAM3.INIT_02=256'he8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000_b60f0008; -defparam bootram.RAM3.INIT_03=256'h31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c_f8880008; -defparam bootram.RAM3.INIT_04=256'h22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003_22400003; -defparam bootram.RAM3.INIT_05=256'he860193c_10880000_b810ff68_11044000_10c43000_30840004_be52ffec_16479003; -defparam bootram.RAM3.INIT_06=256'h3273fffc_99fc1800_bc120018_aa43ffff_3260193c_f9e10000_fa61001c_3021ffe0; -defparam bootram.RAM3.INIT_07=256'h3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff_e8730000; -defparam bootram.RAM3.INIT_08=256'h30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e7d4_d9e00800; -defparam bootram.RAM3.INIT_09=256'hffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e74c_d9e00800_3021fff8; -defparam bootram.RAM3.INIT_0A=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff_00000000; -defparam bootram.RAM3.INIT_0B=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265; -defparam bootram.RAM3.INIT_0C=256'h53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00; -defparam bootram.RAM3.INIT_0D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; -defparam bootram.RAM3.INIT_0E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; -defparam bootram.RAM3.INIT_0F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; -defparam bootram.RAM3.INIT_10=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; -defparam bootram.RAM3.INIT_11=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; -defparam bootram.RAM3.INIT_12=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; -defparam bootram.RAM3.INIT_13=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; -defparam bootram.RAM3.INIT_14=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; -defparam bootram.RAM3.INIT_15=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; -defparam bootram.RAM3.INIT_16=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; -defparam bootram.RAM3.INIT_17=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; -defparam bootram.RAM3.INIT_18=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; -defparam bootram.RAM3.INIT_19=256'h6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61_756e642e; -defparam bootram.RAM3.INIT_1A=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; -defparam bootram.RAM3.INIT_1B=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068; -defparam bootram.RAM3.INIT_1C=256'h6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d; -defparam bootram.RAM3.INIT_1D=256'h0018000f_ffff0031_01b200d9_05160364_14580a2c_05050400_2e2e2e00_77617265; -defparam bootram.RAM3.INIT_1E=256'hb8080000_b0000000_10101200_06820594_09c407d0_13880d05_00002710_000b0000; -defparam bootram.RAM3.INIT_1F=256'h20202020_28282820_20202828_20202020_00202020_00000000_6f72740a_0a0a6162; -defparam bootram.RAM3.INIT_20=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; -defparam bootram.RAM3.INIT_21=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; -defparam bootram.RAM3.INIT_22=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; -defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4a20400_3a0b0b0b_0bae840c_82700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4df2d_88080b0b_80088408; +defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; +defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; +defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; +defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; +defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; +defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; +defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88; +defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06; +defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; +defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; +defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; +defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; +defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; +defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_f0738306_0b0b0bad_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_992d5050_0b0b0b9e_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_cb2d5050_0b0b0b9f_88087575_80088408; +defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; +defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; +defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae800c_810b0b0b; +defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; +defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; +defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_ff3f0410_81f33f9d; +defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; +defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; +defparam bootram.RAM0.INIT_23=256'hc00c8290_a0800bb5_b5bc0c82_0b0b0b0b_38838080_08822eb9_a138ae84_8008802e; +defparam bootram.RAM0.INIT_24=256'h80808480_b5c00cf8_8082800b_bc0cf880_0b0b0bb5_8080a40b_0c04f880_800bb5c4; +defparam bootram.RAM0.INIT_25=256'h0ba6b00b_c00c0b0b_80940bb5_0c80c0a8_0b0bb5bc_808c0b0b_0480c0a8_0bb5c40c; +defparam bootram.RAM0.INIT_26=256'hae8c0c70_92388412_5270802e_08700852_a338ae8c_c8335170_ff3d0db5_b5c40c04; +defparam bootram.RAM0.INIT_27=256'hb808802e_0b0b0bb5_04803d0d_833d0d04_0bb5c834_70f03881_70085252_2dae8c08; +defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5b8_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; +defparam bootram.RAM0.INIT_29=256'h518bb43f_d0055273_3fb23dfe_5254868c_59923d70_3dfee005_d03d0db2_3d0d0404; +defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_b43fa6b4_52735198_38765378_ff74278f_775481ff_8008b238; +defparam bootram.RAM0.INIT_2B=256'hb039fc3d_858a3fff_39a6ec51_a6b85184_3f91c23f_b4518598_068f38a6_812e0981; +defparam bootram.RAM0.INIT_2C=256'h3fa6f051_e03f86d6_85e13f8e_81a08c0c_fc3f800b_80e45189_81a08c0c_0d81ff0b; +defparam bootram.RAM0.INIT_2D=256'h51547380_70810651_08708d2a_3f81c6b4_805182ed_81ff0655_ee3f8008_84e23f83; +defparam bootram.RAM0.INIT_2E=256'h80805380_82c33f82_a6388151_8008802e_5190b53f_81fc8080_5184bd3f_c338a79c; +defparam bootram.RAM0.INIT_2F=256'hf8518484_3f8a39a7_73519191_5184913f_c43fa7bc_8eaa3f90_fc808051_ffff5281; +defparam bootram.RAM0.INIT_30=256'h5183e53f_9938a8fc_8008802e_518fa03f_3fb0800a_d05183f8_74b238a8_3ffea13f; +defparam bootram.RAM0.INIT_31=256'h8fc63f80_98800a51_5183cd3f_d83fa9b4_800a5190_88df3fb0_3f82ac51_815181f9; +defparam bootram.RAM0.INIT_32=256'h5183a53f_bb3faab0_800a518d_ffff5298_80805380_83ba3f82_38aa8451_08802eaa; +defparam bootram.RAM0.INIT_33=256'h80085480_518f893f_81fc8080_5183913f_ba39ab90_3faad451_a43f8fc9_82ac5188; +defparam bootram.RAM0.INIT_34=256'hac5187e9_82ea3f82_3faab051_80518d80_5281fc80_5380ffff_38828080_08802eb5; +defparam bootram.RAM0.INIT_35=256'h82c63ffc_39a7f851_3f81548a_80518fd5_5187da3f_db3f82ac_a7bc5182_3f8f8e3f; +defparam bootram.RAM0.INIT_36=256'hb7387581_54807425_74ff1656_5a575758_7a7c7f7f_04f83d0d_0c863d0d_e33f7380; +defparam bootram.RAM0.INIT_37=256'hff065185_05527781_538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473; +defparam bootram.RAM0.INIT_38=256'h04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a5186fd_81ff0654_cf3f8008; +defparam bootram.RAM0.INIT_39=256'hd051ff89_81f75280_3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533; +defparam bootram.RAM0.INIT_3A=256'h70525684_02a70533_3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d; +defparam bootram.RAM0.INIT_3B=256'h3f800881_755183b2_76537b52_77259738_2e9e3880_56547380_81ff0670_ef3f8008; +defparam bootram.RAM0.INIT_3C=256'h5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056; +defparam bootram.RAM0.INIT_3D=256'h3d0d04fb_75800c88_83388156_2e098106_567480de_883d3356_a03f800b_80d051ff; +defparam bootram.RAM0.INIT_3E=256'h5581bb3f_06537652_157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779; +defparam bootram.RAM0.INIT_3F=256'h800b800c_51819f3f_3f8a5272_705253cb_0d747653_0d04fe3d_800c873d_e539800b; +defparam bootram.RAM1.INIT_00=256'h81135374_55558439_76787055_04fc3d0d_3f833d0d_528051de_ff3d0d73_843d0d04; +defparam bootram.RAM1.INIT_01=256'h863d0d04_3473800c_e7388073_2e098106_0652718a_800881ff_80087334_5181b23f; +defparam bootram.RAM1.INIT_02=256'h0d04ff3d_1234823d_0533ae90_7251028f_04803d0d_3f833d0d_528051c9_ff3d0d73; +defparam bootram.RAM1.INIT_03=256'hae901333_3d0d8053_3d0d04fe_0c535183_05702272_7510abcc_81ce8005_0d73a029; +defparam bootram.RAM1.INIT_04=256'h0d767856_0d04fc3d_e738843d_53827325_d13f8113_33527251_3fae9413_527251c9; +defparam bootram.RAM1.INIT_05=256'h73a02981_7351df3f_87388d52_2e098106_33537281_38ae9014_09810694_54748a2e; +defparam bootram.RAM1.INIT_06=256'hce800552_73a02981_04ff3d0d_0c863d0d_38748c15_72802ef8_84140853_ce800554; +defparam bootram.RAM1.INIT_07=256'hc6a40870_c2880c81_0d800b81_0d04ff3d_800c833d_38901208_70802ef8_88120851; +defparam bootram.RAM1.INIT_08=256'h2a81c284_800c7088_ff0681c2_70227081_10ae9805_38845170_84712583_8f065151; +defparam bootram.RAM1.INIT_09=256'h81517180_33555354_88059705_0d767802_0d04fd3d_880c833d_800b81c2_0c515181; +defparam bootram.RAM1.INIT_0A=256'h81900b81_81c28c0c_72108107_5170f138_81065151_70862a70_81c29008_2e818638; +defparam bootram.RAM1.INIT_0B=256'h06708132_872a7081_c2900870_70f13881_06515151_812a7081_c2900870_c2900c81; +defparam bootram.RAM1.INIT_0C=256'h0c81c290_7081c290_8338a051_5171812e_b13880e8_3871802e_70802eba_51515151; +defparam bootram.RAM1.INIT_0D=256'hcc398151_34ff1252_70810556_08517074_3881c28c_515170f1_70810651_0870812a; +defparam bootram.RAM1.INIT_0E=256'h535481c2_97053355_78028805_fd3d0d76_853d0d04_0c70800c_0b81c290_883980c0; +defparam bootram.RAM1.INIT_0F=256'h81905170_802e8438_81d05171_81c28c0c_f1387210_51515170_2a708106_90087086; +defparam bootram.RAM1.INIT_10=256'h81067081_70872a70_81c29008_5170f138_81065151_70812a70_81c29008_81c2900c; +defparam bootram.RAM1.INIT_11=256'h2e833890_d0517181_c28c0c80_38733381_802e80c5_80cf3871_5170802e_32515151; +defparam bootram.RAM1.INIT_12=256'h2a708106_90087087_f13881c2_51515170_2a708106_90087081_900c81c2_517081c2; +defparam bootram.RAM1.INIT_13=256'h81c2900c_3980c00b_3981518a_5354ffb7_8114ff13_802e8e38_51515170_70813251; +defparam bootram.RAM1.INIT_14=256'h52717425_70a23870_06515254_0870810a_7581c6a4_04fd3d0d_0c853d0d_80517080; +defparam bootram.RAM1.INIT_15=256'h853d0d04_1252e239_27f13881_868d9f71_74315151_c6ac0870_ac085381_9b3881c6; +defparam bootram.RAM1.INIT_16=256'h06515171_127081ff_269638c9_527180da_ff065152_a9117081_8f0533ff_ff3d0d02; +defparam bootram.RAM1.INIT_17=256'h335358ff_58568076_3d0d797b_3d0d04f9_70800c83_ff065151_d0127081_b9268938; +defparam bootram.RAM1.INIT_18=256'h06721970_147081ff_aa387281_5371782e_81173353_ef38810b_09810682_5371ba2e; +defparam bootram.RAM1.INIT_19=256'h71d83881_70335152_bd387216_71802e82_53515452_06515151_337080c4_33abdd11; +defparam bootram.RAM1.INIT_1A=256'h7084190c_ff067205_3f800881_5252feec_06821733_842b9ff0_fb3f8008_163351fe; +defparam bootram.RAM1.INIT_1B=256'h80068417_8c2bbfe0_cb3f8008_163351fe_828a3883_54fd5374_11335753_7010178b; +defparam bootram.RAM1.INIT_1C=256'h9ff00673_8008842b_53fea93f_85173352_80067305_882b83fe_bb3f8008_335253fe; +defparam bootram.RAM1.INIT_1D=256'h842b9ff0_873f8008_163351fe_88180c87_ff067305_3f800881_5253fe98_05861733; +defparam bootram.RAM1.INIT_1E=256'hff068c19_89057081_d2387410_74742780_52717734_3f800812_5252fdf8_06881733; +defparam bootram.RAM1.INIT_1F=256'h53fdc13f_06723352_842b9ff0_cf3f8008_565152fd_52335552_70708105_08177119; +defparam bootram.RAM1.INIT_20=256'h51515284_065a525b_197081ff_81ff0681_33701a70_17081570_7274348c_80081353; +defparam bootram.RAM1.INIT_21=256'h81ff0673_19703070_05547305_0571882a_08783372_17088818_ffb03884_17087526; +defparam bootram.RAM1.INIT_22=256'h3f800812_5252fce4_068a1533_842b9ff0_f33f8008_515354fc_3356545b_101a8911; +defparam bootram.RAM1.INIT_23=256'h3d0d0480_72800c89_83398053_8539fe53_81068938_77722e09_5152fb53_7081ff06; +defparam bootram.RAM1.INIT_24=256'h337880ff_0d029305_0d04fe3d_f138823d_51515170_2a708106_90087088_3d0d81d6; +defparam bootram.RAM1.INIT_25=256'h7681d680_5170f138_81065151_70882a70_81d69008_80075353_060780c0_067a8c80; +defparam bootram.RAM1.INIT_26=256'h3881d690_72802e96_900c7251_800781d6_980c7182_ff0681d6_900c7581_0c7181d6; +defparam bootram.RAM1.INIT_27=256'h810b81d6_04fc3d0d_0c843d0d_08517080_3881d680_515170f1_70810651_0870882a; +defparam bootram.RAM1.INIT_28=256'h800b81d6_56fee43f_f63d0d7d_863d0d04_51ff873f_53805280_55885480_940c8880; +defparam bootram.RAM1.INIT_29=256'h88a80b81_81d6980c_800c810b_882b81d6_d6840c7c_0c8b0b81_0b81d690_980c8880; +defparam bootram.RAM1.INIT_2A=256'h900c8a80_800b81d6_80d33888_54737627_3f7e5580_900cfeb3_a80b81d6_d6900c8a; +defparam bootram.RAM1.INIT_2B=256'h883d7675_d680085b_84085a81_085981d6_5881d688_81d68c08_0cfe983f_0b81d690; +defparam bootram.RAM1.INIT_2C=256'h57348112_75708105_17517033_27913871_80527173_83387053_53707327_31525790; +defparam bootram.RAM1.INIT_2D=256'hc0526851_70545780_3d0d883d_3d0d04ea_d6980c8c_39800b81_1454ffa9_52ec3972; +defparam bootram.RAM1.INIT_2E=256'h81069438_81aa2e09_2e9d3873_547381ff_17703351_05575574_0284059d_fed23f80; +defparam bootram.RAM1.INIT_2F=256'h5473800c_27d13880_1555be75_548b3981_06853881_992e0981_51547381_74167033; +defparam bootram.RAM1.INIT_30=256'h85f73f80_d8527351_558453ab_fe823f80_84527951_3d705454_f93d0d86_983d0d04; +defparam bootram.RAM1.INIT_31=256'h97053370_fd3d0d02_a0940c04_04810b81_0c893d0d_81557480_81068338_08752e09; +defparam bootram.RAM1.INIT_32=256'h2ba00671_90067483_07077310_88067173_0672812a_71832a84_71872a07_852a8206; +defparam bootram.RAM1.INIT_33=256'h51525351_81d4800c_7081ff06_78872b07_06707207_852b80c0_81ff0676_73070770; +defparam bootram.RAM1.INIT_34=256'hff51ff98_ff9e3f81_5381ff51_81d00a07_74d00a06_04fe3d0d_52853d0d_55525555; +defparam bootram.RAM1.INIT_35=256'h81ff0652_72882a70_51ff813f_873f80e1_3fb251ff_9951ff8c_ff923f81_3f81aa51; +defparam bootram.RAM1.INIT_36=256'hdb3f7290_982a51fe_fee23f72_3f818151_b251fee8_51feed3f_7281ff06_52fef53f; +defparam bootram.RAM1.INIT_37=256'hfeba3fa0_bf3f8e51_3f8051fe_a151fec4_feca3f81_cf3fb051_065253fe_2a7081ff; +defparam bootram.RAM1.INIT_38=256'h8c0cf93d_398c0802_3d0d04ff_fea63f84_ab3f8051_3fa051fe_8051feb0_51feb53f; +defparam bootram.RAM1.INIT_39=256'h800b8c08_0888050c_0508308c_388c0888_088025ab_8c088805_08fc050c_0d800b8c; +defparam bootram.RAM1.INIT_3A=256'h088c0508_fc050c8c_05088c08_0c8c08f4_8c08f405_8838810b_08fc0508_f4050c8c; +defparam bootram.RAM1.INIT_3B=256'h38810b8c_fc050888_050c8c08_0b8c08f0_8c050c80_08308c08_8c088c05_8025ab38; +defparam bootram.RAM1.INIT_3C=256'h81a73f80_88050851_08528c08_8c088c05_050c8053_088c08fc_8c08f005_08f0050c; +defparam bootram.RAM1.INIT_3D=256'h8c08f805_08f8050c_0508308c_388c08f8_08802e8c_8c08fc05_f8050c54_08708c08; +defparam bootram.RAM1.INIT_3E=256'h88050880_050c8c08_0b8c08fc_fb3d0d80_08028c0c_8c0c048c_54893d0d_0870800c; +defparam bootram.RAM1.INIT_3F=256'h8c388c08_05088025_0c8c088c_8c08fc05_050c810b_308c0888_08880508_2593388c; +defparam bootram.RAM2.INIT_00=256'h8c08f805_3f800870_050851ad_528c0888_088c0508_0c81538c_8c088c05_8c050830; +defparam bootram.RAM2.INIT_01=256'h800c5487_f8050870_050c8c08_308c08f8_08f80508_2e8c388c_fc050880_0c548c08; +defparam bootram.RAM2.INIT_02=256'h088c0508_f8050c8c_800b8c08_08fc050c_0d810b8c_8c0cfd3d_048c0802_3d0d8c0c; +defparam bootram.RAM2.INIT_03=256'h088c0508_2499388c_088c0508_38800b8c_08802ea3_8c08fc05_0827ac38_8c088805; +defparam bootram.RAM2.INIT_04=256'h388c088c_802e80c9_08fc0508_0cc9398c_8c08fc05_fc050810_050c8c08_108c088c; +defparam bootram.RAM2.INIT_05=256'hf805088c_050c8c08_318c0888_088c0508_8805088c_a1388c08_88050826_05088c08; +defparam bootram.RAM2.INIT_06=256'h2a8c088c_8c050881_050c8c08_2a8c08fc_fc050881_050c8c08_078c08f8_08fc0508; +defparam bootram.RAM2.INIT_07=256'h8c08f805_0c518d39_8c08f405_88050870_8f388c08_0508802e_398c0890_050cffaf; +defparam bootram.RAM2.INIT_08=256'h56528372_78777956_04fc3d0d_3d0d8c0c_08800c85_8c08f405_f4050c51_08708c08; +defparam bootram.RAM2.INIT_09=256'h72712e09_74335253_a0387433_5271ff2e_b038ff12_5170802e_74078306_278c3874; +defparam bootram.RAM2.INIT_0A=256'h04747454_0c863d0d_38800b80_098106e2_5571ff2e_ff145455_81158115_8106bd38; +defparam bootram.RAM2.INIT_0B=256'h55ffaf39_38707355_718326e9_14545451_118414fc_068f3884_082e0981_51700873; +defparam bootram.RAM2.INIT_0C=256'h83065170_38727507_8f72278c_55555555_7670797b_04fc3d0d_0c863d0d_72713180; +defparam bootram.RAM2.INIT_0D=256'hff2e0981_ff125271_81055634_54337470_72708105_ff2e9838_ff125271_802ea738; +defparam bootram.RAM2.INIT_0E=256'h54087170_72708405_8405530c_54087170_72708405_0d047451_800c863d_06ea3874; +defparam bootram.RAM2.INIT_0F=256'hf0125271_8405530c_54087170_72708405_8405530c_54087170_72708405_8405530c; +defparam bootram.RAM2.INIT_10=256'h387054ff_718326ed_0cfc1252_70840553_05540871_38727084_83722795_8f26c938; +defparam bootram.RAM2.INIT_11=256'ha4528151_e3c63fae_0ce4a83f_3873b5cc_72812e98_84085454_0d800bae_8339fd3d; +defparam bootram.RAM2.INIT_12=256'h51843f00_a53f8008_528151e6_af3faea4_e4913fe3_72b5cc0c_08519b3f_e6bc3f80; +defparam bootram.RAM2.INIT_13=256'hff058171_18841908_d9388188_77802e80_085a545a_0882c811_0d7baea8_ff39f73d; +defparam bootram.RAM2.INIT_14=256'h77065372_81801908_88055656_822b7811_24b53873_e9388074_80742480_2b595559; +defparam bootram.RAM2.INIT_15=256'h57547380_812c5a57_17fc1779_2dff14fc_74085372_53537951_78167008_802eb538; +defparam bootram.RAM2.INIT_16=256'h2dff14fc_74085372_51f8c03f_08a53879_0853bc13_ad38aea8_085877ff_25d63877; +defparam bootram.RAM2.INIT_17=256'h53722d79_51bc1308_ff943972_d2398057_25ffa938_57547380_812c5a57_17fc1779; +defparam bootram.RAM2.INIT_18=256'h5270ff2e_12700852_38702dfc_70ff2e91_70085252_ac0bfc05_ff3d0db5_51f8943f; +defparam bootram.RAM2.INIT_19=256'h523a206d_4552524f_4f4b0000_00000040_3f040000_0404e398_38833d0d_098106f1; +defparam bootram.RAM2.INIT_1A=256'h49484558_20696e20_4261636b_65642120_7475726e_65207265_696d6167_61696e20; +defparam bootram.RAM2.INIT_1B=256'h6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00_64206d6f_206c6f61; +defparam bootram.RAM2.INIT_1C=256'h53746172_6e0a0000_6974696f_55206564_61205a50_756c7472_70657220_72207375; +defparam bootram.RAM2.INIT_1D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; +defparam bootram.RAM2.INIT_1E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; +defparam bootram.RAM2.INIT_1F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; +defparam bootram.RAM2.INIT_20=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; +defparam bootram.RAM2.INIT_21=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; +defparam bootram.RAM2.INIT_22=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; +defparam bootram.RAM2.INIT_23=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; +defparam bootram.RAM2.INIT_24=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; +defparam bootram.RAM2.INIT_25=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; +defparam bootram.RAM2.INIT_26=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; +defparam bootram.RAM2.INIT_27=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; +defparam bootram.RAM2.INIT_28=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; +defparam bootram.RAM2.INIT_29=256'h64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67_204c6f61_756e642e; +defparam bootram.RAM2.INIT_2A=256'h65747572_523a2052_4552524f_2e000000_6d616765_6e672069_61727469_2e205374; +defparam bootram.RAM2.INIT_2B=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; +defparam bootram.RAM2.INIT_2C=256'h64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068_206e6576; +defparam bootram.RAM2.INIT_2D=256'h61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d_696f6e20; +defparam bootram.RAM2.INIT_2E=256'h00202020_0b0b0b0b_01b200d9_05160364_14580a2c_2e2e2e00_77617265_6669726d; +defparam bootram.RAM2.INIT_2F=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; +defparam bootram.RAM2.INIT_30=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; +defparam bootram.RAM2.INIT_31=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; +defparam bootram.RAM2.INIT_32=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; +defparam bootram.RAM2.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_37=256'hffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000_792e6578_64756d6d; +defparam bootram.RAM2.INIT_38=256'h0018000f_ffff0031_05050400_01010100_00001ab4_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_39=256'h00000000_00001a4c_000019f0_00001994_00000000_0000172c_000016e0_000b0000; +defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_000016ec; +defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3E=256'h1234e66d_330eabcd_00000001_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_000b0000_deec0005; +defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_ffffffff_00000000_ffffffff_00000000_00000000; +defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; @@ -233,13 +233,24 @@ defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2B=256'h28282020_20282828_20202020_20202020_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2C=256'h10101010_10101010_10101010_88101010_20202020_20202020_20202020_20202020; -defparam bootram.RAM3.INIT_2D=256'h01010101_01010101_41414101_10414141_10101010_04041010_04040404_04040404; -defparam bootram.RAM3.INIT_2E=256'h02020202_02020202_42424202_10424242_10101010_01010110_01010101_01010101; -defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_10101020_02020210_02020202_02020202; +defparam bootram.RAM3.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_33=256'h01010100_00001948_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001d70_ffffffff; +defparam bootram.RAM3.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v index 4e0b190ef..3edb539f7 100644 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -131,7 +131,7 @@ module u2plus_core output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); - localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_BUF_POOL = 64; // router localparam SR_UDP_SM = 96; // 64 regs localparam SR_RX_DSP = 160; // 16 localparam SR_RX_CTRL = 176; // 16 @@ -153,9 +153,9 @@ module u2plus_core wire [31:0] set_data, set_data_dsp; wire set_stb, set_stb_dsp; - wire wb_rst, dsp_rst; + reg wb_rst; wire dsp_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; wire proc_int, overrun, underrun; wire [3:0] uart_tx_int, uart_rx_int; @@ -173,7 +173,7 @@ module u2plus_core wire serdes_link_up; wire epoch; wire [31:0] irq; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; wire run_rx, run_tx; // /////////////////////////////////////////////////////////////////////////////////////////////// @@ -197,21 +197,21 @@ module u2plus_core wb_1master #(.decode_w(8), .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM - .s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool - .s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI - .s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C - .s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO - .s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback - .s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC - .s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K) - .s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC - .s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused - .sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART - .sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR - .sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused - .sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP - .se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash - .sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // 16K-20K, Buffer Pool + .s2_addr(8'b0110_0000),.s2_mask(8'b1111_1111), // SPI + .s3_addr(8'b0110_0001),.s3_mask(8'b1111_1111), // I2C + .s4_addr(8'b0110_0010),.s4_mask(8'b1111_1111), // GPIO + .s5_addr(8'b0110_0011),.s5_mask(8'b1111_1111), // Readback + .s6_addr(8'b0110_0100),.s6_mask(8'b1111_1111), // Ethernet MAC + .s7_addr(8'b0101_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b0110_0101),.s8_mask(8'b1111_1111), // PIC + .s9_addr(8'b0110_0110),.s9_mask(8'b1111_1111), // Unused + .sa_addr(8'b0110_0111),.sa_mask(8'b1111_1111), // UART + .sb_addr(8'b0110_1000),.sb_mask(8'b1111_1111), // ATR + .sc_addr(8'b0110_1001),.sc_mask(8'b1111_1111), // Unused + .sd_addr(8'b0110_1010),.sd_mask(8'b1111_1111), // ICAP + .se_addr(8'b0110_1011),.se_mask(8'b1111_1111), // SPI Flash + .sf_addr(8'b1000_0000),.sf_mask(8'b1100_0000), // 32-48K, Main RAM .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -251,35 +251,75 @@ module u2plus_core ////////////////////////////////////////////////////////////////////////////////////////// // Reset Controller - + + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + wire por_rst; + wire [aw-1:0] cpu_adr; + wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)? + 16'hfff8 : //top of 8K boot ram re-purposed at 56K + 16'h1ff8 ; //top of 8K boot ram + + //When the main program runs, it will try to access system ram at 0. + //This logic re-maps the cpu address to force select the system ram. + assign m0_adr = + (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_WAIT)? cpu_adr : ( //in bootloader + (cpu_adr[15:14] == 2'b00)? {2'b10, cpu_adr[13:0]} : ( //map 0-16 to 32-48 (main ram) + (cpu_adr[15:13] == 3'b111)? {3'b000, cpu_adr[12:0]} : ( //map 56-64 to 0-8 (boot ram) + cpu_adr))); //otherwise + + system_control sysctrl ( + .wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) + ); + + always @(posedge wb_clk) + if(por_rst) begin + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; + wb_rst <= 1'b1; + end + else begin + case(cpu_bldr_ctrl_state) + + CPU_BLDR_CTRL_WAIT: begin + wb_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; + wb_rst <= 1'b1; + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + wb_rst <= 1'b0; + end + + endcase //cpu_bldr_ctrl_state + end + // ///////////////////////////////////////////////////////////////////////// // Processor - wire [31:0] if_dat; - wire [15:0] if_adr; - - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst), // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - + .stack_start(cpu_sp_init), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone // I-port connects directly to processor - wire [31:0] if_dat_boot, if_dat_main; - assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot; - bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(if_adr[12:0]), .if_data(if_dat_boot), + .if_adr(13'b0), .if_data(), .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); @@ -289,10 +329,10 @@ module u2plus_core `include "bootloader.rmi" - ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) + ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .if_adr(if_adr[14:0]), .if_data(if_dat_main), - .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); // ///////////////////////////////////////////////////////////////////////// @@ -310,34 +350,33 @@ module u2plus_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 spi_top shared_spi @@ -370,31 +409,25 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd3; + localparam compat_num = 32'd4; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) ); // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), @@ -410,36 +443,38 @@ module u2plus_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] udp_tx_data, udp_rx_data; - wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; - - udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), - .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), - .debug(debug_udp) ); + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - wire [35:0] tx_err_data, udp1_tx_data; - wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), - .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 @@ -471,6 +506,8 @@ module u2plus_core .in(set_data),.out(adc_outs),.changed()); setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); + setting_reg #(.my_addr(5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(bldr_done),.changed()); // ///////////////////////////////////////////////////////////////////////// // LEDS @@ -555,7 +592,7 @@ module u2plus_core // ICAP for reprogramming the FPGA, Slave #13 (D) s3a_icap_wb s3a_icap_wb - (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), + (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); // ///////////////////////////////////////////////////////////////////////// @@ -652,7 +689,8 @@ module u2plus_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), @@ -681,10 +719,13 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // VITA Timing + wire [31:0] debug_sync; + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v index a18eb73ae..c642842f6 100644 --- a/fpga/usrp2/udp/prot_eng_tx.v +++ b/fpga/usrp2/udp/prot_eng_tx.v @@ -7,6 +7,8 @@ // Odd means the last word is half full // Flags[1:0] is {eop, sop} // Protocol word format is: +// 21 UDP Source Port Here +// 20 UDP Dest Port Here // 19 Last Header Line // 18 IP Header Checksum XOR // 17 IP Length Here @@ -34,28 +36,40 @@ module prot_eng_tx assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); - localparam HDR_WIDTH = 16 + 4; // 16 bits plus flags + localparam HDR_WIDTH = 16 + 6; // 16 bits plus flags localparam HDR_LEN = 32; // Up to 64 bytes of protocol // Store header values in a small dual-port (distributed) ram reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; wire [HDR_WIDTH-1:0] header_word; - reg [15:0] chk_precompute; - + + reg [1:0] port_sel; + reg [31:0] per_port_data[0:3]; + reg [15:0] udp_src_port, udp_dst_port, chk_precompute; + + always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; + always @(posedge clk) udp_dst_port <= per_port_data[port_sel][15:0]; + always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) - begin - header_ram[set_addr[4:0]] <= set_data; - if(set_data[18]) - chk_precompute <= set_data[15:0]; - end + header_ram[set_addr[4:0]] <= set_data; + + always @(posedge clk) + if(set_stb & (set_addr == (BASE + 14))) + chk_precompute <= set_data[15:0]; + + always @(posedge clk) + if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) + per_port_data[set_addr[1:0]] <= set_data; - assign header_word = header_ram[state]; + wire do_udp_src_port = header_word[21]; + wire do_udp_dst_port = header_word[20]; + wire last_hdr_line = header_word[19]; + wire do_ip_chk = header_word[18]; + wire do_ip_len = header_word[17]; + wire do_udp_len = header_word[16]; - wire last_hdr_line = header_word[19]; - wire ip_chk = header_word[18]; - wire ip_len = header_word[17]; - wire udp_len = header_word[16]; + assign header_word = header_ram[state]; // Protocol State Machine reg [15:0] length; @@ -75,6 +89,7 @@ module prot_eng_tx 0 : begin fast_path <= datain[0]; + port_sel <= datain[2:1]; state <= 1; end 1 : @@ -113,15 +128,18 @@ module prot_eng_tx checksum_reg <= checksum; always @* - if(ip_chk) - //dataout_int <= header_word[15:0] ^ ip_length; + if(do_payload) + dataout_int <= datain[15:0]; + else if(do_ip_chk) dataout_int <= 16'hFFFF ^ checksum_reg; - else if(ip_len) + else if(do_ip_len) dataout_int <= ip_length; - else if(udp_len) + else if(do_udp_len) dataout_int <= udp_length; - else if(do_payload) - dataout_int <= datain[15:0]; + else if(do_udp_src_port) + dataout_int <= udp_src_port; + else if(do_udp_dst_port) + dataout_int <= udp_dst_port; else dataout_int <= header_word[15:0]; diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v index e7ffeb5e1..c8fffe605 100644 --- a/fpga/usrp2/udp/prot_eng_tx_tb.v +++ b/fpga/usrp2/udp/prot_eng_tx_tb.v @@ -80,7 +80,7 @@ module prot_eng_tx_tb(); begin count <= 4; src_rdy_f36i <= 1; - f36_data <= 32'h0001_000c; + f36_data <= 32'h0003_000c; f36_sof <= 1; f36_eof <= 0; f36_occ <= 0; @@ -140,16 +140,23 @@ module prot_eng_tx_tb(); @(negedge rst); @(posedge clk); WriteSREG(BASE, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234}); - WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678}); - WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+1, {11'b0, 5'h00, 16'h0000}); + WriteSREG(BASE+2, {11'b0, 5'h00, 16'hABCD}); + WriteSREG(BASE+3, {11'b0, 5'h00, 16'h1234}); + WriteSREG(BASE+4, {11'b0, 5'h00, 16'h5678}); + WriteSREG(BASE+5, {11'b0, 5'h00, 16'hF00D}); + WriteSREG(BASE+6, {11'b0, 5'h00, 16'hBEEF}); + WriteSREG(BASE+7, {11'b0, 5'h10, 16'hDCBA}); + WriteSREG(BASE+8, {11'b0, 5'h00, 16'h4321}); + WriteSREG(BASE+9, {11'b0, 5'h04, 16'hABCD}); + WriteSREG(BASE+10, {11'b0, 5'h08, 16'hABCD}); @(posedge clk); + + WriteSREG(BASE+24, 16'h6666); + WriteSREG(BASE+25, 16'h7777); + WriteSREG(BASE+26, 16'h8888); + WriteSREG(BASE+27, 16'h9999); + PutPacketInFIFO36(32'hA0B0C0D0,16); @(posedge clk); @(posedge clk); diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v index 44bb7b548..cc34cceed 100644 --- a/fpga/usrp2/vrt/gen_context_pkt.v +++ b/fpga/usrp2/vrt/gen_context_pkt.v @@ -1,7 +1,8 @@ module gen_context_pkt - #(parameter PROT_ENG_FLAGS=1) + #(parameter PROT_ENG_FLAGS=1, + parameter DSP_NUMBER=0) (input clk, input reset, input clear, input trigger, output sent, input [31:0] streamid, @@ -67,10 +68,10 @@ module gen_context_pkt endcase // case (ctxt_state) assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); - + always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd28 }; // UDP port 1 or 3 CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v index 2ec78189b..6f567668d 100644 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ b/fpga/usrp2/vrt/vita_tx_chain.v @@ -5,7 +5,8 @@ module vita_tx_chain parameter REPORT_ERROR=0, parameter DO_FLOW_CONTROL=0, parameter PROT_ENG_FLAGS=0, - parameter USE_TRANS_HEADER=0) + parameter USE_TRANS_HEADER=0, + parameter DSP_NUMBER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, @@ -71,7 +72,7 @@ module vita_tx_chain wire [35:0] flow_data, err_data_int; wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), @@ -82,7 +83,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .packet_consumed(packet_consumed), .trigger(trigger)); - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v index ab6da8bd0..e966d987c 100644 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ b/fpga/usrp2/vrt/vita_tx_control.v @@ -17,14 +17,12 @@ module vita_tx_control // To DSP Core output [WIDTH-1:0] sample, - output run, + output reg run, input strobe, output [31:0] debug ); - assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16]; - wire [63:0] send_time = sample_fifo_i[63:0]; wire [15:0] seqnum = sample_fifo_i[79:64]; wire eop = sample_fifo_i[80]; @@ -169,11 +167,39 @@ module vita_tx_control send_error <= 0; endcase // case (ibs_state) + assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout - assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); + + assign sample = (ibs_state == IBS_RUN) ? sample_fifo_i[5+64+16+WIDTH-1:5+64+16] : {WIDTH{1'b0}}; + //assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); assign error = send_error; assign ack = send_ack; + localparam MAX_IDLE = 1000000; + // approx 10 ms timeout with a 100 MHz clock, but burning samples will slow that down + reg [19:0] countdown; + + always @(posedge clk) + if(reset | clear) + begin + run <= 0; + countdown <= 0; + end + else + if (ibs_state == IBS_RUN) + if(eob & eop & strobe & sample_fifo_src_rdy_i) + run <= 0; + else + begin + run <= 1; + countdown <= MAX_IDLE; + end + else + if (countdown == 0) + run <= 0; + else + countdown <= countdown - 1; + always @(posedge clk) if(reset | clear) packet_consumed <= 0; |