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-rw-r--r--fpga/usrp2/vrt/vita_rx_chain.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v
index ca2f847bc..2788dc9d5 100644
--- a/fpga/usrp2/vrt/vita_rx_chain.v
+++ b/fpga/usrp2/vrt/vita_rx_chain.v
@@ -41,7 +41,7 @@ module vita_rx_chain
wire clear;
assign clear_o = clear;
wire clear_int;
- setting_reg #(.my_addr(BASE+3)) sr
+ setting_reg #(.my_addr(BASE+8)) sr
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_int));