diff options
Diffstat (limited to 'fpga/usrp2/vrt')
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_control.v | 39 |
1 files changed, 27 insertions, 12 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v index 39f32d7fe..daec734a8 100644 --- a/fpga/usrp2/vrt/vita_rx_control.v +++ b/fpga/usrp2/vrt/vita_rx_control.v @@ -46,13 +46,13 @@ module vita_rx_control wire [63:0] rcvtime_pre; reg [63:0] rcvtime; - wire [28:0] numlines_pre; - wire send_imm_pre, chain_pre, reload_pre; + wire [27:0] numlines_pre; + wire send_imm_pre, chain_pre, reload_pre, stop_pre; reg send_imm, chain, reload; wire read_ctrl, not_empty_ctrl, write_ctrl; reg sc_pre2; wire [33:0] fifo_line; - reg [28:0] lines_left, lines_total; + reg [27:0] lines_left, lines_total; reg [2:0] ibs_state; wire now, early, late; wire sample_fifo_in_rdy; @@ -83,7 +83,7 @@ module vita_rx_control fifo_short #(.WIDTH(96)) commandfifo (.clk(clk),.reset(reset),.clear(clear), .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(), - .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), + .dataout({send_imm_pre,chain_pre,reload_pre,stop_pre,numlines_pre,rcvtime_pre}), .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl), .occupied(command_queue_len), .space() ); @@ -97,7 +97,7 @@ module vita_rx_control localparam IBS_LATECMD = 6; localparam IBS_ZEROLEN = 7; - wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & (numlines_pre==0))); + wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & stop_pre)); wire signal_overrun = (ibs_state == IBS_OVERRUN); wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN); wire signal_latecmd = (ibs_state == IBS_LATECMD); @@ -121,10 +121,19 @@ module vita_rx_control time_compare time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late)); - wire too_late = late & ~send_imm; wire go_now = now | send_imm; wire full = ~sample_fifo_in_rdy; + reg too_late; + + always @(posedge clk) + if(reset | clear) + too_late <= 0; + else + too_late <= late & ~send_imm; + + reg late_valid; + always @(posedge clk) if(reset | clear) begin @@ -135,6 +144,7 @@ module vita_rx_control send_imm <= 0; chain <= 0; reload <= 0; + late_valid <= 0; end else case(ibs_state) @@ -144,7 +154,8 @@ module vita_rx_control lines_left <= numlines_pre; lines_total <= numlines_pre; rcvtime <= rcvtime_pre; - if(numlines_pre == 0) + late_valid <= 0; + if(stop_pre) ibs_state <= IBS_ZEROLEN; else ibs_state <= IBS_WAITING; @@ -153,10 +164,14 @@ module vita_rx_control reload <= reload_pre; end IBS_WAITING : - if(go_now) - ibs_state <= IBS_RUNNING; - else if(too_late) - ibs_state <= IBS_LATECMD; + begin + late_valid <= 1; + if(late_valid) + if(go_now) + ibs_state <= IBS_RUNNING; + else if(too_late) + ibs_state <= IBS_LATECMD; + end IBS_RUNNING : if(strobe) if(full) @@ -182,7 +197,7 @@ module vita_rx_control send_imm <= send_imm_pre; chain <= chain_pre; reload <= reload_pre; - if(numlines_pre == 0) // If we are told to stop here + if(stop_pre) // If we are told to stop here ibs_state <= IBS_IDLE; else ibs_state <= IBS_RUNNING; |