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-rw-r--r--fpga/usrp2/vrt/vita_rx_chain.v29
1 files changed, 25 insertions, 4 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v
index 1986743b3..8b41e5fa8 100644
--- a/fpga/usrp2/vrt/vita_rx_chain.v
+++ b/fpga/usrp2/vrt/vita_rx_chain.v
@@ -50,11 +50,32 @@ module vita_rx_chain
.data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int),
.debug_rx(vrf_debug) );
- dsp_framer36 #(.BUF_SIZE(FIFOSIZE),
- .PORT_SEL(UNIT),
- .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp0_framer36
- (.clk(clk), .reset(reset), .clear(clear),
+ wire [FIFOSIZE-1:0] access_adr, access_len;
+ wire access_we, access_stb, access_ok, access_done, access_skip_read;
+ wire [35:0] dsp_to_buf, buf_to_dsp;
+ wire [35:0] rx_data_int2;
+ wire rx_src_rdy_int2, rx_dst_rdy_int2;
+
+ double_buffer #(.BUF_SIZE(FIFOSIZE)) db
+ (.clk(clk),.reset(reset),.clear(clear),
+ .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
+ .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
+ .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),
+
.data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int),
+ .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2));
+
+ dspengine_16to8 #(.BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_16to8
+ (.clk(clk),.reset(reset),.clear(clear),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
+ .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
+ .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
+
+ add_routing_header #(.PORT_SEL(UNIT),
+ .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp_routing_header
+ (.clk(clk), .reset(reset), .clear(clear),
+ .data_i(rx_data_int2), .src_rdy_i(rx_src_rdy_int2), .dst_rdy_o(rx_dst_rdy_int2),
.data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) );
assign debug = vrc_debug; // | vrf_debug;