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Diffstat (limited to 'fpga/usrp2/vrt/vita_tx_control.v')
-rw-r--r--fpga/usrp2/vrt/vita_tx_control.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v
index e966d987c..14b97a215 100644
--- a/fpga/usrp2/vrt/vita_tx_control.v
+++ b/fpga/usrp2/vrt/vita_tx_control.v
@@ -71,7 +71,7 @@ module vita_tx_control
wire [31:0] error_policy;
setting_reg #(.my_addr(BASE+3)) sr_error_policy
- (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(error_policy),.changed());
wire policy_wait = error_policy[0];