1 files changed, 24 insertions, 15 deletions

diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v
index d0516bec8..20ad6b995 100644
--- a/fpga/usrp2/vrt/vita_tx_control.v
+++ b/fpga/usrp2/vrt/vita_tx_control.v
@@ -6,9 +6,10 @@ module vita_tx_control
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     
     input [63:0] vita_time,
-    output error,
+    output error, output ack,
     output reg [31:0] error_code,
-
+    output reg packet_consumed,
+    
     // From vita_tx_deframer
     input [5+64+16+WIDTH-1:0] sample_fifo_i,
     input sample_fifo_src_rdy_i,
@@ -37,9 +38,8 @@ module vita_tx_control
    // FIXME ignore too_early for now for timing reasons
    assign too_early = 0;
    time_compare 
-     time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), 
-		   .late(late), .too_early());
-//		   .late(late), .too_early(too_early));
+     time_compare (.time_now(vita_time), .trigger_time(send_time), 
+		   .now(now), .early(early), .late(late), .too_early());
    
    localparam IBS_IDLE = 0;
    localparam IBS_RUN = 1;  // FIXME do we need this?
@@ -48,6 +48,7 @@ module vita_tx_control
    localparam IBS_ERROR_DONE = 4;
    localparam IBS_ERROR_WAIT = 5;
 
+   wire [31:0] CODE_EOB_ACK = {seqnum,16'd1};
    wire [31:0] CODE_UNDERRUN = {seqnum,16'd2};
    wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4};
    wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8};
@@ -56,11 +57,6 @@ module vita_tx_control
    
    reg [2:0] ibs_state;
 
-   wire      clear_state;
-   setting_reg #(.my_addr(BASE+1)) sr
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_state));
-   
    wire [31:0] error_policy;
    setting_reg #(.my_addr(BASE+3)) sr_error_policy
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -69,13 +65,15 @@ module vita_tx_control
    wire        policy_wait = error_policy[0];
    wire        policy_next_packet = error_policy[1];
    wire        policy_next_burst = error_policy[2];
-   reg 	       send_error;
+   reg 	       send_error, send_ack;
    
    always @(posedge clk)
-     if(reset | clear_state)
+     if(reset | clear)
        begin
 	  ibs_state <= IBS_IDLE;
 	  send_error <= 0;
+	  send_ack <= 0;
+	  error_code <= 0;
        end
      else
        case(ibs_state)
@@ -106,7 +104,11 @@ module vita_tx_control
 	       end
 	     else if(eop)
 	       if(eob)
-		 ibs_state <= IBS_IDLE;
+		 begin
+		    ibs_state <= IBS_ERROR_DONE;  // Not really an error
+		    error_code <= CODE_EOB_ACK;
+		    send_ack <= 1;
+		 end
 	       else
 		 ibs_state <= IBS_CONT_BURST;
 
@@ -145,6 +147,7 @@ module vita_tx_control
 	 IBS_ERROR_DONE :
 	   begin
 	      send_error <= 0;
+	      send_ack <= 0;
 	      ibs_state <= IBS_IDLE;
 	   end
 	 
@@ -154,10 +157,16 @@ module vita_tx_control
 
    assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN));  // FIXME also cleanout
    assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
-   //assign error = (ibs_state == IBS_ERROR_DONE);
    assign error = send_error;
+   assign ack = send_ack;
 
-   assign debug = { { now,early,late,too_early,eop,eob,sob,send_at },
+   always @(posedge clk)
+     if(reset | clear)
+       packet_consumed <= 0;
+     else
+       packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o;
+   
+   assign debug = { { now,early,late,ack,eop,eob,sob,send_at },
 		    { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] },
 		    { 8'b0 },
 		    { 8'b0 } };