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-rw-r--r--fpga/usrp2/udp/add_onescomp.v12
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diff --git a/fpga/usrp2/udp/add_onescomp.v b/fpga/usrp2/udp/add_onescomp.v
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+
+
+module add_onescomp
+ #(parameter WIDTH = 16)
+ (input [WIDTH-1:0] A,
+ input [WIDTH-1:0] B,
+ output [WIDTH-1:0] SUM);
+
+ wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
+ assign SUM = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
+
+endmodule // add_onescomp