diff options
Diffstat (limited to 'fpga/usrp2/top')
59 files changed, 9539 insertions, 0 deletions
diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore new file mode 100644 index 000000000..0d90f1698 --- /dev/null +++ b/fpga/usrp2/top/.gitignore @@ -0,0 +1,2 @@ +/*.sav +build* diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common new file mode 100644 index 000000000..6f855a070 --- /dev/null +++ b/fpga/usrp2/top/Makefile.common @@ -0,0 +1,62 @@ +# +# Copyright 2008, 2009, 2010 Ettus Research LLC +# + +################################################## +# Constants +################################################## +ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.) +ifeq ($(ISE_VER),10) + ISE_EXT = ise +else + ISE_EXT = xise +endif +BASE_DIR = $(abspath ..) +ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py +ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) +BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin +BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit +MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs + +################################################## +# Global Targets +################################################## +all: bin + +proj: $(ISE_FILE) + +check: $(ISE_FILE) + $(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf + $(ISE_HELPER) "Check Syntax" + +synth: $(ISE_FILE) + $(ISE_HELPER) "Synthesize - XST" + +bin: check $(BIN_FILE) + $(ISE_HELPER) "Generate Programming File" + +mcs: $(MCS_FILE) + +clean: + $(RM) -r $(BUILD_DIR) + +.PHONY: all proj check synth bin mcs clean + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: +$(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "" + +$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "Generate Programming File" + touch $@ + +$(MCS_FILE): $(BIN_FILE) + promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIT_FILE) + +.EXPORT_ALL_VARIABLES: diff --git a/fpga/usrp2/top/eth_test/.gitignore b/fpga/usrp2/top/eth_test/.gitignore new file mode 100644 index 000000000..b30397081 --- /dev/null +++ b/fpga/usrp2/top/eth_test/.gitignore @@ -0,0 +1,43 @@ +/xst +/_ngo +/_xmsgs +/*.stx +/*.tspec +/*.xml +/*.gyd +/*.ngr +/*.tim +/*.err +/*.lso +/*.bld +/*.cmd_log +/*.ise_ISE_Backup +/*.mfd +/*.vm6 +/*.syr +/*.xst +/*.csv +/*.html +/*.jed +/*.pad +/*.ng* +/*.pnx +/*.rpt +/*.prj +/*_html +/*_log +/*.lfp +/*.bit +/*.bin +/*.vcd +/*.unroutes +/*.drc +/*_map.* +/*_guide.* +/*.twr +/*.twx +/a.out +/*.xpi +/*_pad.txt +/*.bgn +/*.par diff --git a/fpga/usrp2/top/eth_test/eth_sim_top.v b/fpga/usrp2/top/eth_test/eth_sim_top.v new file mode 100644 index 000000000..640a4e60f --- /dev/null +++ b/fpga/usrp2/top/eth_test/eth_sim_top.v @@ -0,0 +1,437 @@ +////////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_basic +////////////////////////////////////////////////////////////////////////////////// + +module eth_sim_top + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output led1, + output led2, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + input PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] ser_debug; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + parameter dw = 32; // Data bus width + parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i; + wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel; + wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack; + wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb; + wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc; + wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err; + wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty; + wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we; + + wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01), + .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010), + .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty) + ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we; + wire [3:0] iram_wr_sel; + wire [aw-1:0] iram_wr_adr, iram_rd_adr; + wire [dw-1:0] iram_wr_dat, iram_rd_dat; + + wire bus_error, proc_int; + + assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0; + assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack; + + ram_loader #(.AWIDTH(16)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start), + .mode_o(cpld_mode), + .done_o(cpld_done), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr), + .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel), + .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack), + .ram_loader_done_o(ram_loader_done)); + + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr), + .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + assign proc_int = 1'b0; + + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + ram_wb_harvard #(.AWIDTH(14)) + ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat), + .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb), + .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel), + + .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel)); + + assign s0_err = 1'b0; + assign s0_rty = 1'b0; + + // Buffer Pool, slave #1 + wire rd0_read, rd0_ready, rd0_done, rd0_empty; + wire rd1_read, rd1_ready, rd1_done, rd1_empty; + wire rd2_read, rd2_ready, rd2_done, rd2_empty; + wire rd3_read, rd3_ready, rd3_done, rd3_empty; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_write, wr0_done, wr0_ready, wr0_full; + wire wr1_write, wr1_done, wr1_ready, wr1_full; + wire wr2_write, wr2_done, wr2_ready, wr2_full; + wire wr3_write, wr3_done, wr3_ready, wr3_full; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + +/* + buffer_pool buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), + + .stream_clk(dsp_clk),.stream_rst(dsp_rst), + // Write Interfaces + .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(), + .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(), + .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(), + .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(), + // Read Interfaces + .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty), + .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty), + .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty), + .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty) + ); +*/ + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i), + .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack), + + .wb_err_o(s2_err),.wb_int_o(s2_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + assign s2_rty = 1'b0; + + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(st_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_err = 1'b0; + assign s3_rty = 1'b0; + + // GPIOs -- Slave #4 + wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d; + assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d; + + simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a), + .gpio(/* io_tx[7:0]*/) ); + + simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b), + .gpio(/* io_tx[15:8] */) ); + + simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c), + .gpio(/* io_rx[7:0] */) ); + + simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d), + .gpio(/* io_rx[15:8]*/) ); + + assign s4_err = 1'b0; + assign s4_rty = 1'b0; + + // Output control lines, SLAVE #5 + wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0]; + assign {led2, led1} = misc_outs[1:0]; + + wb_output_pins32 control_lines + (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i), + .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc), + .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) ); + + assign s5_err = 1'b0; + assign s5_rty = 1'b0; + + // Ethernet slave, #6 + eth_wrapper eth_wrapper + (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(), + .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode + .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER), + .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL), + .Mdio(MDIO),.Mdc(MDC), + // FIFO Interfaces + .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(), + .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(), + // Wishbone + .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack) + ); + + assign s6_err = 1'b0; + assign s6_rty = 1'b0; + + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_err = 1'b0; + assign s7_rty = 1'b0; + assign s7_dat_i = 32'd0; + + /////////////////////////////////////////////////////////////////////////// + // DSP + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_a; + adc_a_reg2 <= adc_a_reg1; + adc_b_reg1 <= adc_b; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg1 <= adc_ovf_a; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg1 <= adc_ovf_b; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done), + .rx_ready_i(wr1_ready),.rx_full_i(wr1_full), + .overrun() ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done), + .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty), + .underrun() ); + + assign dsp_rst = wb_rst; + + ///////////////////////////////////////////////////////////////////////////////////// + // SERDES + serdes_tx serdes_tx + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done), + .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty) + ); + + serdes_rx serdes_rx + (.clk(dsp_clk),.rst(dsp_rst), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done) + ); + + // Debug Pins + wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst}, + {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached}, + {8'hAF}, + {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}}; + + wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst}, + {iram_rd_adr[15:8]}, + {iram_rd_adr[7:0]}, + {serdes_outs}}; + + assign io_rx = ser_debug[31:16]; + assign io_tx = ser_debug[15:0]; + + assign debug = debug_wb; + + assign debug_clk[0] = wb_clk; + assign debug_clk[1] = dsp_clk; + +endmodule // eth_test + + +// Local Variables: +// verilog-library-directories:("." "subdir" "subdir2") +// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v") +// verilog-library-extensions:(".v" ".h") +// End: diff --git a/fpga/usrp2/top/eth_test/eth_tb.v b/fpga/usrp2/top/eth_test/eth_tb.v new file mode 100644 index 000000000..451ce1e7e --- /dev/null +++ b/fpga/usrp2/top/eth_test/eth_tb.v @@ -0,0 +1,257 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +// Nearly everything is an input + +module eth_tb(); + // Misc, debug + wire led1; + wire led2; + wire [31:0] debug; + wire [1:0] debug_clk; + + // Expansion + wire exp_pps_in; + wire exp_pps_out; + + // GMII + // GMII-CTRL + wire GMII_COL; + wire GMII_CRS; + + // GMII-TX + wire [7:0] GMII_TXD; + wire GMII_TX_EN; + wire GMII_TX_ER; + wire GMII_GTX_CLK; + wire GMII_TX_CLK; // 100mbps clk + + // GMII-RX + wire [7:0] GMII_RXD; + wire GMII_RX_CLK; + wire GMII_RX_DV; + wire GMII_RX_ER; + + // GMII-Management + wire MDIO; + wire MDC; + wire PHY_INTn; // open drain + wire PHY_RESETn; + wire PHY_CLK; // possibly use on-board osc + + // RAM + wire [17:0] RAM_D; + wire [18:0] RAM_A; + wire RAM_CE1n; + wire RAM_CENn; + wire RAM_CLK; + wire RAM_WEn; + wire RAM_OEn; + wire RAM_LDn; + + // SERDES + wire ser_enable; + wire ser_prbsen; + wire ser_loopen; + wire ser_rx_en; + + wire ser_tx_clk; + wire [15:0] ser_t; + wire ser_tklsb; + wire ser_tkmsb; + + wire ser_rx_clk; + wire [15:0] ser_r; + wire ser_rklsb; + wire ser_rkmsb; + + // CPLD interface + wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; + + // ADC + wire [13:0] adc_a; + wire adc_ovf_a; + wire adc_oen_a; + wire adc_pdn_a; + + wire [13:0] adc_b; + wire adc_ovf_b; + wire adc_oen_b; + wire adc_pdn_b; + + // DAC + wire [15:0] dac_a; + wire [15:0] dac_b; + + // I2C + wire SCL; + wire SDA; + + // Clock Gen Control + wire [1:0] clk_en; + wire [1:0] clk_sel; + wire clk_func; // FIXME is an input to control the 9510 + wire clk_status; + + // Clocks + reg clk_fpga; + wire clk_to_mac; + wire pps_in; + + // Generic SPI + wire sclk, mosi, miso; + wire sen_clk; + wire sen_dac; + wire sen_tx_db; + wire sen_tx_adc; + wire sen_tx_dac; + wire sen_rx_db; + wire sen_rx_adc; + wire sen_rx_dac; + + // GPIO to DBoards + wire [15:0] io_tx; + wire [15:0] io_rx; + + wire wb_clk, wb_rst; + wire start, clock_ready; + + reg aux_clk; + + initial aux_clk= 1'b0; + always #25 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #7 clk_fpga = ~clk_fpga; + + + wire div_clk; + reg [2:0] div_ctr = 0; + + always @(posedge clk_fpga or negedge clk_fpga) + if(div_ctr==5) + div_ctr = 0; + else + div_ctr = div_ctr + 1; + assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2); + + assign dsp_clk = clk_fpga; + assign wb_clk = clock_ready ? div_clk : aux_clk; + + initial + $monitor($time, ,clock_ready); + + initial begin + $dumpfile("eth_tb.vcd"); + $dumpvars(0,eth_tb); + end + + initial #10000000 $finish; + + cpld_model + cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), + .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); + + eth_sim_top eth_sim_top(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .led1 (led1), + .led2 (led2), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD[7:0]), + .GMII_TX_EN (GMII_TX_EN), + .GMII_TX_ER (GMII_TX_ER), + .GMII_GTX_CLK (GMII_GTX_CLK), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk), + .ser_t (ser_t[15:0]), + .ser_tklsb (ser_tklsb), + .ser_tkmsb (ser_tkmsb), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r[15:0]), + .ser_rklsb (ser_rklsb), + .ser_rkmsb (ser_rkmsb), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_oen_a (adc_oen_a), + .adc_pdn_a (adc_pdn_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_oen_b (adc_oen_b), + .adc_pdn_b (adc_pdn_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0])); + + // Experimental printf-like function + always @(posedge wb_clk) + begin + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000)) + $write("%x",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100)) + $display("%x",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004)) + $write("%c",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104)) + $display("%c",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008)) + $display(""); + end + + +endmodule // u2_sim_top + +// Local Variables: +// verilog-library-directories:("." "subdir" "subdir2") +// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v") +// verilog-library-extensions:(".v" ".h") +// End: diff --git a/fpga/usrp2/top/python/check_inout.py b/fpga/usrp2/top/python/check_inout.py new file mode 100755 index 000000000..ff371d378 --- /dev/null +++ b/fpga/usrp2/top/python/check_inout.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Description: +# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. +# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes + +import sys +import re + +if __name__=='__main__': + if len(sys.argv) == 2: + print "Usage: %s <top level Verilog file> <pin definition UCF>" + sys.exit(-1) + + verilog_filename = sys.argv[1] + ucf_filename = sys.argv[2] + + verilog_file = open(verilog_filename, 'r') + ucf_file = open(ucf_filename, 'r') + + verilog_iolist = list() + ucf_iolist = list() + + #read in all input, inout, and output declarations and compile a list + for line in verilog_file: + for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]): + verilog_iolist.append(match) + + for line in ucf_file: + m = re.search(r"""NET "(\w+).*" """, line.split("#")[0]) + if m is not None: + ucf_iolist.append(m.group(1)) + + #now find corresponding matches and error when you don't find one + #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem + err = False + + for item in verilog_iolist: + if item not in ucf_iolist: + print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item + err = True + + if err: + sys.exit(-1) + + print "No errors found." + sys.exit(0) diff --git a/fpga/usrp2/top/safe_u2plus/.gitignore b/fpga/usrp2/top/safe_u2plus/.gitignore new file mode 100644 index 000000000..a96f0be92 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/.gitignore @@ -0,0 +1,2 @@ +build* +*impact* diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile new file mode 100644 index 000000000..62a02ff40 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/Makefile @@ -0,0 +1,246 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u2plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2plus/capture_ddrlvds.v \ +top/safe_u2plus/u2plus.ucf \ +top/safe_u2plus/safe_u2plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v new file mode 100644 index 000000000..dca9688c5 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v @@ -0,0 +1,23 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [5:1] leds, // LED4 is shared w/INIT_B + output ETH_LED + ); + + wire clk_fpga; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + +endmodule // safe_u2plus diff --git a/fpga/usrp2/top/safe_u2plus/u2plus.ucf b/fpga/usrp2/top/safe_u2plus/u2plus.ucf new file mode 100755 index 000000000..0a9460d86 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/u2plus.ucf @@ -0,0 +1,401 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +#NET "ADC_clkout_p" LOC = "P1" ; +#NET "ADC_clkout_n" LOC = "P2" ; +#NET "ADCA_12_p" LOC = "Y1" ; +#NET "ADCA_12_n" LOC = "Y2" ; +#NET "ADCA_10_p" LOC = "W3" ; +#NET "ADCA_10_n" LOC = "W4" ; +#NET "ADCA_8_p" LOC = "T7" ; +#NET "ADCA_8_n" LOC = "U6" ; +#NET "ADCA_6_p" LOC = "U5" ; +#NET "ADCA_6_n" LOC = "V5" ; +#NET "ADCA_4_p" LOC = "T10" ; +#NET "ADCA_4_n" LOC = "T9" ; +#NET "ADCA_2_p" LOC = "V1" ; +#NET "ADCA_2_n" LOC = "V2" ; +#NET "ADCA_0_p" LOC = "R8" ; +#NET "ADCA_0_n" LOC = "R7" ; +#NET "ADCB_2_p" LOC = "U7" ; +#NET "ADCB_2_n" LOC = "U8" ; +#NET "ADCB_0_p" LOC = "AA2" ; +#NET "ADCB_0_n" LOC = "AA3" ; +#NET "ADCB_4_p" LOC = "AE1" ; +#NET "ADCB_4_n" LOC = "AE2" ; +#NET "ADCB_6_p" LOC = "W1" ; +#NET "ADCB_6_n" LOC = "W2" ; +#NET "ADCB_8_p" LOC = "U3" ; +#NET "ADCB_8_n" LOC = "V4" ; +#NET "ADCB_10_p" LOC = "J1" ; +#NET "ADCB_10_n" LOC = "K1" ; +#NET "ADCB_12_p" LOC = "J3" ; +#NET "ADCB_12_n" LOC = "J2" ; + +## DAC +#NET "DAC_LOCK" LOC = "P4" ; +#NET "DACA<0>" LOC = "P8" ; +#NET "DACA<1>" LOC = "P9" ; +#NET "DACA<2>" LOC = "R5" ; +#NET "DACA<3>" LOC = "R6" ; +#NET "DACA<4>" LOC = "P7" ; +#NET "DACA<5>" LOC = "P6" ; +#NET "DACA<6>" LOC = "T3" ; +#NET "DACA<7>" LOC = "T4" ; +#NET "DACA<8>" LOC = "R3" ; +#NET "DACA<9>" LOC = "R4" ; +#NET "DACA<10>" LOC = "R2" ; +#NET "DACA<11>" LOC = "N1" ; +#NET "DACA<12>" LOC = "N2" ; +#NET "DACA<13>" LOC = "N5" ; +#NET "DACA<14>" LOC = "N4" ; +#NET "DACA<15>" LOC = "M2" ; +#NET "DACB<0>" LOC = "M5" ; +#NET "DACB<1>" LOC = "M6" ; +#NET "DACB<2>" LOC = "M4" ; +#NET "DACB<3>" LOC = "M3" ; +#NET "DACB<4>" LOC = "M8" ; +#NET "DACB<5>" LOC = "M7" ; +#NET "DACB<6>" LOC = "L4" ; +#NET "DACB<7>" LOC = "L3" ; +#NET "DACB<8>" LOC = "K3" ; +#NET "DACB<9>" LOC = "K2" ; +#NET "DACB<10>" LOC = "K5" ; +#NET "DACB<11>" LOC = "K4" ; +#NET "DACB<12>" LOC = "M10" ; +#NET "DACB<13>" LOC = "M9" ; +#NET "DACB<14>" LOC = "J5" ; +#NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +#NET "io_tx<15>" LOC = "K6" ; +#NET "io_tx<14>" LOC = "L7" ; +#NET "io_tx<13>" LOC = "H2" ; +#NET "io_tx<12>" LOC = "H1" ; +#NET "io_tx<11>" LOC = "L10" ; +#NET "io_tx<10>" LOC = "L9" ; +#NET "io_tx<9>" LOC = "G3" ; +#NET "io_tx<8>" LOC = "F3" ; +#NET "io_tx<7>" LOC = "K7" ; +#NET "io_tx<6>" LOC = "J6" ; +#NET "io_tx<5>" LOC = "E1" ; +#NET "io_tx<4>" LOC = "F2" ; +#NET "io_tx<3>" LOC = "J7" ; +#NET "io_tx<2>" LOC = "H6" ; +#NET "io_tx<1>" LOC = "F5" ; +#NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +#NET "io_rx<15>" LOC = "AD1" ; +#NET "io_rx<14>" LOC = "AD2" ; +#NET "io_rx<13>" LOC = "AC2" ; +#NET "io_rx<12>" LOC = "AC3" ; +#NET "io_rx<11>" LOC = "W7" ; +#NET "io_rx<10>" LOC = "W6" ; +#NET "io_rx<9>" LOC = "U9" ; +#NET "io_rx<8>" LOC = "V8" ; +#NET "io_rx<7>" LOC = "AB1" ; +#NET "io_rx<6>" LOC = "AC1" ; +#NET "io_rx<5>" LOC = "V7" ; +#NET "io_rx<4>" LOC = "V6" ; +#NET "io_rx<3>" LOC = "Y5" ; +#NET "io_rx<2>" LOC = "R10" ; +#NET "io_rx<1>" LOC = "R1" ; +#NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +#NET "FPGA_RESET" LOC = "K24" ; + +## Debug +#NET "debug_clk<0>" LOC = "AA10" ; +#NET "debug_clk<1>" LOC = "AD11" ; +#NET "debug<0>" LOC = "AC19" ; +#NET "debug<1>" LOC = "AF20" ; +#NET "debug<2>" LOC = "AE20" ; +#NET "debug<3>" LOC = "AC16" ; +#NET "debug<4>" LOC = "AB16" ; +#NET "debug<5>" LOC = "AF19" ; +#NET "debug<6>" LOC = "AE19" ; +#NET "debug<7>" LOC = "V15" ; +#NET "debug<8>" LOC = "U15" ; +#NET "debug<9>" LOC = "AE17" ; +#NET "debug<10>" LOC = "AD17" ; +#NET "debug<11>" LOC = "V14" ; +#NET "debug<12>" LOC = "W15" ; +#NET "debug<13>" LOC = "AC15" ; +#NET "debug<14>" LOC = "AD14" ; +#NET "debug<15>" LOC = "AC14" ; +#NET "debug<16>" LOC = "AC11" ; +#NET "debug<17>" LOC = "AB12" ; +#NET "debug<18>" LOC = "AC12" ; +#NET "debug<19>" LOC = "V13" ; +#NET "debug<20>" LOC = "W13" ; +#NET "debug<21>" LOC = "AE8" ; +#NET "debug<22>" LOC = "AF8" ; +#NET "debug<23>" LOC = "V12" ; +#NET "debug<24>" LOC = "W12" ; +#NET "debug<25>" LOC = "AB9" ; +#NET "debug<26>" LOC = "AC9" ; +#NET "debug<27>" LOC = "AC8" ; +#NET "debug<28>" LOC = "AB7" ; +#NET "debug<29>" LOC = "V11" ; +#NET "debug<30>" LOC = "U11" ; +#NET "debug<31>" LOC = "Y10" ; + +## UARTS +#NET "TXD<3>" LOC = "AD20" ; +#NET "TXD<2>" LOC = "AC20" ; +#NET "TXD<1>" LOC = "AD19" ; +#NET "RXD<3>" LOC = "AF17" ; +#NET "RXD<2>" LOC = "AF15" ; +#NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +#NET "CLK_STATUS" LOC = "AD22" ; +#NET "CLK_FUNC" LOC = "AC21" ; +#NET "clk_sel<0>" LOC = "AE21" ; +#NET "clk_sel<1>" LOC = "AD21" ; +#NET "clk_en<1>" LOC = "AA17" ; +#NET "clk_en<0>" LOC = "Y17" ; + +## I2C +#NET "SDA" LOC = "V16" ; +#NET "SCL" LOC = "U16" ; + +## Timing +#NET "PPS_IN" LOC = "AB6" ; +#NET "PPS2_IN" LOC = "AA20" ; + +## SPI +#NET "SEN_CLK" LOC = "AA18" ; +#NET "MOSI_CLK" LOC = "W17" ; +#NET "SCLK_CLK" LOC = "V17" ; +#NET "MISO_CLK" LOC = "AC10" ; + +#NET "SEN_DAC" LOC = "AE7" ; +#NET "SCLK_DAC" LOC = "AF5" ; +#NET "MOSI_DAC" LOC = "AE6" ; +#NET "MISO_DAC" LOC = "Y3" ; + +#NET "SCLK_ADC" LOC = "B1" ; +#NET "MOSI_ADC" LOC = "J8" ; +#NET "SEN_ADC" LOC = "J9" ; + +#NET "MOSI_TX_ADC" LOC = "V10" ; +#NET "SEN_TX_ADC" LOC = "W10" ; +#NET "SCLK_TX_ADC" LOC = "AC6" ; +#NET "MISO_TX_ADC" LOC = "G1" ; + +#NET "MOSI_TX_DAC" LOC = "AD6" ; +#NET "SEN_TX_DAC" LOC = "AE4" ; +#NET "SCLK_TX_DAC" LOC = "AF4" ; + +#NET "SCLK_TX_DB" LOC = "AE3" ; +#NET "MOSI_TX_DB" LOC = "AF3" ; +#NET "SEN_TX_DB" LOC = "W9" ; +#NET "MISO_TX_DB" LOC = "AA5" ; + +#NET "MOSI_RX_ADC" LOC = "E3" ; +#NET "SCLK_RX_ADC" LOC = "F4" ; +#NET "SEN_RX_ADC" LOC = "D3" ; +#NET "MISO_RX_ADC" LOC = "C1" ; + +#NET "SCLK_RX_DAC" LOC = "E4" ; +#NET "SEN_RX_DAC" LOC = "K9" ; +#NET "MOSI_RX_DAC" LOC = "K8" ; + +#NET "SCLK_RX_DB" LOC = "G6" ; +#NET "MOSI_RX_DB" LOC = "H7" ; +#NET "SEN_RX_DB" LOC = "B2" ; +#NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +#NET "CLK_TO_MAC" LOC = "P26" ; + +#NET "GMII_TXD<7>" LOC = "G21" ; +#NET "GMII_TXD<6>" LOC = "C26" ; +#NET "GMII_TXD<5>" LOC = "C25" ; +#NET "GMII_TXD<4>" LOC = "J21" ; +#NET "GMII_TXD<3>" LOC = "H21" ; +#NET "GMII_TXD<2>" LOC = "D25" ; +#NET "GMII_TXD<1>" LOC = "D24" ; +#NET "GMII_TXD<0>" LOC = "E26" ; +#NET "GMII_TX_EN" LOC = "D26" ; +#NET "GMII_TX_ER" LOC = "J19" ; +#NET "GMII_GTX_CLK" LOC = "J20" ; +#NET "GMII_TX_CLK" LOC = "P25" ; + +#NET "GMII_RX_CLK" LOC = "P21" ; +#NET "GMII_RXD<7>" LOC = "G22" ; +#NET "GMII_RXD<6>" LOC = "K19" ; +#NET "GMII_RXD<5>" LOC = "K18" ; +#NET "GMII_RXD<4>" LOC = "E24" ; +#NET "GMII_RXD<3>" LOC = "F23" ; +#NET "GMII_RXD<2>" LOC = "L18" ; +#NET "GMII_RXD<1>" LOC = "L17" ; +#NET "GMII_RXD<0>" LOC = "F25" ; +#NET "GMII_RX_DV" LOC = "F24" ; +#NET "GMII_RX_ER" LOC = "L20" ; +#NET "GMII_CRS" LOC = "K20" ; +#NET "GMII_COL" LOC = "G23" ; + +#NET "PHY_INTn" LOC = "L22" ; +#NET "MDIO" LOC = "K21" ; +#NET "MDC" LOC = "J23" ; +#NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" ; + +## MIMO Interface +#NET "exp_time_out_p" LOC = "Y14" ; +#NET "exp_time_out_n" LOC = "AA14" ; +#NET "exp_time_in_p" LOC = "N18" ; +#NET "exp_time_in_n" LOC = "N17" ; +#NET "exp_user_out_p" LOC = "AF14" ; +#NET "exp_user_out_n" LOC = "AE14" ; +#NET "exp_user_in_p" LOC = "L24" ; +#NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +#NET "ser_enable" LOC = "R20" ; +#NET "ser_prbsen" LOC = "U23" ; +#NET "ser_loopen" LOC = "R19" ; +#NET "ser_rx_en" LOC = "Y21" ; +#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +#NET "ser_t<15>" LOC = "V23" ; +#NET "ser_t<14>" LOC = "U22" ; +#NET "ser_t<13>" LOC = "V24" ; +#NET "ser_t<12>" LOC = "V25" ; +#NET "ser_t<11>" LOC = "W23" ; +#NET "ser_t<10>" LOC = "V22" ; +#NET "ser_t<9>" LOC = "T18" ; +#NET "ser_t<8>" LOC = "T17" ; +#NET "ser_t<7>" LOC = "Y24" ; +#NET "ser_t<6>" LOC = "Y25" ; +#NET "ser_t<5>" LOC = "U21" ; +#NET "ser_t<4>" LOC = "T20" ; +#NET "ser_t<3>" LOC = "Y22" ; +#NET "ser_t<2>" LOC = "Y23" ; +#NET "ser_t<1>" LOC = "U19" ; +#NET "ser_t<0>" LOC = "U18" ; +#NET "ser_tkmsb" LOC = "AA24" ; +#NET "ser_tklsb" LOC = "AA25" ; +#NET "ser_rx_clk" LOC = "P18" ; +#NET "ser_r<15>" LOC = "V21" ; +#NET "ser_r<14>" LOC = "U20" ; +#NET "ser_r<13>" LOC = "AA22" ; +#NET "ser_r<12>" LOC = "AA23" ; +#NET "ser_r<11>" LOC = "V18" ; +#NET "ser_r<10>" LOC = "V19" ; +#NET "ser_r<9>" LOC = "AB23" ; +#NET "ser_r<8>" LOC = "AC26" ; +#NET "ser_r<7>" LOC = "AB26" ; +#NET "ser_r<6>" LOC = "AD26" ; +#NET "ser_r<5>" LOC = "AC25" ; +#NET "ser_r<4>" LOC = "W20" ; +#NET "ser_r<3>" LOC = "W21" ; +#NET "ser_r<2>" LOC = "AC23" ; +#NET "ser_r<1>" LOC = "AC24" ; +#NET "ser_r<0>" LOC = "AE26" ; +#NET "ser_rkmsb" LOC = "AD25" ; +#NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +#NET "RAM_D<35>" LOC = "K16" ; +#NET "RAM_D<34>" LOC = "D20" ; +#NET "RAM_D<33>" LOC = "C20" ; +#NET "RAM_D<32>" LOC = "E21" ; +#NET "RAM_D<31>" LOC = "D21" ; +#NET "RAM_D<30>" LOC = "C21" ; +#NET "RAM_D<29>" LOC = "B21" ; +#NET "RAM_D<28>" LOC = "H17" ; +#NET "RAM_D<27>" LOC = "G17" ; +#NET "RAM_D<26>" LOC = "B23" ; +#NET "RAM_D<25>" LOC = "A22" ; +#NET "RAM_D<24>" LOC = "D23" ; +#NET "RAM_D<23>" LOC = "C23" ; +#NET "RAM_D<22>" LOC = "D22" ; +#NET "RAM_D<21>" LOC = "C22" ; +#NET "RAM_D<20>" LOC = "F19" ; +#NET "RAM_D<19>" LOC = "G20" ; +#NET "RAM_D<18>" LOC = "F20" ; +#NET "RAM_D<17>" LOC = "F7" ; +#NET "RAM_D<16>" LOC = "E7" ; +#NET "RAM_D<15>" LOC = "G9" ; +#NET "RAM_D<14>" LOC = "H9" ; +#NET "RAM_D<13>" LOC = "G10" ; +#NET "RAM_D<12>" LOC = "H10" ; +#NET "RAM_D<11>" LOC = "A4" ; +#NET "RAM_D<10>" LOC = "B4" ; +#NET "RAM_D<9>" LOC = "C5" ; +#NET "RAM_D<8>" LOC = "D6" ; +#NET "RAM_D<7>" LOC = "J11" ; +#NET "RAM_D<6>" LOC = "K11" ; +#NET "RAM_D<5>" LOC = "B7" ; +#NET "RAM_D<4>" LOC = "C7" ; +#NET "RAM_D<3>" LOC = "B6" ; +#NET "RAM_D<2>" LOC = "C6" ; +#NET "RAM_D<1>" LOC = "C8" ; +#NET "RAM_D<0>" LOC = "D8" ; +#NET "RAM_A<0>" LOC = "C11" ; +#NET "RAM_A<1>" LOC = "E12" ; +#NET "RAM_A<2>" LOC = "F12" ; +#NET "RAM_A<3>" LOC = "D13" ; +#NET "RAM_A<4>" LOC = "C12" ; +#NET "RAM_A<5>" LOC = "A12" ; +#NET "RAM_A<6>" LOC = "B12" ; +#NET "RAM_A<7>" LOC = "E14" ; +#NET "RAM_A<8>" LOC = "F14" ; +#NET "RAM_A<9>" LOC = "B15" ; +#NET "RAM_A<10>" LOC = "A15" ; +#NET "RAM_A<11>" LOC = "D16" ; +#NET "RAM_A<12>" LOC = "C15" ; +#NET "RAM_A<13>" LOC = "D17" ; +#NET "RAM_A<14>" LOC = "C16" ; +#NET "RAM_A<15>" LOC = "F15" ; +#NET "RAM_A<16>" LOC = "C17" ; +#NET "RAM_A<17>" LOC = "B17" ; +#NET "RAM_A<18>" LOC = "B18" ; +#NET "RAM_A<19>" LOC = "A18" ; +#NET "RAM_A<20>" LOC = "D18" ; +#NET "RAM_BWn<3>" LOC = "D9" ; +#NET "RAM_BWn<2>" LOC = "A9" ; +#NET "RAM_BWn<1>" LOC = "B9" ; +#NET "RAM_BWn<0>" LOC = "G12" ; +#NET "RAM_ZZ" LOC = "J12" ; +#NET "RAM_LDn" LOC = "H12" ; +#NET "RAM_OEn" LOC = "C10" ; +#NET "RAM_WEn" LOC = "D10" ; +#NET "RAM_CENn" LOC = "B10" ; +#NET "RAM_CLK" LOC = "A10" ; + +## SPI Flash +#NET "flash_miso" LOC = "AF24" ; +#NET "flash_clk" LOC = "AE24" ; +#NET "flash_mosi" LOC = "AB15" ; +#NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +##NET "PROG_B" LOC = "A2" ; +##NET "PUDC_B" LOC = "G8" ; +##NET "DONE" LOC = "AB21" ; +##NET "INIT_B" LOC = "AA15" ; + + +##NET "unnamed_net19" LOC = "AE9" ; # VS1 +##NET "unnamed_net18" LOC = "AF9" ; # VS0 +##NET "unnamed_net17" LOC = "AA12" ; # VS2 +##NET "unnamed_net16" LOC = "Y7" ; # M2 +##NET "unnamed_net15" LOC = "AC4" ; # M1 +##NET "unnamed_net14" LOC = "AD4" ; # M0 +##NET "unnamed_net13" LOC = "D4" ; # TMS +##NET "unnamed_net12" LOC = "E23" ; # TDO +##NET "unnamed_net11" LOC = "G7" ; # TDI +##NET "unnamed_net10" LOC = "A25" ; # TCK +##NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/fpga/usrp2/top/single_u2_sim/single_u2_sim.v b/fpga/usrp2/top/single_u2_sim/single_u2_sim.v new file mode 100644 index 000000000..2a7b24849 --- /dev/null +++ b/fpga/usrp2/top/single_u2_sim/single_u2_sim.v @@ -0,0 +1,324 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module single_u2_sim(); + // Misc, debug + wire [7:0] leds; + wire [31:0] debug; + wire [1:0] debug_clk; + + // Expansion + wire exp_pps_in; + wire exp_pps_out; + + // GMII + // GMII-CTRL + wire GMII_COL; + wire GMII_CRS; + + // GMII-TX + wire [7:0] GMII_TXD; + wire GMII_TX_EN; + wire GMII_TX_ER; + wire GMII_GTX_CLK; + wire GMII_TX_CLK; // 100mbps clk + + // GMII-RX + wire [7:0] GMII_RXD; + wire GMII_RX_CLK; + wire GMII_RX_DV; + wire GMII_RX_ER; + + // GMII-Management + wire MDIO; + wire MDC; + wire PHY_INTn; // open drain + wire PHY_RESETn; + wire PHY_CLK; // possibly use on-board osc + + // RAM + wire [17:0] RAM_D; + wire [18:0] RAM_A; + wire RAM_CE1n; + wire RAM_CENn; + wire RAM_CLK; + wire RAM_WEn; + wire RAM_OEn; + wire RAM_LDn; + + // SERDES + wire ser_enable; + wire ser_prbsen; + wire ser_loopen; + wire ser_rx_en; + + wire ser_tx_clk; + wire [15:0] ser_t; + wire ser_tklsb; + wire ser_tkmsb; + + wire ser_rx_clk; + wire [15:0] ser_r; + wire ser_rklsb; + wire ser_rkmsb; + + // CPLD interface + wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; + + // ADC + wire [13:0] adc_a; + wire adc_ovf_a; + wire adc_on_a, adc_oe_a; + + wire [13:0] adc_b; + wire adc_ovf_b; + wire adc_on_b, adc_oe_b; + + // DAC + wire [15:0] dac_a; + wire [15:0] dac_b; + + // I2C + wire SCL; + wire SDA; + + // Clock Gen Control + wire [1:0] clk_en; + wire [1:0] clk_sel; + wire clk_func; // FIXME is an input to control the 9510 + wire clk_status; + + // Clocks + reg clk_fpga; + reg clk_to_mac; + wire pps_in; + + // Generic SPI + wire sclk, mosi, miso; + wire sen_clk; + wire sen_dac; + wire sen_tx_db; + wire sen_tx_adc; + wire sen_tx_dac; + wire sen_rx_db; + wire sen_rx_adc; + wire sen_rx_dac; + + // GPIO to DBoards + wire [15:0] io_tx; + wire [15:0] io_rx; + + wire wb_clk; + wire start, clock_ready; + + reg aux_clk; + + initial aux_clk= 1'b0; + always #6 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #5 clk_fpga = ~clk_fpga; + + initial clk_to_mac = 0; + always #4 clk_to_mac = ~clk_to_mac; + + wire div_clk, dsp_clk; + reg [7:0] div_ctr = 0; + + assign dsp_clk = clock_ready ? clk_fpga : aux_clk; + assign wb_clk = div_clk; + +`define CLK_DIV_2 1 +//`define CLK_DIV_3 + +`ifdef CLK_DIV_2 + localparam clock_divider = 4'd2; + always @(posedge dsp_clk) + div_ctr <= div_ctr + 1; + assign div_clk = div_ctr[0]; +`endif + +`ifdef CLK_DIV_3 + localparam clock_divider = 2; + always @(posedge dsp_clk or negedge dsp_clk) + if(div_ctr == 5) + div_ctr <= 0; + else + div_ctr <= div_ctr + 1; + assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); +`endif + + initial + $monitor($time, ,clock_ready); + + always #1000000 $monitor("Time in ns ",$time); + + initial begin + @(negedge cpld_done); + @(posedge cpld_done); + $dumpfile("single_u2_sim.lxt"); + $dumpvars(0,single_u2_sim); + end + + initial #10000000 $finish; + + cpld_model + cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), + .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); + + serdes_model serdes_model + (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), + .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), + .even(0),.error(0) ); + + adc_model adc_model + (.clk(dsp_clk),.rst(0), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); + + wire [2:0] speed; + phy_sim phy_model + (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), + .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), + .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), + .Crs(GMII_CRS), .Col(GMII_COL), + .Speed(speed), .Done(0) ); + pullup p3(MDIO); + + miim_model miim_model + (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), + .phy_intn_o(PHY_INTn),.speed_o(speed) ); + + xlnx_glbl glbl (.GSR(),.GTS()); + + wire RAM_MODE = 1'b0; + cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), + .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), + .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), + .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); + + M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), + .SDA(SDA),.SCL(SCL),.RESET(0)); + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o; + wire sda_pad_i, sda_pad_o, sda_pad_oen_o; + + pullup p1(SCL); + pullup p2(SDA); + + assign scl_pad_i = SCL; + assign sda_pad_i = SDA; + + assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; + assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; + + // printf output + wire uart_baud_o, uart_tx_o, uart_rx_i; + assign uart_rx_i = 1'b1; + + uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); + + // End the simulation + always @(posedge wb_clk) + if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) + begin + $display($time, "Finish called.",); + $finish; + end + + u2_core #(.RAM_SIZE(32768)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD[7:0]), + .GMII_TX_EN (GMII_TX_EN), + .GMII_TX_ER (GMII_TX_ER), + .GMII_GTX_CLK (GMII_GTX_CLK), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk), + .ser_t (ser_t[15:0]), + .ser_tklsb (ser_tklsb), + .ser_tkmsb (ser_tkmsb), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r[15:0]), + .ser_rklsb (ser_rklsb), + .ser_rkmsb (ser_rkmsb), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_init_b (1), + .por (0), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (uart_baud_o), + .sim_mode (1'b1), + .clock_divider (clock_divider) + ); + +endmodule // single_u2_sim diff --git a/fpga/usrp2/top/tcl/ise_helper.tcl b/fpga/usrp2/top/tcl/ise_helper.tcl new file mode 100644 index 000000000..a4bee76b8 --- /dev/null +++ b/fpga/usrp2/top/tcl/ise_helper.tcl @@ -0,0 +1,88 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +proc set_props {process options} { + if ![string compare $options ""] { + return + } + set state 1 + foreach opt $options { + if $state { + set key $opt + set state 0 + } else { + puts ">>> Setting: $process\[$key\] = $opt" + if ![string compare $process "Project"] { + project set $key $opt + } else { + project set $key $opt -process $process + } + set state 1 + } + } +} + +if [file isfile $env(ISE_FILE)] { + puts ">>> Opening project: $env(ISE_FILE)" + project open $env(ISE_FILE) +} else { + puts ">>> Creating project: $env(ISE_FILE)" + project new $env(ISE_FILE) + + ################################################## + # Set the project properties + ################################################## + set_props "Project" $env(PROJECT_PROPERTIES) + + ################################################## + # Add the sources + ################################################## + foreach source $env(SOURCES) { + puts ">>> Adding source to project: $source" + xfile add $source + } + + ################################################## + # Set the top level module + ################################################## + project set top $env(TOP_MODULE) + + ################################################## + # Set the process properties + ################################################## + set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES) + set_props "Translate" $env(TRANSLATE_PROPERTIES) + set_props "Map" $env(MAP_PROPERTIES) + set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES) + set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES) + set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES) + set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) +} + +if [string compare [lindex $argv 0] ""] { + puts ">>> Running Process: [lindex $argv 0]" + process run [lindex $argv 0] +} + +project close +exit + + diff --git a/fpga/usrp2/top/u1e/.gitignore b/fpga/usrp2/top/u1e/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/fpga/usrp2/top/u1e/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/u1e/Makefile new file mode 100644 index 000000000..3cb9fd8f3 --- /dev/null +++ b/fpga/usrp2/top/u1e/Makefile @@ -0,0 +1,101 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e_core.v \ +u1e.v \ +u1e.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e/README b/fpga/usrp2/top/u1e/README new file mode 100644 index 000000000..14c7a4955 --- /dev/null +++ b/fpga/usrp2/top/u1e/README @@ -0,0 +1,4 @@ + +make clean +make sim +./tb_u1e -lxt2 diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/u1e/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + diff --git a/fpga/usrp2/top/u1e/make.sim b/fpga/usrp2/top/u1e/make.sim new file mode 100644 index 000000000..1c163884c --- /dev/null +++ b/fpga/usrp2/top/u1e/make.sim @@ -0,0 +1,7 @@ +all: sim + +sim: + iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e + +clean: + rm -f tb_u1e *.vcd *.lxt a.out diff --git a/fpga/usrp2/top/u1e/tb_u1e.v b/fpga/usrp2/top/u1e/tb_u1e.v new file mode 100644 index 000000000..5fc8134fb --- /dev/null +++ b/fpga/usrp2/top/u1e/tb_u1e.v @@ -0,0 +1,41 @@ +`timescale 1ps / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + xlnx_glbl glbl (.GSR(),.GTS()); + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0, rst_fpga = 1; + always #15625 clk_fpga = ~clk_fpga; + + initial #200000 + @(posedge clk_fpga) + rst_fpga <= 0; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model_async gpmc_model_async + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // tb_u1e diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/fpga/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/fpga/usrp2/top/u1e/u1e.ucf b/fpga/usrp2/top/u1e/u1e.ucf new file mode 100644 index 000000000..0c487a601 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e.ucf @@ -0,0 +1,259 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; + +## FTDI UART to USB converter +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; + +#NET "SYSEN" LOC = "C11" ; + +## I2C +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; + +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; + +### Clock Gen SPI +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; + +## Clock gen control +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; + +#NET "reset_codec" LOC = "C2" ; + +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; + +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; + +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; + +NET "PPS_IN" LOC = "M5" ; + +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; + +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; + +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/fpga/usrp2/top/u1e/u1e.v b/fpga/usrp2/top/u1e/u1e.v new file mode 100644 index 000000000..445b14a03 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e.v @@ -0,0 +1,141 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO + input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + + input PPS_IN + ); + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + wire clk_2x, dcm_rst, dcm_locked, clk_fb; + DCM #(.CLK_FEEDBACK ( "1X" ), + .CLKDV_DIVIDE ( 2 ), + .CLKFX_DIVIDE ( 2 ), + .CLKFX_MULTIPLY ( 2 ), + .CLKIN_DIVIDE_BY_2 ( "FALSE" ), + .CLKIN_PERIOD ( 15.625 ), + .CLKOUT_PHASE_SHIFT ( "NONE" ), + .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), + .DFS_FREQUENCY_MODE ( "LOW" ), + .DLL_FREQUENCY_MODE ( "LOW" ), + .DUTY_CYCLE_CORRECTION ( "TRUE" ), + .FACTORY_JF ( 16'h8080 ), + .PHASE_SHIFT ( 0 ), + .STARTUP_WAIT ( "FALSE" )) + clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), + .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), + .CLKDV(), .CLKFX(), .CLKFX180(), + .CLK2X(), .CLK2X180(), + .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), + .LOCKED(dcm_locked), .STATUS()); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(delay_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), + .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), + .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, + {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, + {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), + .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Local Debug + // assign debug_clk = {clk_fpga, clk_2x }; + // assign debug = { TXSYNC, TXBLANK, TX }; + +endmodule // u1e diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v new file mode 100644 index 000000000..e7e798b34 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -0,0 +1,459 @@ + + +//`define LOOPBACK 1 +//`define TIMED 1 +`define DSP 1 + +module u1e_core + (input clk_fpga, input rst_fpga, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + + input [11:0] misc_gpio, input pps_in + ); + + localparam TXFIFOSIZE = 13; + localparam RXFIFOSIZE = 13; + + localparam SR_RX_DSP = 0; // 5 regs + localparam SR_CLEAR_FIFO = 6; // 1 reg + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_TIME64 = 28; // 4 regs + + wire [7:0] COMPAT_NUM = 8'd2; + + wire wb_clk = clk_fpga; + wire wb_rst = rst_fpga; + + wire pps_int; + wire [63:0] vita_time; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire [31:0] debug_vt; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; + wire [7:0] rate; + + wire bus_error; + + wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; + + setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); + assign clear_tx = clear_tx_int & do_clear; + assign clear_rx = clear_rx_int & do_clear; + + gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .debug(debug_gpmc)); + + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + +`ifdef LOOPBACK + wire [7:0] WHOAMI = 1; + + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + assign tx_underrun = 0; + assign rx_overrun = 0; + + wire run_tx, run_rx, strobe_tx, strobe_rx; +`endif // LOOPBACK + +`ifdef TIMED + wire [7:0] WHOAMI = 2; + + // TX side + wire tx_enable; + + fifo_pacer tx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), + .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), + .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), + .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // RX side + wire rx_enable; + + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), + .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), + .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + +`endif // `ifdef TIMED + +`ifdef DSP + wire [7:0] WHOAMI = 0; + + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx1_data; + wire run_rx; + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), + .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [15:0] tx_i_int, tx_q_int; + wire run_tx; + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + +`else // !`ifdef DSP + // Dummy DSP signal generator for test purposes + wire [23:0] tx_i_int, tx_q_int; + wire [23:0] freq = {reg_test,8'd0}; + reg [23:0] phase; + + always @(posedge wb_clk) + phase <= phase + freq; + + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); + + assign tx_i = tx_i_int[23:10]; + assign tx_q = tx_q_int[23:10]; +`endif // !`ifdef DSP + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s7_ack = 0; + assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + tx_frame_len <= 0; + xfer_rate <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_TX_FRAMELEN : + tx_frame_len <= s0_dat_mosi; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign tx_enable = xfer_rate[15]; + assign rx_enable = xfer_rate[14]; + assign rate = xfer_rate[7:0]; + + assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #5 + + // only have 32 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), + .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { EM_CLK, clk_fpga }; + + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, + { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, + { EM_D } }; + + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + + assign debug_gpio_1 = debug_vt; + +/* + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, + {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, + {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, + {2'b0, bus_error, debug_gpmc[4:0] }, + {misc_gpio[7:0]} }; + */ +endmodule // u1e_core diff --git a/fpga/usrp2/top/u1e_ethdebug/.gitignore b/fpga/usrp2/top/u1e_ethdebug/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/fpga/usrp2/top/u1e_ethdebug/Makefile b/fpga/usrp2/top/u1e_ethdebug/Makefile new file mode 100644 index 000000000..751b52970 --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/Makefile @@ -0,0 +1,83 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e.v \ +u1e.ucf + +SOURCES = $(abspath $(TOP_SRCS)) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf new file mode 100644 index 000000000..d6a2ea4ed --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf @@ -0,0 +1,88 @@ + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; +NET "overo_gpio64" LOC = "A4" ; # nRESET +NET "overo_gpio176" LOC = "B4" ; # IRQ + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.v b/fpga/usrp2/top/u1e_ethdebug/u1e.v new file mode 100644 index 000000000..2a543a313 --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/u1e.v @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +//`define DCM 1 + +module u1e + (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, + + // GPMC + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_NADV_ALE, + + input overo_gpio64, input overo_gpio176 + ); + + assign debug_clk = {EM_CLK, EM_NADV_ALE}; + + assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; + + assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, + { EM_A[10], EM_A[7:1] }, + { EM_D[15:8] }, + { EM_D[7:0] } }; + + +endmodule // u1e diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/u1e_passthru/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile new file mode 100644 index 000000000..d1950629b --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/Makefile @@ -0,0 +1,99 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = passthru +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +passthru.v \ +passthru.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/u1e_passthru/passthru.ucf new file mode 100644 index 000000000..64e6f0440 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/passthru.ucf @@ -0,0 +1,6 @@ +NET "overo_gpio145" LOC = "C7" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; +NET "fpga_cfg_din" LOC = "W17" ; +NET "fpga_cfg_cclk" LOC = "V17" ; diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v new file mode 100644 index 000000000..12e4db017 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio145, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio145; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru diff --git a/fpga/usrp2/top/u2_rev3/.gitignore b/fpga/usrp2/top/u2_rev3/.gitignore new file mode 100644 index 000000000..f50a2b7e5 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3/.gitignore @@ -0,0 +1,57 @@ +/*.ptwx +/*.xrpt +/*.zip +/*_xdb +/templates +/netgen +/_ngo +/_xmsgs +/_pace.ucf +/*.cmd +/*.ibs +/*.lfp +/*.mfp +/*.bit +/*.bin +/*.stx +/*.par +/*.unroutes +/*.ntrc_log +/*.ngr +/*.mrp +/*.html +/*.lso +/*.twr +/*.bld +/*.ncd +/*.txt +/*.cmd_log +/*.drc +/*.map +/*.twr +/*.xml +/*.syr +/*.ngm +/*.xst +/*.csv +/*.html +/*.lock +/*.ncd +/*.twx +/*.ise_ISE_Backup +/*.xml +/*.ut +/*.xpi +/*.ngd +/*.ncd +/*.pad +/*.bgn +/*.ngc +/*.pcf +/*.ngd +/xst +/*.log +/*.rpt +/*.cel +/*.restore +/build* diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/u2_rev3/Makefile new file mode 100644 index 000000000..05ada2476 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3/Makefile @@ -0,0 +1,99 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +PROJECT_PROPERTIES = \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2_core.v \ +u2_rev3.v \ +u2_rev3.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v new file mode 100644 index 000000000..413931ec9 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3/u2_core.v @@ -0,0 +1,737 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=16384, parameter RAM_AW=14) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_time_in, + output exp_time_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + assign dsp_rst = wb_rst; + + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time; + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat; + wire [15:0] ram_loader_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we; + ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) + ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), + .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), + .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), + .wb_we(ram_loader_we), + .ram_loader_done(ram_loader_done), + // CPLD Interface + .cpld_clk(cpld_clk), + .cpld_din(cpld_din), + .cpld_start(cpld_start_int), + .cpld_mode(cpld_mode_int), + .cpld_done(cpld_done_int), + .cpld_detached(cpld_detached)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), + .ram_loader_done_i(ram_loader_done), + + .if_adr(16'b0), .if_data(), + + .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio({io_tx,io_rx}) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd4; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); + + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; + + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + + setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + + assign irq= {{8'b0}, + {8'b0}, + {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), + .wb_ack_o(sd_ack) ); + + assign sd_dat_i[31:8] = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + wire [31:0] vrc_debug; + wire clear_rx; + + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); + + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(clk_to_mac), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + assign RAM_CLK = clk_to_mac; + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + wire [31:0] debug_sync; + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf new file mode 100644 index 000000000..8017f61ff --- /dev/null +++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf @@ -0,0 +1,336 @@ +NET "leds[0]" LOC = "E8" ; +NET "leds[1]" LOC = "F7" ; +NET "leds[2]" LOC = "E5" ; +NET "leds[3]" LOC = "B7" ; +NET "leds[4]" LOC = "C11" ; +NET "leds[5]" LOC = "AB19" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "uart_tx_o" LOC = "C7" ; +NET "uart_rx_i" LOC = "A3" ; +NET "exp_time_in_p" LOC = "V3" ; +NET "exp_time_in_n" LOC = "V4" ; +NET "exp_time_out_p" LOC = "V1" ; +NET "exp_time_out_n" LOC = "V2" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_RX_CLK" LOC = "AA12" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "MDIO" LOC = "Y16" |PULLUP ; +NET "MDC" LOC = "V18" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "PHY_CLK" LOC = "V15" ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_enable" LOC = "W11" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "cpld_start" LOC = "AA9" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_detached" LOC = "V11" ; +NET "cpld_init_b" LOC = "W12" ; +NET "cpld_misc" LOC = "Y12" ; +NET "POR" LOC = "W18" ; +NET "WDI" LOC = "W15" ; +NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; +NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; +NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; +NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; +NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; +NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; +NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; +NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; +NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; +NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; +NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; +NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; +NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; +NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_oen_a" LOC = "E19" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; +NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; +NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; +NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; +NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; +NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; +NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; +NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; +NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; +NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; +NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; +NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; +NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; +NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_lock" LOC = "D6" ; +NET "SCL" LOC = "A7" ; +NET "SDA" LOC = "D8" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "pps_in" LOC = "K1" ; +NET "sclk" LOC = "K5" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sdi" LOC = "J1" ; +NET "sdo" LOC = "J2" ; +NET "sen_tx_db" LOC = "C1" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v new file mode 100644 index 000000000..759f7b7b8 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v @@ -0,0 +1,572 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_rev3 + ( + // Misc, debug + output [5:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_time_in_p, // Diff + input exp_time_in_n, // Diff + output exp_time_out_p, // Diff + output exp_time_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + input cpld_detached,// V11 unused + output cpld_init_b, // W12 unused dual purpose + output cpld_misc, // Y12 + + // Watchdog interface + input POR, + output WDI, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output reg [15:0] dac_a, + output reg [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + assign cpld_init_b = 0; + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + wire clk90, clk180, clk270; + + // reset the watchdog continuously + reg [15:0] wd; + wire config_success; + + always @(posedge wb_clk) + if(~config_success) + wd <= 0; + else + wd <= wd + 1; + assign WDI = wd[15]; + + wire clk_fpga_unbuf; + + IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n)); + BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); + + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire cpld_clock_buf; + BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); + + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + // ADC A and B are swapped in schematic to facilitate clean layout + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_b; + adc_b_reg1 <= adc_a; + adc_ovf_a_reg1 <= adc_ovf_b; + adc_ovf_b_reg1 <= adc_ovf_a; + end + + always @(posedge dsp_clk) + begin + adc_a_reg2 <= adc_a_reg1; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(clk90), + .CLK180(clk180), + .CLK270(clk270), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign leds = 6'b011111 ^ leds_int; // all except eth are active-low + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + wire ser_rx_clk_buf; + BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk)); + always @(posedge ser_rx_clk_buf) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + + wire [17:0] RAM_D_pi; + wire [17:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + // + // DCM edits start here + // + + + wire RAM_CLK_buf; + wire clk_to_mac_buf; + wire clk125_ext_clk0; + wire clk125_ext_clk180; + wire clk125_ext_clk0_buf; + wire clk125_ext_clk180_buf; + wire clk125_int_buf; + wire clk125_int; + + IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), + .O(clk_to_mac_buf)); + + DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_ext_clk0), + .CLK180(clk125_ext_clk180) ); + defparam DCM_INST1.CLK_FEEDBACK = "1X"; + defparam DCM_INST1.CLKDV_DIVIDE = 2.0; + defparam DCM_INST1.CLKFX_DIVIDE = 1; + defparam DCM_INST1.CLKFX_MULTIPLY = 4; + defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST1.CLKIN_PERIOD = 8.000; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; + defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST1.FACTORY_JF = 16'h8080; + defparam DCM_INST1.PHASE_SHIFT = -64; + defparam DCM_INST1.STARTUP_WAIT = "FALSE"; + + IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), + .O(RAM_CLK_buf)); + BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), + .O(clk125_ext_clk0_buf)); + BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), + .O(clk125_ext_clk180_buf)); + + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk125_ext_clk0_buf), + .C1(clk125_ext_clk180_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + +// SRL16 dcm2_rst_i1 (.D(1'b0), +// .CLK(clk_to_mac_buf), +// .Q(dcm2_rst), +// .A0(1'b1), +// .A1(1'b1), +// .A2(1'b1), +// .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i1 is "000F"; + + DCM DCM_INST2 (.CLKFB(clk125_int_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_int)); + defparam DCM_INST2.CLK_FEEDBACK = "1X"; + defparam DCM_INST2.CLKDV_DIVIDE = 2.0; + defparam DCM_INST2.CLKFX_DIVIDE = 1; + defparam DCM_INST2.CLKFX_MULTIPLY = 4; + defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST2.CLKIN_PERIOD = 8.000; + defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST2.FACTORY_JF = 16'h8080; + defparam DCM_INST2.PHASE_SHIFT = 0; + defparam DCM_INST2.STARTUP_WAIT = "FALSE"; + + BUFG clk125_int_buf_i1 (.I(clk125_int), + .O(clk125_int_buf)); + + // + // DCM edits end here + // + + + u2_core #(.RAM_SIZE(16384), .RAM_AW(14)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk125_int_buf), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk_buf), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_pi (RAM_D_pi), + .RAM_D_po (RAM_D_po), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + // .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_rev2 diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile new file mode 100644 index 000000000..5b7ed5a8e --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile @@ -0,0 +1,254 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev3 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/buffer_int.v \ +control_lib/buffer_pool.v \ +control_lib/cascadefifo2.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/fifo_2clock.v \ +control_lib/fifo_2clock_casc.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/longfifo.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +eth/mac_rxfifo_int.v \ +eth/mac_txfifo_int.v \ +eth/rtl/verilog/Clk_ctrl.v \ +eth/rtl/verilog/MAC_rx.v \ +eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ +eth/rtl/verilog/MAC_rx/CRC_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ +eth/rtl/verilog/MAC_top.v \ +eth/rtl/verilog/MAC_tx.v \ +eth/rtl/verilog/MAC_tx/CRC_gen.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ +eth/rtl/verilog/MAC_tx/Random_gen.v \ +eth/rtl/verilog/Phy_int.v \ +eth/rtl/verilog/RMON.v \ +eth/rtl/verilog/RMON/RMON_addr_gen.v \ +eth/rtl/verilog/RMON/RMON_ctrl.v \ +eth/rtl/verilog/Reg_int.v \ +eth/rtl/verilog/eth_miim.v \ +eth/rtl/verilog/flow_ctrl_rx.v \ +eth/rtl/verilog/flow_ctrl_tx.v \ +eth/rtl/verilog/miim/eth_clockgen.v \ +eth/rtl/verilog/miim/eth_outputcontrol.v \ +eth/rtl/verilog/miim/eth_shiftreg.v \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/integrate.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_rev3/u2_rev3.ucf \ +top/u2_rev3/u2_rev3.v \ +top/u2_rev3_2rx_iad/u2_core.v \ +top/u2_rev3_2rx_iad/dsp_core_rx.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, testbench, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +testbench: + iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v + +clean: + rm -rf $(BUILD_DIR) + rm -f dsp_core_tb + rm -f *.lx2 + rm -f *.dat + rm -f *.vcd diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/README b/fpga/usrp2/top/u2_rev3_2rx_iad/README new file mode 100644 index 000000000..3efc5305b --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/README @@ -0,0 +1,32 @@ +This is a custom build for USRP2 FPGA. It allows using a BasicRX or +LFRX board and feed two independent, real signals. In addition, instead +of the CIC/HB decimator, which optimizes frequency response, it uses an +integrate and dump decimator, which optimizes for time-domain impulse +response. + +These changes have been made in dsp_core_rx.v: + +* A second DDC has been added, sharing a frequency register with + the existing DDC. + +* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... + into the receive FIFO. This limits the host configured decimation + to 8 intead of 4. Use gr.deinterleave to recover the streams. + +* The ADCs are hardcoded: + + RX_A ==> DDC #1 I-input + 0 ==> DDC #1 Q-input + RX_B ==> DDC #2 I-input + 0 ==> DDC #2 Q-input + + Thus, the input mux has been disabled. + +* The CIC/HB decimator has been replaced by an integrate and dump at + the decimation rate. + +* To assist with meeting timing, the external RAM has been disabled. + +The basic application is to coherently sample two real IF streams and +downconvert to baseband, while minimizing the impulse response duration +of the resampling filters. diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile b/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile new file mode 100644 index 000000000..34373a676 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile @@ -0,0 +1,4 @@ +-y . +-y ../../sdr_lib +-y ../../control_lib +-y ../../models diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v new file mode 100644 index 000000000..4a945bd1a --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v @@ -0,0 +1,212 @@ +`define DSP_CORE_RX_BASE 160 +module dsp_core_rx + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + input [15:0] io_rx, + + output reg [31:0] sample, + input run, + output strobe, + output [31:0] debug + ); + + wire [15:0] scale_i, scale_q; + wire [13:0] adc_a_ofs, adc_b_ofs; + reg [13:0] adc_i, adc_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [35:0] prod_i, prod_q; + wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b; + wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b; + wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b; + + wire enable_hb1, enable_hb2; // Correspond to std firmware settings + wire [7:0] cic_decim; // for combined CIC/HB decimator + wire [9:0] decim_rate; // Reconstructed original decimation setting + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_a),.adc_out(adc_a_ofs)); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_b),.adc_out(adc_b_ofs)); + +`ifdef MUXCTRL + wire [3:0] muxctrl; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(muxctrl),.changed()); +`endif + + wire [1:0] gpio_ena; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(gpio_ena),.changed()); + + // The TVRX connects to what is called adc_b, thus A and B are + // swapped throughout the design. + // + // In the interest of expediency and keeping the s/w sane, we just remap them here. + // The I & Q fields are mapped the same: + // 0 -> "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + +`ifdef MUXCTRL + always @(posedge clk) + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case(muxctrl[1:0]) + + always @(posedge clk) + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" + 1: adc_q <= adc_a_ofs; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case(muxctrl[3:2]) +`else // !`ifdef MUXCTRL + always @(posedge clk) + begin + adc_i <= adc_a_ofs; + adc_q <= adc_b_ofs; + end +`endif // !`ifdef MUXCTRL + + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + MULT18X18S mult_i + (.P(prod_i), // 36-bit multiplier output + .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S mult_q + (.P(prod_q), // 36-bit multiplier output + .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + + // Route I,0 to first CORDIC + cordic_z24 #(.bitwidth(24)) + cordic_a(.clock(clk), .reset(rst), .enable(run), + .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]), + .xo(i_cordic_a),.yo(q_cordic_a),.zo() ); + + // Route Q,0 to second CORDIC + cordic_z24 #(.bitwidth(24)) + cordic_b(.clock(clk), .reset(rst), .enable(run), + .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]), + .xo(i_cordic_b),.yo(q_cordic_b),.zo() ); + + // Reconstruct original decimation rate from standard firmware settings + assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : + {1'b0,cic_decim,1'b0 }) : + cic_decim; + + cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator + cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), + .strobe_fast(1),.strobe_slow(strobe_iad) ); + + wire strobe_iad_o; + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(i_cordic_a), + .stb_o(strobe_iad_o),.integ_o(i_iad_a) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(q_cordic_a), + .stb_o(),.integ_o(q_iad_a) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(i_cordic_b), + .stb_o(),.integ_o(i_iad_b) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(q_cordic_b), + .stb_o(),.integ_o(q_iad_b) ); + + round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a)); + round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a)); + round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b)); + round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b)); + + reg [31:0] sample_out_a, sample_out_b, sample_out; + reg stb_d1, stb_d2, stb_d3, stb_d4, stb_d5; + reg strobe_out; + + // Register samples on strobe_iad + // Output A on d1 + // Output B on d5 + always @(posedge clk) + begin + stb_d1 <= strobe_iad_o; + stb_d2 <= stb_d1; + stb_d3 <= stb_d2; + stb_d4 <= stb_d3; + stb_d5 <= stb_d4; + end + + always @(posedge clk) + if (strobe_iad_o) + begin + // Streaming GPIO + // io_rx[15] => I channel LSB if gpio_ena[0] high + // io_rx[14] => Q channel LSB if gpio_ena[1] high + sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0], + q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] }; + sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0], + q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] }; + end + + always @(posedge clk) + begin + if (stb_d1) + sample <= sample_out_a; + else if (stb_d5) + sample <= sample_out_b; + strobe_out <= stb_d1|stb_d5; + end + + assign strobe = strobe_out; + assign debug = 0; + +endmodule // dsp_core_rx diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav new file mode 100644 index 000000000..12f746860 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav @@ -0,0 +1,106 @@ +[size] 1680 975 +[pos] -1 -1 +*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] dsp_core_tb. +@200 +-SYSCON +@28 +dsp_core_tb.clk +dsp_core_tb.rst +dsp_core_tb.run +@200 +- +-Settings Bus +@22 +dsp_core_tb.set_addr[7:0] +@24 +dsp_core_tb.set_data[31:0] +@28 +dsp_core_tb.set_stb +@200 +- +-RX DSP CORE +@22 +dsp_core_tb.rx_path.adc_a[13:0] +dsp_core_tb.rx_path.adc_b[13:0] +@28 +dsp_core_tb.rx_path.adc_ovf_a +dsp_core_tb.rx_path.adc_ovf_b +@22 +dsp_core_tb.rx_path.io_rx[15:0] +@200 +- +@22 +dsp_core_tb.rx_path.sample[31:0] +@28 +dsp_core_tb.rx_path.strobe +@200 +- +@22 +dsp_core_tb.rx_path.phase_inc[31:0] +dsp_core_tb.rx_path.scale_i[15:0] +dsp_core_tb.rx_path.scale_q[15:0] +@28 +dsp_core_tb.rx_path.enable_hb1 +dsp_core_tb.rx_path.enable_hb2 +@22 +dsp_core_tb.rx_path.cic_decim[7:0] +dsp_core_tb.rx_path.adc_a_ofs[13:0] +dsp_core_tb.rx_path.adc_b_ofs[13:0] +dsp_core_tb.rx_path.muxctrl[3:0] +@200 +- +@22 +dsp_core_tb.rx_path.adc_i[13:0] +dsp_core_tb.rx_path.adc_q[13:0] +dsp_core_tb.rx_path.phase[31:0] +dsp_core_tb.rx_path.prod_i[35:0] +dsp_core_tb.rx_path.prod_q[35:0] +@8420 +dsp_core_tb.rx_path.i_cordic_a[23:0] +dsp_core_tb.rx_path.q_cordic_a[23:0] +dsp_core_tb.rx_path.i_cordic_b[23:0] +dsp_core_tb.rx_path.q_cordic_b[23:0] +@22 +dsp_core_tb.rx_path.decim_rate[9:0] +@28 +dsp_core_tb.rx_path.strobe_iad +@22 +dsp_core_tb.rx_path.i_iad_a[31:0] +dsp_core_tb.rx_path.q_iad_a[31:0] +@23 +dsp_core_tb.rx_path.i_iad_b[31:0] +@22 +dsp_core_tb.rx_path.q_iad_b[31:0] +@28 +dsp_core_tb.rx_path.strobe_iad_o +@8420 +dsp_core_tb.rx_path.i_out_a[15:0] +dsp_core_tb.rx_path.q_out_a[15:0] +dsp_core_tb.rx_path.i_out_b[15:0] +dsp_core_tb.rx_path.q_out_b[15:0] +@28 +dsp_core_tb.rx_path.gpio_ena[1:0] +@22 +dsp_core_tb.rx_path.sample_out_a[31:0] +dsp_core_tb.rx_path.sample_out_b[31:0] +dsp_core_tb.rx_path.sample[31:0] +@28 +dsp_core_tb.rx_path.strobe_out +dsp_core_tb.rx_path.stb_d1 +dsp_core_tb.rx_path.stb_d2 +dsp_core_tb.rx_path.stb_d3 +dsp_core_tb.rx_path.stb_d4 +dsp_core_tb.rx_path.stb_d5 +@200 +- +-FIFO Bus +@22 +dsp_core_tb.master_time[31:0] +dsp_core_tb.wr_dat[31:0] +@28 +dsp_core_tb.wr_done +dsp_core_tb.wr_error +dsp_core_tb.wr_full +dsp_core_tb.wr_ready +dsp_core_tb.wr_write diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v new file mode 100644 index 000000000..d947df40a --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v @@ -0,0 +1,233 @@ +`timescale 1ns / 100ps + +module dsp_core_tb; + +/////////////////////////////////////////////////////////////////////////////////// +// Sim-wide wires/busses // +/////////////////////////////////////////////////////////////////////////////////// + + // System control bus + reg clk = 0; + reg rst = 1; + + // Configuration bus + reg set_stb = 0; + reg [7:0] set_addr = 0; + reg [31:0] set_data = 0; + + // ADC input bus + wire signed [13:0] adc_a; + wire signed [13:0] adc_b; + wire adc_ovf_a; + wire adc_ovf_b; + + // RX sample bus + reg run = 1; + wire [31:0] sample; + wire stb; + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation control // +/////////////////////////////////////////////////////////////////////////////////// + + // Set up output files + initial begin + $dumpfile("dsp_core_tb.vcd"); + $dumpvars(0,dsp_core_tb); + end + + // Update display every 10 us + always #1000 $monitor("Time in us ",$time/1000); + + // Generate master clock 50% @ 100 MHz + always + #5 clk = ~clk; + +/////////////////////////////////////////////////////////////////////////////////// +// Unit(s) under test // +/////////////////////////////////////////////////////////////////////////////////// + + reg [13:0] amplitude = 13'h1fff; + reg [15:0] impulse_len = 0; + reg [15:0] zero_len = 0; + reg adc_ena = 0; + + initial #500 @(posedge clk) adc_ena = 1; + + impulse adc + (.clk(clk),.rst(rst),.ena(adc_ena), + .dc_offset_a(0),.dc_offset_b(0), + .amplitude(amplitude), + .impulse_len(impulse_len),.zero_len(zero_len), + .adc_a(adc_a),.adc_b(adc_b), + .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); + + initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's + initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset + dsp_core_rx rx_path + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .io_rx(16'b0), + .run(adc_ena),.sample(sample),.strobe(stb), + .debug() ); + + reg [31:0] master_time = 0; + always @(posedge clk) + master_time <= master_time + 1; + + reg wr_ready = 1; + reg wr_full = 0; + + wire [31:0] wr_dat; + wire wr_write; + wire wr_done; + wire wr_error; + wire [15:0] fifo_occupied; + wire fifo_full; + wire fifo_empty; + + rx_control rx_buffer + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time), + .overrun(), // unconnected output + .wr_dat_o(wr_dat), + .wr_write_o(wr_write), + .wr_done_o(wr_done), + .wr_error_o(wr_error), + .wr_ready_i(wr_ready), + .wr_full_i(wr_full), + .sample(sample), + .run(), // unconnected output, supposed to drive 'run' + .strobe(stb), + .fifo_occupied(fifo_occupied), + .fifo_full(fifo_full), + .fifo_empty(fifo_empty), + .debug_rx() // unconnected output + ); + + + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation output/checking // +/////////////////////////////////////////////////////////////////////////////////// + + integer rx_file; + + initial + rx_file = $fopen("rx.dat", "wb"); + + always @(posedge clk) + begin + // Write RX sample I&Q in format Octave can load + if (stb) + begin + $fwrite(rx_file, sample[31:16]); + $fputc(32, rx_file); + $fwrite(rx_file, sample[15:0]); + $fputc(13, rx_file); + end + end + +/////////////////////////////////////////////////////////////////////////////////// +// Tasks // +/////////////////////////////////////////////////////////////////////////////////// + + task power_on; + begin + @(posedge clk) + rst = #1 1'b1; + @(posedge clk) + rst = #1 1'b0; + end + endtask // power_on + + task set_impulse_len; + input [15:0] len; + @(posedge clk) impulse_len = len-1; + endtask + + task set_zero_len; + input [15:0] len; + @(posedge clk) zero_len = len-1; + endtask + + // Strobe configuration bus with addr, data + task write_cfg_register; + input [7:0] regno; + input [31:0] value; + + begin + @(posedge clk); + set_addr <= regno; + set_data <= value; + set_stb <= 1'b1; + @(posedge clk); + set_stb <= 1'b0; + end + endtask // write_cfg_register + + // Set RX DDC frequency + task set_ddc_freq; + input [31:0] freq; + + write_cfg_register(160, freq); + endtask // set_ddc_freq + + // Set RX IQ scaling registers + task set_rx_scale_iq; + input [15:0] scale_i; + input [15:0] scale_q; + + write_cfg_register(161, {scale_i,scale_q}); + endtask // set_rx_scale_iq + + // Set RX MUX control + task set_rx_muxctrl; + input [3:0] muxctrl; + + write_cfg_register(168, muxctrl); + endtask // set_rx_muxctrl + + // Set RX CIC decim and halfband enables + task set_decim; + input hb1_ena; + input hb2_ena; + input [7:0] decim; + + write_cfg_register(162, {hb1_ena,hb2_ena,decim}); + endtask // set_decim + + +/////////////////////////////////////////////////////////////////////////////////// +// Individual tests // +/////////////////////////////////////////////////////////////////////////////////// + + task test_rx; + begin + set_impulse_len(10); + set_zero_len(990); + set_rx_muxctrl(1); + set_ddc_freq(32'h10000000); + set_rx_scale_iq(1243, 1243); + set_decim(1, 1, 1); + + #100000 $finish; + end + endtask // test_rx + + +/////////////////////////////////////////////////////////////////////////////////// +// Top-level test // +/////////////////////////////////////////////////////////////////////////////////// + + // Execute tests + initial + begin + power_on(); + test_rx(); + end + +endmodule // dsp_core_tb diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v b/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v new file mode 100644 index 000000000..fc5e3c1ed --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v @@ -0,0 +1,68 @@ +module impulse + (input clk, + input rst, + input ena, + + input [13:0] dc_offset_a, + input [13:0] dc_offset_b, + input [13:0] amplitude, + input [15:0] impulse_len, + input [15:0] zero_len, + + output [13:0] adc_a, + output [13:0] adc_b, + output adc_ovf_a, + output adc_ovf_b + ); + + reg [13:0] adc_a_int = 0; + reg [13:0] adc_b_int = 0; + + reg [15:0] count; + + localparam ST_ZERO = 0; + localparam ST_HIGH = 1; + reg state; + + always @(posedge clk) + if (rst | ~ena) + begin + adc_a_int <= 0; + adc_b_int <= 0; + count <= 0; + state <= ST_ZERO; + end + else + case(state) + ST_ZERO: + if (count == zero_len) + begin + adc_a_int <= amplitude; + adc_b_int <= amplitude >> 2; + state <= ST_HIGH; + count <= 0; + end + else + count <= count + 1; + + ST_HIGH: + if (count == impulse_len) + begin + adc_a_int <= 0; + adc_b_int <= 0; + state <= ST_ZERO; + count <= 0; + end + else + count <= count + 1; + + endcase // case (state) + + assign adc_a = adc_a_int + dc_offset_a; + assign adc_b = adc_b_int + dc_offset_b; + + // Ignore for now + assign adc_ovf_a = 0; + assign adc_ovf_b = 0; + +endmodule // impulse diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v b/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v new file mode 100755 index 000000000..3d96a4e0e --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v @@ -0,0 +1,789 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=32768) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, + s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; + wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; + wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; + + wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), + .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), + .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), + .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), + .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), + .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), + .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), + .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), + .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), + .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), + .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), + .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), + .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), + .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), + .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), + .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + assign s0_err = 1'b0; + assign s0_rty = 1'b0; + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // Buffer Pool, slave #1 + wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; + wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; + wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; + wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; + wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; + wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; + wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), + .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), + .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), + .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), + .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), + .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), + .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), + .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), + // Read Interfaces + .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), + .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), + .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), + .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), + .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), + .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), + .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), + .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) + ); + + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + assign s2_rty = 1'b0; + + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + assign s3_err = 1'b0; + assign s3_rty = 1'b0; + + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + assign s4_err = 1'b0; + assign s4_rty = 1'b0; + + // Buffer Pool Status -- Slave #5 + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), + .wb_dat_o(s5_dat_i), + .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), + .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) + ); + + assign s5_err = 1'b0; + assign s5_rty = 1'b0; + + // Slave, #6 Ethernet MAC, see below + + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_err = 1'b0; + assign s7_rty = 1'b0; + assign s7_dat_i = 32'd0; + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {clk_status,serdes_link_up}; + + setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; + wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; + wire [31:0] Tx_mac_data, Rx_mac_data; + wire [1:0] Tx_mac_BE, Rx_mac_BE; + wire rst_mac; + + oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); + + MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) + MAC_top + (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), + .rst_mac(rst_mac),.rst_user(dsp_rst), + .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), + .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), + .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), + .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), + .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), + .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), + .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), + .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), + .Crs(GMII_CRS),.Col(GMII_COL), + .Mdio(MDIO),.Mdc(MDC), + .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), + .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), + .debug0(debug_mac0),.debug1(debug_mac1) ); + + assign s6_err = 1'b0; + assign s6_rty = 1'b0; + + mac_rxfifo_int mac_rxfifo_int + (.clk(dsp_clk),.rst(dsp_rst), + .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), + .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), + .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), + .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), + .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), + .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); + + mac_txfifo_int mac_txfifo_int + (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), + .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), + .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), + .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), + .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), + .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; + + simple_pic #(.is(16),.dwidth(32)) simple_pic + (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + assign s8_err = 0; + assign s8_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + assign s9_err = 0; + assign s9_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), + .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + assign s10_err = 0; + assign s10_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), + .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + assign s11_err = 0; + assign s11_rty = 0; + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; + always @(negedge dsp_clk) pps_negedge <= pps_in; + always @(posedge dsp_clk) pps_posedge <= pps_in; + always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; + always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; + + wire pps_o; + time_sync time_sync + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), + .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), + .sys_clk_i(dsp_clk),.master_time_o(master_time), + .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), + .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), + .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); + assign s12_err = 0; + assign s12_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we), + .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i), + .wb_ack_o(s13_ack) ); + assign s13_err = 0; + assign s13_rty = 0; + // ///////////////////////////////////////////////////////////////////////// + // DSP + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + + rx_control #(.FIFOSIZE(10)) rx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.overrun(overrun), + .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), + .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), + .debug_rx(debug_rx) ); + + // dummy_rx dsp_core_rx + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + tx_control #(.FIFOSIZE(10)) tx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.underrun(underrun), + .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), + .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), + .debug(debug_txc) ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), + .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), + .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + +`ifdef EXTRAM + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes + + wire [15:0] bus2ram, ram2bus; + wire [15:0] bridge_adr; + wire [1:0] bridge_sel; + wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; + + wire [19:0] page; + wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; + setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(page),.changed()); + + wb_bridge_16_32 bridge + (.wb_clk(wb_clk),.wb_rst(wb_rst), + .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), + .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), + .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), + .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); + + wb_zbt16_b wb_zbt16_b + (.clk(wb_clk),.rst(wb_rst), + .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), + .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), + .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), + .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), + .sram_mode(),.sram_zz() ); + + assign s14_err = 0; assign s14_rty = 0; + assign RAM_CE1n = 0; + assign RAM_D[17:16] = 2'bzz; +`endif + +`ifdef DEBUG + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; + + always @(posedge dsp_clk) + serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + assign debug_clk[0] = 0; + assign debug_clk[1] = dsp_clk; + + assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; +`endif + +endmodule // u2_core + +// wire debug_mux; +// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), +// .in(set_data),.out(debug_mux),.changed()); + +//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; +//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; + +//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, +// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + +//assign debug = debug_tx_dsp; +//assign debug = debug_serdes0; + +//assign debug_gpio_0 = 0; //debug_serdes0; +//assign debug_gpio_1 = 0; //debug_serdes1; + +// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, +// {8'b0}, +// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, +// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; + +//assign debug = {dac_a,dac_b}; + +/* + assign debug = {{ram_loader_done, takeover, 6'd0}, + {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, + {8'd0}, + {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ + +/*assign debug = host_to_dsp_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; + */ +// Assign various commonly used debug buses. +/* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh b/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh new file mode 100755 index 000000000..626f224e5 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/fpga/usrp2/top/u2_rev3_iad/.gitignore b/fpga/usrp2/top/u2_rev3_iad/.gitignore new file mode 100644 index 000000000..e4daaf1ea --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/.gitignore @@ -0,0 +1,4 @@ +/build +/*.vcd +/dsp_core_tb +/*.dat diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile new file mode 100644 index 000000000..5ae8846dd --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/Makefile @@ -0,0 +1,254 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev3 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/buffer_int.v \ +control_lib/buffer_pool.v \ +control_lib/cascadefifo2.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/fifo_2clock.v \ +control_lib/fifo_2clock_casc.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/longfifo.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +eth/mac_rxfifo_int.v \ +eth/mac_txfifo_int.v \ +eth/rtl/verilog/Clk_ctrl.v \ +eth/rtl/verilog/MAC_rx.v \ +eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ +eth/rtl/verilog/MAC_rx/CRC_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ +eth/rtl/verilog/MAC_top.v \ +eth/rtl/verilog/MAC_tx.v \ +eth/rtl/verilog/MAC_tx/CRC_gen.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ +eth/rtl/verilog/MAC_tx/Random_gen.v \ +eth/rtl/verilog/Phy_int.v \ +eth/rtl/verilog/RMON.v \ +eth/rtl/verilog/RMON/RMON_addr_gen.v \ +eth/rtl/verilog/RMON/RMON_ctrl.v \ +eth/rtl/verilog/Reg_int.v \ +eth/rtl/verilog/eth_miim.v \ +eth/rtl/verilog/flow_ctrl_rx.v \ +eth/rtl/verilog/flow_ctrl_tx.v \ +eth/rtl/verilog/miim/eth_clockgen.v \ +eth/rtl/verilog/miim/eth_outputcontrol.v \ +eth/rtl/verilog/miim/eth_shiftreg.v \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/integrate.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2_rev3/u2_rev3.ucf \ +top/u2_rev3/u2_rev3.v \ +top/u2_rev3_iad/dsp_core_rx.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, testbench, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +testbench: + iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v + +clean: + rm -rf $(BUILD_DIR) + rm -f dsp_core_tb + rm -f *.lx2 + rm -f *.dat + rm -f *.vcd diff --git a/fpga/usrp2/top/u2_rev3_iad/cmdfile b/fpga/usrp2/top/u2_rev3_iad/cmdfile new file mode 100644 index 000000000..34373a676 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/cmdfile @@ -0,0 +1,4 @@ +-y . +-y ../../sdr_lib +-y ../../control_lib +-y ../../models diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v new file mode 100644 index 000000000..2882464ba --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v @@ -0,0 +1,158 @@ +`define DSP_CORE_RX_BASE 160 +module dsp_core_rx + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + input [15:0] io_rx, + + output [31:0] sample, + input run, + output strobe, + output [31:0] debug + ); + + wire [15:0] scale_i, scale_q; + wire [13:0] adc_a_ofs, adc_b_ofs; + reg [13:0] adc_i, adc_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [35:0] prod_i, prod_q; + wire [23:0] i_cordic, q_cordic; + wire [31:0] i_iad, q_iad; + wire [15:0] i_out, q_out; + + wire enable_hb1, enable_hb2; // Correspond to std firmware settings + wire [7:0] cic_decim; // for combined CIC/HB decimator + wire [9:0] decim_rate; // Reconstructed original decimation setting + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_a),.adc_out(adc_a_ofs)); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_b),.adc_out(adc_b_ofs)); + + wire [3:0] muxctrl; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(muxctrl),.changed()); + + wire [1:0] gpio_ena; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(gpio_ena),.changed()); + + // The TVRX connects to what is called adc_b, thus A and B are + // swapped throughout the design. + // + // In the interest of expediency and keeping the s/w sane, we just remap them here. + // The I & Q fields are mapped the same: + // 0 -> "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + + always @(posedge clk) + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case(muxctrl[1:0]) + + always @(posedge clk) + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" + 1: adc_q <= adc_a_ofs; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case(muxctrl[3:2]) + + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + MULT18X18S mult_i + (.P(prod_i), // 36-bit multiplier output + .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S mult_q + (.P(prod_q), // 36-bit multiplier output + .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + + cordic_z24 #(.bitwidth(24)) + cordic(.clock(clk), .reset(rst), .enable(run), + .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]), + .xo(i_cordic),.yo(q_cordic),.zo() ); + + // Reconstruct original decimation rate from standard firmware settings + assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : + {1'b0,cic_decim,1'b0 }) : + cic_decim; + + cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator + cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), + .strobe_fast(1),.strobe_slow(strobe_iad) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(i_cordic), + .stb_o(strobe),.integ_o(i_iad) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(q_cordic), + .stb_o(),.integ_o(q_iad) ); + + round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out)); + round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out)); + + // Streaming GPIO + // + // io_rx[15] => I channel LSB if gpio_ena[0] high + // io_rx[14] => Q channel LSB if gpio_ena[1] high + + reg [31:0] sample_reg; + always @(posedge clk) + begin + sample_reg[31:17] <= i_out[15:1]; + sample_reg[15:1] <= q_out[15:1]; + sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; + sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; + end + + assign sample = sample_reg; + assign debug = {clk, rst, run, strobe}; + +endmodule // dsp_core_rx diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav new file mode 100644 index 000000000..17c90cdd7 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav @@ -0,0 +1,61 @@ +[size] 1680 975 +[pos] -1 -1 +*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] dsp_core_tb. +@200 +-SYSCON +@28 +dsp_core_tb.clk +dsp_core_tb.rst +dsp_core_tb.run +@200 +- +-Settings Bus +@22 +dsp_core_tb.set_addr[7:0] +@24 +dsp_core_tb.set_data[31:0] +@28 +dsp_core_tb.set_stb +@200 +- +-RX DSP CORE +- +@24 +dsp_core_tb.rx_path.decim_rate[9:0] +@200 +- +@8420 +dsp_core_tb.adc_a[13:0] +@20000 +- +@200 +- +@8420 +dsp_core_tb.rx_path.adc_a_ofs[13:0] +@20000 +- +@200 +- +@8022 +dsp_core_tb.rx_path.i_cordic[23:0] +@20000 +- +@200 +- +@8022 +dsp_core_tb.rx_path.i_iad[31:0] +@20000 +- +@200 +- +@8420 +dsp_core_tb.rx_path.i_out[15:0] +@20000 +- +@200 +- +@28 +dsp_core_tb.stb +@200 +- diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v new file mode 100644 index 000000000..4d5a5b537 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v @@ -0,0 +1,196 @@ +`timescale 1ns / 100ps + +module dsp_core_tb; + +/////////////////////////////////////////////////////////////////////////////////// +// Sim-wide wires/busses // +/////////////////////////////////////////////////////////////////////////////////// + + // System control bus + reg clk = 0; + reg rst = 1; + + // Configuration bus + reg set_stb = 0; + reg [7:0] set_addr = 0; + reg [31:0] set_data = 0; + + // ADC input bus + wire signed [13:0] adc_a; + wire signed [13:0] adc_b; + wire adc_ovf_a; + wire adc_ovf_b; + + // RX sample bus + reg run = 1; + wire [31:0] sample; + wire stb; + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation control // +/////////////////////////////////////////////////////////////////////////////////// + + // Set up output files + initial begin + $dumpfile("dsp_core_tb.vcd"); + $dumpvars(0,dsp_core_tb); + end + + // Update display every 10 us + always #1000 $monitor("Time in us ",$time/1000); + + // Generate master clock 50% @ 100 MHz + always + #5 clk = ~clk; + +/////////////////////////////////////////////////////////////////////////////////// +// Unit(s) under test // +/////////////////////////////////////////////////////////////////////////////////// + + reg [13:0] amplitude = 13'h1fff; + reg [15:0] impulse_len = 0; + reg [15:0] zero_len = 0; + reg adc_ena = 0; + + initial #500 @(posedge clk) adc_ena = 1; + + impulse adc + (.clk(clk),.rst(rst),.ena(adc_ena), + .dc_offset_a(0),.dc_offset_b(0), + .amplitude(amplitude), + .impulse_len(impulse_len),.zero_len(zero_len), + .adc_a(adc_a),.adc_b(adc_b), + .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); + + initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's + initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset + dsp_core_rx rx_path + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .io_rx(16'b0), + .run(adc_ena),.sample(sample),.strobe(stb), + .debug() ); + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation output/checking // +/////////////////////////////////////////////////////////////////////////////////// + + integer rx_file; + + initial + rx_file = $fopen("rx.dat", "wb"); + + always @(posedge clk) + begin + // Write RX sample I&Q in format Octave can load + if (stb) + begin + $fwrite(rx_file, sample[31:16]); + $fputc(32, rx_file); + $fwrite(rx_file, sample[15:0]); + $fputc(13, rx_file); + end + end + +/////////////////////////////////////////////////////////////////////////////////// +// Tasks // +/////////////////////////////////////////////////////////////////////////////////// + + task power_on; + begin + @(posedge clk) + rst = #1 1'b1; + @(posedge clk) + rst = #1 1'b0; + end + endtask // power_on + + task set_impulse_len; + input [15:0] len; + @(posedge clk) impulse_len = len-1; + endtask + + task set_zero_len; + input [15:0] len; + @(posedge clk) zero_len = len-1; + endtask + + // Strobe configuration bus with addr, data + task write_cfg_register; + input [7:0] regno; + input [31:0] value; + + begin + @(posedge clk); + set_addr <= regno; + set_data <= value; + set_stb <= 1'b1; + @(posedge clk); + set_stb <= 1'b0; + end + endtask // write_cfg_register + + // Set RX DDC frequency + task set_ddc_freq; + input [31:0] freq; + + write_cfg_register(160, freq); + endtask // set_ddc_freq + + // Set RX IQ scaling registers + task set_rx_scale_iq; + input [15:0] scale_i; + input [15:0] scale_q; + + write_cfg_register(161, {scale_i,scale_q}); + endtask // set_rx_scale_iq + + // Set RX MUX control + task set_rx_muxctrl; + input [3:0] muxctrl; + + write_cfg_register(168, muxctrl); + endtask // set_rx_muxctrl + + // Set RX CIC decim and halfband enables + task set_decim; + input hb1_ena; + input hb2_ena; + input [7:0] decim; + + write_cfg_register(162, {hb1_ena,hb2_ena,decim}); + endtask // set_decim + + +/////////////////////////////////////////////////////////////////////////////////// +// Individual tests // +/////////////////////////////////////////////////////////////////////////////////// + + task test_rx; + begin + set_impulse_len(1); + set_zero_len(999); + set_rx_muxctrl(1); + set_ddc_freq(0); + set_rx_scale_iq(1243, 1243); + set_decim(0, 1, 3); + + #100000 $finish; + end + endtask // test_rx + + +/////////////////////////////////////////////////////////////////////////////////// +// Top-level test // +/////////////////////////////////////////////////////////////////////////////////// + + // Execute tests + initial + begin + power_on(); + test_rx(); + end + +endmodule // dsp_core_tb diff --git a/fpga/usrp2/top/u2_rev3_iad/impulse.v b/fpga/usrp2/top/u2_rev3_iad/impulse.v new file mode 100644 index 000000000..7f0cdc9be --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/impulse.v @@ -0,0 +1,63 @@ +module impulse + (input clk, + input rst, + input ena, + + input [13:0] dc_offset_a, + input [13:0] dc_offset_b, + input [13:0] amplitude, + input [15:0] impulse_len, + input [15:0] zero_len, + + output [13:0] adc_a, + output [13:0] adc_b, + output adc_ovf_a, + output adc_ovf_b + ); + + reg [13:0] adc_a_int = 0; + reg [15:0] count; + + localparam ST_ZERO = 0; + localparam ST_HIGH = 1; + reg state; + + always @(posedge clk) + if (rst | ~ena) + begin + adc_a_int <= 0; + count <= 0; + state <= ST_ZERO; + end + else + case(state) + ST_ZERO: + if (count == zero_len) + begin + adc_a_int <= amplitude; + state <= ST_HIGH; + count <= 0; + end + else + count <= count + 1; + + ST_HIGH: + if (count == impulse_len) + begin + adc_a_int <= 0; + state <= ST_ZERO; + count <= 0; + end + else + count <= count + 1; + + endcase // case (state) + + assign adc_a = adc_a_int + dc_offset_a; + + // Ignore for now + assign adc_b = dc_offset_b; + assign adc_ovf_a = 0; + assign adc_ovf_b = 0; + +endmodule // impulse diff --git a/fpga/usrp2/top/u2_rev3_iad/wave.sh b/fpga/usrp2/top/u2_rev3_iad/wave.sh new file mode 100755 index 000000000..626f224e5 --- /dev/null +++ b/fpga/usrp2/top/u2_rev3_iad/wave.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/fpga/usrp2/top/u2plus/.gitignore b/fpga/usrp2/top/u2plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/u2plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile new file mode 100644 index 000000000..c38bd3ec1 --- /dev/null +++ b/fpga/usrp2/top/u2plus/Makefile @@ -0,0 +1,99 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi new file mode 100644 index 000000000..4c7d918c0 --- /dev/null +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -0,0 +1,216 @@ +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4b70400_3a0b0b0b_0bae9c0c_80700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4f42d_88080b0b_80088408; +defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; +defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; +defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; +defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; +defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; +defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; +defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88; +defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06; +defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; +defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; +defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; +defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; +defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; +defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_88738306_0b0b0bae_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ae2d5050_0b0b0b9e_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_e02d5050_0b0b0b9f_88087575_80088408; +defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; +defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; +defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae980c_810b0b0b; +defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; +defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; +defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_943f0410_81f33f9e; +defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; +defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; +defparam bootram.RAM0.INIT_23=256'hec0c8290_a0800bb5_b5e80c82_0b0b0b0b_38838080_08822eb9_a138ae9c_9808802e; +defparam bootram.RAM0.INIT_24=256'h80808480_b5ec0cf8_8082800b_e80cf880_0b0b0bb5_8080a40b_0c04f880_800bb5f0; +defparam bootram.RAM0.INIT_25=256'h0ba6c40b_ec0c0b0b_80940bb5_0c80c0a8_0b0bb5e8_808c0b0b_0480c0a8_0bb5f00c; +defparam bootram.RAM0.INIT_26=256'haea40c70_92388412_5270802e_08700852_a338aea4_f4335170_ff3d0db5_b5f00c04; +defparam bootram.RAM0.INIT_27=256'he408802e_0b0b0bb5_04803d0d_833d0d04_0bb5f434_70f03881_70085252_2daea408; +defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5e4_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; +defparam bootram.RAM0.INIT_29=256'h518bc93f_d0055273_3fb23dfe_525486a0_59923d70_3dfee005_d03d0db2_3d0d0404; +defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_c93fa6c8_52735198_38765378_ff74278f_775481ff_8008b238; +defparam bootram.RAM0.INIT_2B=256'hb039803d_859e3fff_39a78051_a6cc5184_3f91d73f_c85185ac_068f38a6_812e0981; +defparam bootram.RAM0.INIT_2C=256'h0ca78851_0b81a08c_3d0d81ff_3d0d04fc_51f63982_380bff11_70ff2e87_0dff1351; +defparam bootram.RAM0.INIT_2D=256'h81ff0655_ee3f8008_84e23f83_3fa78451_e13f86d6_85e13f8e_81a08c0c_dd3f800b; +defparam bootram.RAM0.INIT_2E=256'h81fc8080_5184bd3f_c338a7b0_51547380_70810651_08708d2a_3f81c6b4_805182ed; +defparam bootram.RAM0.INIT_2F=256'h8eab3f90_fc808051_ffff5281_80805380_82c33f82_a6388151_8008802e_5190b63f; +defparam bootram.RAM0.INIT_30=256'he45183f8_74b238a8_3ffe8d3f_8c518484_3f8a39a8_73519192_5184913f_c53fa7d0; +defparam bootram.RAM0.INIT_31=256'hfec03fb0_3f82ac51_815181f9_5183e53f_9938a990_8008802e_518fa13f_3fb0800a; +defparam bootram.RAM0.INIT_32=256'h83ba3f82_38aa9851_08802eaa_8fc73f80_98800a51_5183cd3f_d93fa9c8_800a5190; +defparam bootram.RAM0.INIT_33=256'h3faae851_853f8fca_82ac51fe_5183a53f_bc3faac4_800a518d_ffff5298_80805380; +defparam bootram.RAM0.INIT_34=256'h5380ffff_38828080_08802eb5_80085480_518f8a3f_81fc8080_5183913f_ba39aba4; +defparam bootram.RAM0.INIT_35=256'hdb3f82ac_a7d05182_3f8f8f3f_ac51fdca_82ea3f82_3faac451_80518d81_5281fc80; +defparam bootram.RAM0.INIT_36=256'h04f83d0d_0c863d0d_cf3f7380_82c63ffc_39a88c51_3f81548a_80518fd6_51fdbb3f; +defparam bootram.RAM0.INIT_37=256'h70810558_8a3d3476_17575473_b7387581_54807425_74ff1656_5a575758_7a7c7f7f; +defparam bootram.RAM0.INIT_38=256'h8a5186fd_81ff0654_cf3f8008_ff065185_05527781_538a3dfc_a1053482_33028405; +defparam bootram.RAM0.INIT_39=256'h748338dc_5580de56_02a30533_04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e; +defparam bootram.RAM0.INIT_3A=256'h7c5702ab_04f93d0d_3f883d0d_d051ff89_81f75280_3dfc0553_34815488_5675883d; +defparam bootram.RAM0.INIT_3B=256'h56547380_81ff0670_ef3f8008_70525684_02a70533_3dfc0552_34815389_0533893d; +defparam bootram.RAM0.INIT_3C=256'h83388155_5473802e_ff067056_3f800881_755183b2_76537b52_77259738_2e9e3880; +defparam bootram.RAM0.INIT_3D=256'h883d3356_a03f800b_80d051ff_5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89; +defparam bootram.RAM0.INIT_3E=256'h7081ff06_56567433_3d0d7779_3d0d04fb_75800c88_83388156_2e098106_567480de; +defparam bootram.RAM0.INIT_3F=256'h0d04fe3d_800c873d_e539800b_5581bb3f_06537652_157481ff_2e903881_54547280; +defparam bootram.RAM1.INIT_00=256'h528051de_ff3d0d73_843d0d04_800b800c_51819f3f_3f8a5272_705253cb_0d747653; +defparam bootram.RAM1.INIT_01=256'h800881ff_80087334_5181b23f_81135374_55558439_76787055_04fc3d0d_3f833d0d; +defparam bootram.RAM1.INIT_02=256'h3f833d0d_528051c9_ff3d0d73_863d0d04_3473800c_e7388073_2e098106_0652718a; +defparam bootram.RAM1.INIT_03=256'h7510abe0_81ce8005_0d73a029_0d04ff3d_1234823d_0533aea8_7251028f_04803d0d; +defparam bootram.RAM1.INIT_04=256'h33527251_3faeac13_527251c9_aea81333_3d0d8053_3d0d04fe_0c535183_05702272; +defparam bootram.RAM1.INIT_05=256'h38aea814_09810694_54748a2e_0d767856_0d04fc3d_e738843d_53827325_d13f8113; +defparam bootram.RAM1.INIT_06=256'h72802ef8_84140853_ce800554_73a02981_7351df3f_87388d52_2e098106_33537281; +defparam bootram.RAM1.INIT_07=256'h38901208_70802ef8_88120851_ce800552_73a02981_04ff3d0d_0c863d0d_38748c15; +defparam bootram.RAM1.INIT_08=256'h38845170_84712583_8f065151_c6a40870_c2880c81_0d800b81_0d04ff3d_800c833d; +defparam bootram.RAM1.INIT_09=256'h880c833d_800b81c2_0c515181_2a81c284_800c7088_ff0681c2_70227081_10aeb005; +defparam bootram.RAM1.INIT_0A=256'h70862a70_81c29008_2e818638_81517180_33555354_88059705_0d767802_0d04fd3d; +defparam bootram.RAM1.INIT_0B=256'h812a7081_c2900870_c2900c81_81900b81_81c28c0c_72108107_5170f138_81065151; +defparam bootram.RAM1.INIT_0C=256'h3871802e_70802eba_51515151_06708132_872a7081_c2900870_70f13881_06515151; +defparam bootram.RAM1.INIT_0D=256'h515170f1_70810651_0870812a_0c81c290_7081c290_8338a051_5171812e_b13880e8; +defparam bootram.RAM1.INIT_0E=256'h0c70800c_0b81c290_883980c0_cc398151_34ff1252_70810556_08517074_3881c28c; +defparam bootram.RAM1.INIT_0F=256'h51515170_2a708106_90087086_535481c2_97053355_78028805_fd3d0d76_853d0d04; +defparam bootram.RAM1.INIT_10=256'h70812a70_81c29008_81c2900c_81905170_802e8438_81d05171_81c28c0c_f1387210; +defparam bootram.RAM1.INIT_11=256'h80cf3871_5170802e_32515151_81067081_70872a70_81c29008_5170f138_81065151; +defparam bootram.RAM1.INIT_12=256'h90087081_900c81c2_517081c2_2e833890_d0517181_c28c0c80_38733381_802e80c5; +defparam bootram.RAM1.INIT_13=256'h802e8e38_51515170_70813251_2a708106_90087087_f13881c2_51515170_2a708106; +defparam bootram.RAM1.INIT_14=256'h04ff3d0d_0c853d0d_80517080_81c2900c_3980c00b_3981518a_5354ffb7_8114ff13; +defparam bootram.RAM1.INIT_15=256'hc01122ae_108e06ae_c6a40870_25923881_aebc0880_7124a638_08525280_7381c6a4; +defparam bootram.RAM1.INIT_16=256'hffa91170_028f0533_04ff3d0d_38833d0d_115170fb_387151ff_80722589_bc0c5151; +defparam bootram.RAM1.INIT_17=256'h81ff0651_38d01270_71b92689_ff065151_c9127081_da269638_52527180_81ff0651; +defparam bootram.RAM1.INIT_18=256'h82ef3881_2e098106_ff5371ba_76335358_7b585680_f93d0d79_833d0d04_5170800c; +defparam bootram.RAM1.INIT_19=256'hc4065151_11337080_7033abf5_ff067219_81147081_2eaa3872_53537178_0b811733; +defparam bootram.RAM1.INIT_1A=256'h08842b9f_fefb3f80_81163351_5271d838_16703351_82bd3872_5271802e_51535154; +defparam bootram.RAM1.INIT_1B=256'h5354fd53_8b113357_0c701017_05708419_81ff0672_ec3f8008_335252fe_f0068217; +defparam bootram.RAM1.INIT_1C=256'h08882b83_febb3f80_17335253_e0800684_088c2bbf_fecb3f80_83163351_74828a38; +defparam bootram.RAM1.INIT_1D=256'h983f8008_335253fe_73058617_2b9ff006_3f800884_5253fea9_05851733_fe800673; +defparam bootram.RAM1.INIT_1E=256'hf83f8008_335252fd_f0068817_08842b9f_fe873f80_87163351_0588180c_81ff0673; +defparam bootram.RAM1.INIT_1F=256'h05523355_19707081_19081771_81ff068c_10890570_80d23874_34747427_12527177; +defparam bootram.RAM1.INIT_20=256'h8c170815_53727434_3f800813_5253fdc1_f0067233_08842b9f_fdcf3f80_52565152; +defparam bootram.RAM1.INIT_21=256'h84170888_26ffb038_84170875_5b515152_ff065a52_81197081_7081ff06_7033701a; +defparam bootram.RAM1.INIT_22=256'h5b515354_11335654_73101a89_7081ff06_05197030_2a055473_72057188_18087833; +defparam bootram.RAM1.INIT_23=256'h5377722e_065152fb_127081ff_e43f8008_335252fc_f0068a15_08842b9f_fcf33f80; +defparam bootram.RAM1.INIT_24=256'h882a7081_d6900870_803d0d81_893d0d04_5372800c_53833980_388539fe_09810689; +defparam bootram.RAM1.INIT_25=256'hc0800753_80060780_ff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151; +defparam bootram.RAM1.INIT_26=256'h81ff0681_d6900c75_800c7181_387681d6_515170f1_70810651_0870882a_5381d690; +defparam bootram.RAM1.INIT_27=256'h51515170_2a708106_90087088_963881d6_5172802e_d6900c72_82800781_d6980c71; +defparam bootram.RAM1.INIT_28=256'h80538052_80558854_d6940c88_0d810b81_0d04fc3d_800c843d_80085170_f13881d6; +defparam bootram.RAM1.INIT_29=256'h900c8b0b_800b81d6_d6980c88_3f800b81_7d56fee4_04f63d0d_3f863d0d_8051ff87; +defparam bootram.RAM1.INIT_2A=256'hd6900cfe_8aa80b81_81d6900c_0c88a80b_0b81d698_d6800c81_7c882b81_81d6840c; +defparam bootram.RAM1.INIT_2B=256'h3f81d68c_900cfe98_800b81d6_d6900c8a_88800b81_2780d338_80547376_b33f7e55; +defparam bootram.RAM1.INIT_2C=256'h27833870_90537073_75315257_5b883d76_81d68008_d684085a_88085981_085881d6; +defparam bootram.RAM1.INIT_2D=256'ha939800b_721454ff_1252ec39_05573481_33757081_71175170_73279138_53805271; +defparam bootram.RAM1.INIT_2E=256'h9d055755_80028405_51fed23f_80c05268_3d705457_ea3d0d88_8c3d0d04_81d6980c; +defparam bootram.RAM1.INIT_2F=256'h81992e09_33515473_38741670_09810694_7381aa2e_ff2e9d38_51547381_74177033; +defparam bootram.RAM1.INIT_30=256'h863d7054_04f93d0d_0c983d0d_80547380_7527d138_811555be_81548b39_81068538; +defparam bootram.RAM1.INIT_31=256'h38815574_09810683_8008752e_5185f73f_abec5273_80558653_51fe823f_54865279; +defparam bootram.RAM1.INIT_32=256'h0771832a_0671872a_70852a82_02970533_04fd3d0d_81a0940c_0d04810b_800c893d; +defparam bootram.RAM1.INIT_33=256'h76852b80_7081ff06_71730707_832ba006_10900674_73070773_2a880671_84067281; +defparam bootram.RAM1.INIT_34=256'h0d04fe3d_5552853d_51555255_0c515253_0681d480_077081ff_0778872b_c0067072; +defparam bootram.RAM1.INIT_35=256'h819951ff_51ff923f_983f81aa_81ff51ff_51ff9e3f_075381ff_0681d00a_0d74d00a; +defparam bootram.RAM1.INIT_36=256'h0651feed_3f7281ff_5252fef5_7081ff06_3f72882a_e151ff81_ff873f80_8c3fb251; +defparam bootram.RAM1.INIT_37=256'hfecf3fb0_ff065253_902a7081_fedb3f72_72982a51_51fee23f_e83f8181_3fb251fe; +defparam bootram.RAM1.INIT_38=256'hb03fa051_3f8051fe_a051feb5_51feba3f_febf3f8e_c43f8051_81a151fe_51feca3f; +defparam bootram.RAM1.INIT_39=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_ff398c08_843d0d04_51fea63f_feab3f80; +defparam bootram.RAM1.INIT_3A=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; +defparam bootram.RAM1.INIT_3B=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; +defparam bootram.RAM1.INIT_3C=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; +defparam bootram.RAM1.INIT_3D=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; +defparam bootram.RAM1.INIT_3E=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; +defparam bootram.RAM1.INIT_3F=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; +defparam bootram.RAM2.INIT_00=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; +defparam bootram.RAM2.INIT_01=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; +defparam bootram.RAM2.INIT_02=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM2.INIT_03=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; +defparam bootram.RAM2.INIT_04=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; +defparam bootram.RAM2.INIT_05=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; +defparam bootram.RAM2.INIT_06=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; +defparam bootram.RAM2.INIT_07=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; +defparam bootram.RAM2.INIT_08=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; +defparam bootram.RAM2.INIT_09=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; +defparam bootram.RAM2.INIT_0A=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; +defparam bootram.RAM2.INIT_0B=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; +defparam bootram.RAM2.INIT_0C=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; +defparam bootram.RAM2.INIT_0D=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; +defparam bootram.RAM2.INIT_0E=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; +defparam bootram.RAM2.INIT_0F=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; +defparam bootram.RAM2.INIT_10=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; +defparam bootram.RAM2.INIT_11=256'hae9c0854_3d0d800b_ff8339fd_ed387054_52718326_530cfc12_71708405_84055408; +defparam bootram.RAM2.INIT_12=256'h3f72b5f8_8008519b_51e6bc3f_aed05281_3fe3b13f_f80ce493_983873b5_5472812e; +defparam bootram.RAM2.INIT_13=256'hd40882c8_3d0d7bae_00ff39f7_0851843f_e6a53f80_d0528151_e39a3fae_0ce3fc3f; +defparam bootram.RAM2.INIT_14=256'h80e93880_59807424_712b5955_08ff0581_88188419_80d93881_5a77802e_11085a54; +defparam bootram.RAM2.INIT_15=256'h08535379_38781670_72802eb5_08770653_56818019_11880556_73822b78_7424b538; +defparam bootram.RAM2.INIT_16=256'hffad38ae_77085877_8025d638_57575473_79812c5a_fc17fc17_722dff14_51740853; +defparam bootram.RAM2.INIT_17=256'h57575473_79812c5a_fc17fc17_722dff14_3f740853_7951f8c0_1308a538_d40853bc; +defparam bootram.RAM2.INIT_18=256'hb5d80bfc_3fff3d0d_7951f894_0853722d_7251bc13_57ff9439_38d23980_8025ffa9; +defparam bootram.RAM2.INIT_19=256'h0d0404e3_f138833d_2e098106_525270ff_fc127008_9138702d_5270ff2e_05700852; +defparam bootram.RAM2.INIT_1A=256'h65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040_833f0400; +defparam bootram.RAM2.INIT_1B=256'h64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e; +defparam bootram.RAM2.INIT_1C=256'h756c7472_70657220_72207375_6f616465_6f6f746c_322b2062_55535250_4e4f4b00; +defparam bootram.RAM2.INIT_1D=256'h50322b20_20555352_74696e67_53746172_6e0a0000_6974696f_55206564_61205a50; +defparam bootram.RAM2.INIT_1E=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073; +defparam bootram.RAM2.INIT_1F=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; +defparam bootram.RAM2.INIT_20=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068; +defparam bootram.RAM2.INIT_21=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520; +defparam bootram.RAM2.INIT_22=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046; +defparam bootram.RAM2.INIT_23=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000; +defparam bootram.RAM2.INIT_24=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM2.INIT_25=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM2.INIT_26=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM2.INIT_27=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61; +defparam bootram.RAM2.INIT_28=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f; +defparam bootram.RAM2.INIT_29=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563; +defparam bootram.RAM2.INIT_2A=256'h6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00; +defparam bootram.RAM2.INIT_2B=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765; +defparam bootram.RAM2.INIT_2C=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67; +defparam bootram.RAM2.INIT_2D=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000; +defparam bootram.RAM2.INIT_2E=256'h2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75; +defparam bootram.RAM2.INIT_2F=256'h20202828_20202020_00202020_80700000_0b0b0b0b_01b200d9_05160364_14580a2c; +defparam bootram.RAM2.INIT_30=256'h10101010_10101010_20881010_20202020_20202020_20202020_20202020_28282820; +defparam bootram.RAM2.INIT_31=256'h01010101_41414141_10104141_10101010_04040410_04040404_10040404_10101010; +defparam bootram.RAM2.INIT_32=256'h02020202_42424242_10104242_10101010_01010101_01010101_01010101_01010101; +defparam bootram.RAM2.INIT_33=256'h00000000_00000000_20000000_10101010_02020202_02020202_02020202_02020202; +defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_37=256'h792e6578_64756d6d_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_38=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000; +defparam bootram.RAM2.INIT_39=256'hffffffff_000b0000_0018000f_ffff0031_05050400_01010100_00001ae0_00000000; +defparam bootram.RAM2.INIT_3A=256'h000019c0_00000000_00001758_000016f8_06820594_09c407d0_13880d05_00002710; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001a78_00001a1c; +defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00001704_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001; +defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_16=256'hffffffff_00000000_ffffffff_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/capture_ddrlvds.v b/fpga/usrp2/top/u2plus/capture_ddrlvds.v new file mode 100644 index 000000000..b9f53ff8c --- /dev/null +++ b/fpga/usrp2/top/u2plus/capture_ddrlvds.v @@ -0,0 +1,39 @@ + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk_regional; + wire ssclk_io; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(negedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/u2plus/u2plus.ucf new file mode 100755 index 000000000..5fbe55c26 --- /dev/null +++ b/fpga/usrp2/top/u2plus/u2plus.ucf @@ -0,0 +1,424 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +NET "ADC_clkout_p" LOC = "P1" ; +NET "ADC_clkout_n" LOC = "P2" ; +NET "ADCA_12_p" LOC = "Y1" ; +NET "ADCA_12_n" LOC = "Y2" ; +NET "ADCA_10_p" LOC = "W3" ; +NET "ADCA_10_n" LOC = "W4" ; +NET "ADCA_8_p" LOC = "T7" ; +NET "ADCA_8_n" LOC = "U6" ; +NET "ADCA_6_p" LOC = "U5" ; +NET "ADCA_6_n" LOC = "V5" ; +NET "ADCA_4_p" LOC = "T10" ; +NET "ADCA_4_n" LOC = "T9" ; +NET "ADCA_2_p" LOC = "V1" ; +NET "ADCA_2_n" LOC = "V2" ; +NET "ADCA_0_p" LOC = "R8" ; +NET "ADCA_0_n" LOC = "R7" ; +NET "ADCB_2_p" LOC = "U7" ; +NET "ADCB_2_n" LOC = "U8" ; +NET "ADCB_0_p" LOC = "AA2" ; +NET "ADCB_0_n" LOC = "AA3" ; +NET "ADCB_4_p" LOC = "AE1" ; +NET "ADCB_4_n" LOC = "AE2" ; +NET "ADCB_6_p" LOC = "W1" ; +NET "ADCB_6_n" LOC = "W2" ; +NET "ADCB_8_p" LOC = "U3" ; +NET "ADCB_8_n" LOC = "V4" ; +NET "ADCB_10_p" LOC = "J1" ; +NET "ADCB_10_n" LOC = "K1" ; +NET "ADCB_12_p" LOC = "J3" ; +NET "ADCB_12_n" LOC = "J2" ; + +## DAC +NET "DAC_LOCK" LOC = "P4" ; +NET "DACA<0>" LOC = "P8" ; +NET "DACA<1>" LOC = "P9" ; +NET "DACA<2>" LOC = "R5" ; +NET "DACA<3>" LOC = "R6" ; +NET "DACA<4>" LOC = "P7" ; +NET "DACA<5>" LOC = "P6" ; +NET "DACA<6>" LOC = "T3" ; +NET "DACA<7>" LOC = "T4" ; +NET "DACA<8>" LOC = "R3" ; +NET "DACA<9>" LOC = "R4" ; +NET "DACA<10>" LOC = "R2" ; +NET "DACA<11>" LOC = "N1" ; +NET "DACA<12>" LOC = "N2" ; +NET "DACA<13>" LOC = "N5" ; +NET "DACA<14>" LOC = "N4" ; +NET "DACA<15>" LOC = "M2" ; +NET "DACB<0>" LOC = "M5" ; +NET "DACB<1>" LOC = "M6" ; +NET "DACB<2>" LOC = "M4" ; +NET "DACB<3>" LOC = "M3" ; +NET "DACB<4>" LOC = "M8" ; +NET "DACB<5>" LOC = "M7" ; +NET "DACB<6>" LOC = "L4" ; +NET "DACB<7>" LOC = "L3" ; +NET "DACB<8>" LOC = "K3" ; +NET "DACB<9>" LOC = "K2" ; +NET "DACB<10>" LOC = "K5" ; +NET "DACB<11>" LOC = "K4" ; +NET "DACB<12>" LOC = "M10" ; +NET "DACB<13>" LOC = "M9" ; +NET "DACB<14>" LOC = "J5" ; +NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +NET "io_tx<15>" LOC = "K6" ; +NET "io_tx<14>" LOC = "L7" ; +NET "io_tx<13>" LOC = "H2" ; +NET "io_tx<12>" LOC = "H1" ; +NET "io_tx<11>" LOC = "L10" ; +NET "io_tx<10>" LOC = "L9" ; +NET "io_tx<9>" LOC = "G3" ; +NET "io_tx<8>" LOC = "F3" ; +NET "io_tx<7>" LOC = "K7" ; +NET "io_tx<6>" LOC = "J6" ; +NET "io_tx<5>" LOC = "E1" ; +NET "io_tx<4>" LOC = "F2" ; +NET "io_tx<3>" LOC = "J7" ; +NET "io_tx<2>" LOC = "H6" ; +NET "io_tx<1>" LOC = "F5" ; +NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +NET "io_rx<15>" LOC = "AD1" ; +NET "io_rx<14>" LOC = "AD2" ; +NET "io_rx<13>" LOC = "AC2" ; +NET "io_rx<12>" LOC = "AC3" ; +NET "io_rx<11>" LOC = "W7" ; +NET "io_rx<10>" LOC = "W6" ; +NET "io_rx<9>" LOC = "U9" ; +NET "io_rx<8>" LOC = "V8" ; +NET "io_rx<7>" LOC = "AB1" ; +NET "io_rx<6>" LOC = "AC1" ; +NET "io_rx<5>" LOC = "V7" ; +NET "io_rx<4>" LOC = "V6" ; +NET "io_rx<3>" LOC = "Y5" ; +NET "io_rx<2>" LOC = "R10" ; +NET "io_rx<1>" LOC = "R1" ; +NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +NET "FPGA_RESET" LOC = "K24" ; + +## Debug +NET "debug_clk<0>" LOC = "AA10" ; +NET "debug_clk<1>" LOC = "AD11" ; +NET "debug<0>" LOC = "AC19" ; +NET "debug<1>" LOC = "AF20" ; +NET "debug<2>" LOC = "AE20" ; +NET "debug<3>" LOC = "AC16" ; +NET "debug<4>" LOC = "AB16" ; +NET "debug<5>" LOC = "AF19" ; +NET "debug<6>" LOC = "AE19" ; +NET "debug<7>" LOC = "V15" ; +NET "debug<8>" LOC = "U15" ; +NET "debug<9>" LOC = "AE17" ; +NET "debug<10>" LOC = "AD17" ; +NET "debug<11>" LOC = "V14" ; +NET "debug<12>" LOC = "W15" ; +NET "debug<13>" LOC = "AC15" ; +NET "debug<14>" LOC = "AD14" ; +NET "debug<15>" LOC = "AC14" ; +NET "debug<16>" LOC = "AC11" ; +NET "debug<17>" LOC = "AB12" ; +NET "debug<18>" LOC = "AC12" ; +NET "debug<19>" LOC = "V13" ; +NET "debug<20>" LOC = "W13" ; +NET "debug<21>" LOC = "AE8" ; +NET "debug<22>" LOC = "AF8" ; +NET "debug<23>" LOC = "V12" ; +NET "debug<24>" LOC = "W12" ; +NET "debug<25>" LOC = "AB9" ; +NET "debug<26>" LOC = "AC9" ; +NET "debug<27>" LOC = "AC8" ; +NET "debug<28>" LOC = "AB7" ; +NET "debug<29>" LOC = "V11" ; +NET "debug<30>" LOC = "U11" ; +NET "debug<31>" LOC = "Y10" ; + +## UARTS +NET "TXD<3>" LOC = "AD20" ; +NET "TXD<2>" LOC = "AC20" ; +NET "TXD<1>" LOC = "AD19" ; +NET "RXD<3>" LOC = "AF17" ; +NET "RXD<2>" LOC = "AF15" ; +NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +NET "clk_status" LOC = "AD22" ; +NET "CLK_FUNC" LOC = "AC21" ; +NET "clk_sel<0>" LOC = "AE21" ; +NET "clk_sel<1>" LOC = "AD21" ; +NET "clk_en<1>" LOC = "AA17" ; +NET "clk_en<0>" LOC = "Y17" ; + +## I2C +NET "SDA" LOC = "V16" ; +NET "SCL" LOC = "U16" ; + +## Timing +NET "PPS_IN" LOC = "AB6" ; +NET "PPS2_IN" LOC = "AA20" ; + +## SPI +NET "SEN_CLK" LOC = "AA18" ; +NET "MOSI_CLK" LOC = "W17" ; +NET "SCLK_CLK" LOC = "V17" ; +NET "MISO_CLK" LOC = "AC10" ; + +NET "SEN_DAC" LOC = "AE7" ; +NET "SCLK_DAC" LOC = "AF5" ; +NET "MOSI_DAC" LOC = "AE6" ; +NET "MISO_DAC" LOC = "Y3" ; + +NET "SCLK_ADC" LOC = "B1" ; +NET "MOSI_ADC" LOC = "J8" ; +NET "SEN_ADC" LOC = "J9" ; + +NET "MOSI_TX_ADC" LOC = "V10" ; +NET "SEN_TX_ADC" LOC = "W10" ; +NET "SCLK_TX_ADC" LOC = "AC6" ; +NET "MISO_TX_ADC" LOC = "G1" ; + +NET "MOSI_TX_DAC" LOC = "AD6" ; +NET "SEN_TX_DAC" LOC = "AE4" ; +NET "SCLK_TX_DAC" LOC = "AF4" ; + +NET "SCLK_TX_DB" LOC = "AE3" ; +NET "MOSI_TX_DB" LOC = "AF3" ; +NET "SEN_TX_DB" LOC = "W9" ; +NET "MISO_TX_DB" LOC = "AA5" ; + +NET "MOSI_RX_ADC" LOC = "E3" ; +NET "SCLK_RX_ADC" LOC = "F4" ; +NET "SEN_RX_ADC" LOC = "D3" ; +NET "MISO_RX_ADC" LOC = "C1" ; + +NET "SCLK_RX_DAC" LOC = "E4" ; +NET "SEN_RX_DAC" LOC = "K9" ; +NET "MOSI_RX_DAC" LOC = "K8" ; + +NET "SCLK_RX_DB" LOC = "G6" ; +NET "MOSI_RX_DB" LOC = "H7" ; +NET "SEN_RX_DB" LOC = "B2" ; +NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +NET "CLK_TO_MAC" LOC = "P26" ; + +NET "GMII_TXD<7>" LOC = "G21" ; +NET "GMII_TXD<6>" LOC = "C26" ; +NET "GMII_TXD<5>" LOC = "C25" ; +NET "GMII_TXD<4>" LOC = "J21" ; +NET "GMII_TXD<3>" LOC = "H21" ; +NET "GMII_TXD<2>" LOC = "D25" ; +NET "GMII_TXD<1>" LOC = "D24" ; +NET "GMII_TXD<0>" LOC = "E26" ; +NET "GMII_TX_EN" LOC = "D26" ; +NET "GMII_TX_ER" LOC = "J19" ; +NET "GMII_GTX_CLK" LOC = "J20" ; +NET "GMII_TX_CLK" LOC = "P25" ; + +NET "GMII_RX_CLK" LOC = "P21" ; +NET "GMII_RXD<7>" LOC = "G22" ; +NET "GMII_RXD<6>" LOC = "K19" ; +NET "GMII_RXD<5>" LOC = "K18" ; +NET "GMII_RXD<4>" LOC = "E24" ; +NET "GMII_RXD<3>" LOC = "F23" ; +NET "GMII_RXD<2>" LOC = "L18" ; +NET "GMII_RXD<1>" LOC = "L17" ; +NET "GMII_RXD<0>" LOC = "F25" ; +NET "GMII_RX_DV" LOC = "F24" ; +NET "GMII_RX_ER" LOC = "L20" ; +NET "GMII_CRS" LOC = "K20" ; +NET "GMII_COL" LOC = "G23" ; + +NET "PHY_INTn" LOC = "L22" ; +NET "MDIO" LOC = "K21" ; +NET "MDC" LOC = "J23" ; +NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; + +## MIMO Interface +NET "exp_time_out_p" LOC = "Y14" ; +NET "exp_time_out_n" LOC = "AA14" ; +NET "exp_time_in_p" LOC = "N18" ; +NET "exp_time_in_n" LOC = "N17" ; +NET "exp_user_out_p" LOC = "AF14" ; +NET "exp_user_out_n" LOC = "AE14" ; +NET "exp_user_in_p" LOC = "L24" ; +NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +NET "ser_enable" LOC = "R20" ; +NET "ser_prbsen" LOC = "U23" ; +NET "ser_loopen" LOC = "R19" ; +NET "ser_rx_en" LOC = "Y21" ; +NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +NET "ser_t<15>" LOC = "V23" ; +NET "ser_t<14>" LOC = "U22" ; +NET "ser_t<13>" LOC = "V24" ; +NET "ser_t<12>" LOC = "V25" ; +NET "ser_t<11>" LOC = "W23" ; +NET "ser_t<10>" LOC = "V22" ; +NET "ser_t<9>" LOC = "T18" ; +NET "ser_t<8>" LOC = "T17" ; +NET "ser_t<7>" LOC = "Y24" ; +NET "ser_t<6>" LOC = "Y25" ; +NET "ser_t<5>" LOC = "U21" ; +NET "ser_t<4>" LOC = "T20" ; +NET "ser_t<3>" LOC = "Y22" ; +NET "ser_t<2>" LOC = "Y23" ; +NET "ser_t<1>" LOC = "U19" ; +NET "ser_t<0>" LOC = "U18" ; +NET "ser_tkmsb" LOC = "AA24" ; +NET "ser_tklsb" LOC = "AA25" ; +NET "ser_rx_clk" LOC = "P18" ; +NET "ser_r<15>" LOC = "V21" ; +NET "ser_r<14>" LOC = "U20" ; +NET "ser_r<13>" LOC = "AA22" ; +NET "ser_r<12>" LOC = "AA23" ; +NET "ser_r<11>" LOC = "V18" ; +NET "ser_r<10>" LOC = "V19" ; +NET "ser_r<9>" LOC = "AB23" ; +NET "ser_r<8>" LOC = "AC26" ; +NET "ser_r<7>" LOC = "AB26" ; +NET "ser_r<6>" LOC = "AD26" ; +NET "ser_r<5>" LOC = "AC25" ; +NET "ser_r<4>" LOC = "W20" ; +NET "ser_r<3>" LOC = "W21" ; +NET "ser_r<2>" LOC = "AC23" ; +NET "ser_r<1>" LOC = "AC24" ; +NET "ser_r<0>" LOC = "AE26" ; +NET "ser_rkmsb" LOC = "AD25" ; +NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; + +## SPI Flash +NET "flash_miso" LOC = "AF24" ; +NET "flash_clk" LOC = "AE24" ; +NET "flash_mosi" LOC = "AB15" ; +NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +#NET "PROG_B" LOC = "A2" ; +#NET "PUDC_B" LOC = "G8" ; +#NET "DONE" LOC = "AB21" ; +#NET "INIT_B" LOC = "AA15" ; + + +#NET "unnamed_net19" LOC = "AE9" ; # VS1 +#NET "unnamed_net18" LOC = "AF9" ; # VS0 +#NET "unnamed_net17" LOC = "AA12" ; # VS2 +#NET "unnamed_net16" LOC = "Y7" ; # M2 +#NET "unnamed_net15" LOC = "AC4" ; # M1 +#NET "unnamed_net14" LOC = "AD4" ; # M0 +#NET "unnamed_net13" LOC = "D4" ; # TMS +#NET "unnamed_net12" LOC = "E23" ; # TDO +#NET "unnamed_net11" LOC = "G7" ; # TDI +#NET "unnamed_net10" LOC = "A25" ; # TCK +#NET "unnamed_net20" LOC = "V20" ; # SUSPEND + + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; + +#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; + + diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v new file mode 100644 index 000000000..c0140e989 --- /dev/null +++ b/fpga/usrp2/top/u2plus/u2plus.v @@ -0,0 +1,450 @@ +`timescale 1ns / 1ps +//`define DCM_FOR_RAMCLK +////////////////////////////////////////////////////////////////////////////////// + +module u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + input ADC_clkout_p, input ADC_clkout_n, + input ADCA_12_p, input ADCA_12_n, + input ADCA_10_p, input ADCA_10_n, + input ADCA_8_p, input ADCA_8_n, + input ADCA_6_p, input ADCA_6_n, + input ADCA_4_p, input ADCA_4_n, + input ADCA_2_p, input ADCA_2_n, + input ADCA_0_p, input ADCA_0_n, + input ADCB_12_p, input ADCB_12_n, + input ADCB_10_p, input ADCB_10_n, + input ADCB_8_p, input ADCB_8_n, + input ADCB_6_p, input ADCB_6_n, + input ADCB_4_p, input ADCB_4_n, + input ADCB_2_p, input ADCB_2_n, + input ADCB_0_p, input ADCB_0_n, + + // DAC + output reg [15:0] DACA, + output reg [15:0] DACB, + input DAC_LOCK, // unused for now + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + input FPGA_RESET, + output [1:0] debug_clk, + output [31:0] debug, + output [3:1] TXD, input [3:1] RXD, // UARTs + //input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input CLK_FUNC, // FIXME is an input to control the 9510 + input clk_status, + + inout SCL, inout SDA, // I2C + + // PPS + input PPS_IN, input PPS2_IN, + + // SPI + output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, + output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, + output SEN_ADC, output SCLK_ADC, output MOSI_ADC, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, + output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, + output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, + output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, + + // GigE PHY + input CLK_TO_MAC, + + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + input GMII_RX_CLK, + input [7:0] GMII_RXD, + input GMII_RX_DV, + input GMII_RX_ER, + input GMII_COL, + input GMII_CRS, + + input PHY_INTn, // open drain + inout MDIO, + output MDC, + output PHY_RESETn, + output ETH_LED, + +// input POR, + + // Expansion + input exp_time_in_p, input exp_time_in_n, // Diff + output exp_time_out_p, output exp_time_out_n, // Diff + input exp_user_in_p, input exp_user_in_n, // Diff + output exp_user_out_p, output exp_user_out_n, // Diff + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // SRAM + inout [35:0] RAM_D, + output [20:0] RAM_A, + output [3:0] RAM_BWn, + output RAM_ZZ, + output RAM_LDn, + output RAM_OEn, + output RAM_WEn, + output RAM_CENn, + output RAM_CLK, + + // SPI Flash + output flash_cs, + output flash_clk, + output flash_mosi, + input flash_miso + ); + + wire CLK_TO_MAC_int, CLK_TO_MAC_int2; + IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); + BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_in; + IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); + defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_out; + OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); + defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + // ADC A is inverted on the schematic to facilitate a clean layout + // We account for that here by inverting it +`ifdef LVDS + wire [13:0] adc_a, adc_a_inv, adc_b; + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a_inv,adc_b})); + assign adc_a = ~adc_a_inv; +`else + reg [13:0] adc_a, adc_b; + always @(posedge dsp_clk) + begin + adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; + adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; + end +`endif // !`ifdef LVDS + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(clk270_100), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. + BUFG clk270_100_buf_i1 (.I(clk270_100), + .O(clk270_100_buf)); + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk270_100_buf), + .C1(~clk270_100_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + + + // + // Instantiate IO for Bidirectional bus to SRAM + // + wire [35:0] RAM_D_pi; + wire [35:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + generate + for (i=0;i<36;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; + + u2plus_core u2p_c(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (CLK_TO_MAC_int2), + .pps_in (PPS_IN), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .adc_a (adc_a[13:0]), + .adc_ovf_a (1'b0), + .adc_on_a (), + .adc_oe_a (), + .adc_b (adc_b[13:0]), + .adc_ovf_b (1'b0), + .adc_on_b (), + .adc_oe_b (), + .dac_a (dac_a_int[15:0]), + .dac_b (dac_b_int[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (SEN_CLK), + .sen_dac (SEN_DAC), + .sen_adc (SEN_ADC), + .sen_tx_db (SEN_TX_DB), + .sen_tx_adc (SEN_TX_ADC), + .sen_tx_dac (SEN_TX_DAC), + .sen_rx_db (SEN_RX_DB), + .sen_rx_adc (SEN_RX_ADC), + .sen_rx_dac (SEN_RX_DAC), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_po (RAM_D_po), + .RAM_D_pi (RAM_D_pi), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (TXD[3:1]), + .uart_rx_i ({1'b1,RXD[3:1]}), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2), + .button (FPGA_RESET), + .spiflash_cs (flash_cs), + .spiflash_clk (flash_clk), + .spiflash_miso (flash_miso), + .spiflash_mosi (flash_mosi) + ); + + // Drive low so that RAM does not sleep. + assign RAM_ZZ = 0; + // Byte Writes are qualified by the global write enable + // Always do 36bit operations to extram. + assign RAM_BWn = 4'b0000; + +endmodule // u2plus diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v new file mode 100644 index 000000000..c152f083e --- /dev/null +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -0,0 +1,738 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2plus_core + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_time_in, + output exp_time_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_adc, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [35:0] RAM_D_pi, + output [35:0] RAM_D_po, + output RAM_D_poe, + output [20:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output [3:0] uart_tx_o, + input [3:0] uart_rx_i, + output [3:0] uart_baud_o, + input sim_mode, + input [3:0] clock_divider, + input button, + + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi + ); + + localparam SR_BUF_POOL = 64; // router + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire wb_rst, dsp_rst; + + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun; + wire [3:0] uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time; + wire run_rx, run_tx; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // 16K-20K, Buffer Pool + .s2_addr(8'b0110_0000),.s2_mask(8'b1111_1111), // SPI + .s3_addr(8'b0110_0001),.s3_mask(8'b1111_1111), // I2C + .s4_addr(8'b0110_0010),.s4_mask(8'b1111_1111), // GPIO + .s5_addr(8'b0110_0011),.s5_mask(8'b1111_1111), // Readback + .s6_addr(8'b0110_0100),.s6_mask(8'b1111_1111), // Ethernet MAC + .s7_addr(8'b0101_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b0110_0101),.s8_mask(8'b1111_1111), // PIC + .s9_addr(8'b0110_0110),.s9_mask(8'b1111_1111), // Unused + .sa_addr(8'b0110_0111),.sa_mask(8'b1111_1111), // UART + .sb_addr(8'b0110_1000),.sb_mask(8'b1111_1111), // ATR + .sc_addr(8'b0110_1001),.sc_mask(8'b1111_1111), // Unused + .sd_addr(8'b0110_1010),.sd_mask(8'b1111_1111), // ICAP + .se_addr(8'b0110_1011),.se_mask(8'b1111_1111), // SPI Flash + .sf_addr(8'b1000_0000),.sf_mask(8'b1100_0000), // 32-48K, Main RAM + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + reg cpu_rst; + wire cpu_enb = ~cpu_rst; + wire [aw-1:0] cpu_adr; + wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)? + 16'hfff8 : //top of 8K boot ram re-purposed at 56K + 16'h1ff8 ; //top of 8K boot ram + + //When the main program runs, it will try to access system ram at 0. + //This logic re-maps the cpu address to force select the system ram. + assign m0_adr = + (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_WAIT)? cpu_adr : ( //in bootloader + (cpu_adr[15:14] == 2'b00)? {2'b10, cpu_adr[13:0]} : ( //map 0-16 to 32-48 (main ram) + (cpu_adr[15:13] == 3'b111)? {3'b000, cpu_adr[12:0]} : ( //map 56-64 to 0-8 (boot ram) + cpu_adr))); //otherwise + + always @(posedge wb_clk) + if(wb_rst) begin + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; + cpu_rst <= 1'b1; + end + else begin + case(cpu_bldr_ctrl_state) + + CPU_BLDR_CTRL_WAIT: begin + cpu_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; + cpu_rst <= 1'b1; + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + cpu_rst <= 1'b0; + end + + endcase //cpu_bldr_ctrl_state + end + + // ///////////////////////////////////////////////////////////////////////// + // Processor + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst | cpu_rst), .enb(cpu_enb), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .stack_start(cpu_sp_init), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone + // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone + // I-port connects directly to processor + + bootram bootram(.clk(wb_clk), .reset(wb_rst), + .if_adr(13'b0), .if_data(), + .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + +////blinkenlights v0.1 +//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; +//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; + +`include "bootloader.rmi" + + ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio({io_tx,io_rx}) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd4; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); + + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + setting_reg #(.my_addr(5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(bldr_done),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; + + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + + setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + + assign irq= {{8'b0}, + {uart_tx_int[3:0], uart_rx_int[3:0]}, + {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // ICAP for reprogramming the FPGA, Slave #13 (D) + + s3a_icap_wb s3a_icap_wb + (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), + .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI for Flash -- Slave #14 (E) + spi_top flash_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), + .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), + .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), + .ss_pad_o(spiflash_cs), + .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + wire [31:0] vrc_debug; + wire clear_rx; + + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); + + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + assign RAM_A[20:18] = 3'b0; + + ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(dsp_clk), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A[17:0]), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core |