diff options
Diffstat (limited to 'fpga/usrp2/top')
| -rw-r--r-- | fpga/usrp2/top/B100/timing.ucf | 7 | ||||
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/E1x0.v | 18 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/Makefile.E110 | 1 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/timing.ucf | 4 | ||||
| -rw-r--r-- | fpga/usrp2/top/Makefile.common | 2 |
6 files changed, 24 insertions, 10 deletions
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf index c4404e1d0..7b212a9a6 100644 --- a/fpga/usrp2/top/B100/timing.ucf +++ b/fpga/usrp2/top/B100/timing.ucf @@ -15,5 +15,10 @@ INST "GPIF_SLOE" TNM = gpif_net_out; INST "GPIF_SLRD" TNM = gpif_net_out; INST "GPIF_PKTEND" TNM = gpif_net_out; -TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING; +TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "IFCLK" RISING; TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING; + +TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; + +NET PPS_IN TIG; +NET debug_led* TIG; diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 423282153..302565101 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -71,7 +71,7 @@ module u1plus_core localparam SR_GPIO = 224; // 5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd11, 16'd1}; //major, minor + localparam compat_num = {16'd11, 16'd2}; //major, minor //assign run signals used for ATR logic wire [NUM_RX_DSPS-1:0] run_rx_n; diff --git a/fpga/usrp2/top/E1x0/E1x0.v b/fpga/usrp2/top/E1x0/E1x0.v index 8efb056e9..44129ce92 100644 --- a/fpga/usrp2/top/E1x0/E1x0.v +++ b/fpga/usrp2/top/E1x0/E1x0.v @@ -59,10 +59,20 @@ module E1x0 wire clk_fpga; wire reset; - reg async_reset; - always @(negedge EM_CLK) begin - async_reset <= ~EM_NCS6 && ~EM_NWE && (EM_A[9:2] == 8'hff) && EM_D[0]; - end + reg por_rst; + reg [7:0] por_counter = 8'h0; + + always @(posedge clk_fpga) + if (por_counter != 8'h55) + begin + por_counter <= por_counter + 8'h1; + por_rst <= 1'b1; + end + else por_rst <= 1'b0; + + wire async_reset; + cross_clock_reader #(.WIDTH(1)) read_gpio_reset + (.clk(clk_fpga), .rst(por_rst), .in(cgen_sen_b & ~cgen_sclk), .out(async_reset)); IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110 index e5be8d2fa..c2d3e39e6 100644 --- a/fpga/usrp2/top/E1x0/Makefile.E110 +++ b/fpga/usrp2/top/E1x0/Makefile.E110 @@ -50,7 +50,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \ TOP_SRCS = \ ../B100/u1plus_core.v \ E1x0.v \ -E1x0.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf index 7d3d9e090..1483c2a05 100644 --- a/fpga/usrp2/top/E1x0/timing.ucf +++ b/fpga/usrp2/top/E1x0/timing.ucf @@ -14,8 +14,8 @@ INST "EM_NCS6" TNM = gpmc_net; INST "EM_NWE" TNM = gpmc_net; INST "EM_NOE" TNM = gpmc_net; -TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 12 ns BEFORE "EM_CLK" FALLING; -TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read +TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 10 ns BEFORE "EM_CLK" FALLING; +#TIMEGRP "gpmc_net_out" OFFSET = OUT 13 ns AFTER "EM_CLK" RISING; //2 clock cyc per read #constrain interrupt lines NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common index 3b71e7b13..bd999f007 100644 --- a/fpga/usrp2/top/Makefile.common +++ b/fpga/usrp2/top/Makefile.common @@ -55,7 +55,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) $(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) @echo $@ - $(ISE_HELPER) "Generate Programming File" + $(ISE_HELPER) "Generate Programming File" 2>&1 | tee $(BUILD_DIR)/build.log touch $@ $(MCS_FILE): $(BIN_FILE) |