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-rw-r--r--fpga/usrp2/top/u2_core/u2_core.v30
-rw-r--r--fpga/usrp2/top/u2_rev1/.gitignore52
-rw-r--r--fpga/usrp2/top/u2_rev1/Makefile129
-rw-r--r--fpga/usrp2/top/u2_rev1/u2_fpga.isebin477678 -> 0 bytes
-rwxr-xr-xfpga/usrp2/top/u2_rev1/u2_fpga.ucf341
-rw-r--r--fpga/usrp2/top/u2_rev1/u2_fpga_top.prj102
-rw-r--r--fpga/usrp2/top/u2_rev1/u2_fpga_top.v393
-rw-r--r--fpga/usrp2/top/u2_rev2/.gitignore57
-rw-r--r--fpga/usrp2/top/u2_rev2/Makefile248
-rw-r--r--fpga/usrp2/top/u2_rev2/u2_rev2.ucf337
-rw-r--r--fpga/usrp2/top/u2_rev2/u2_rev2.v417
-rw-r--r--fpga/usrp2/top/u2_rev3/Makefile3
12 files changed, 20 insertions, 2089 deletions
diff --git a/fpga/usrp2/top/u2_core/u2_core.v b/fpga/usrp2/top/u2_core/u2_core.v
index cd0199005..b57e4f127 100644
--- a/fpga/usrp2/top/u2_core/u2_core.v
+++ b/fpga/usrp2/top/u2_core/u2_core.v
@@ -154,9 +154,9 @@ module u2_core
localparam SERDES_TX_FIFOSIZE = 9;
localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo?
- wire [7:0] set_addr;
- wire [31:0] set_data;
- wire set_stb;
+ wire [7:0] set_addr, set_addr_dsp;
+ wire [31:0] set_data, set_data_dsp;
+ wire set_stb, set_stb_dsp;
wire ram_loader_done;
wire ram_loader_rst, wb_rst, dsp_rst;
@@ -359,7 +359,7 @@ module u2_core
.wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
.stream_clk(dsp_clk), .stream_rst(dsp_rst),
- .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
.status(status),.sys_int_o(buffer_int),
.s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
@@ -454,7 +454,7 @@ module u2_core
udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
.rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
.tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
.rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy),
@@ -476,10 +476,14 @@ module u2_core
settings_bus settings_bus
(.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
.wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
- .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+ .strobe(set_stb),.addr(set_addr),.data(set_data));
assign s7_dat_i = 32'd0;
+ settings_bus_crossclock settings_bus_crossclock
+ (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
+ .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+
// Output control lines
wire [7:0] clock_outs, serdes_outs, adc_outs;
assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
@@ -600,7 +604,7 @@ module u2_core
dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
(.clk(dsp_clk),.rst(dsp_rst),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
.debug(debug_rx_dsp) );
@@ -609,7 +613,7 @@ module u2_core
vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy),
@@ -619,7 +623,7 @@ module u2_core
vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
.data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
.fifo_occupied(), .fifo_full(), .fifo_empty(),
@@ -646,14 +650,14 @@ module u2_core
vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
.sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
.debug(debug_vtd) );
vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time),.underrun(underrun),
.sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
@@ -663,7 +667,7 @@ module u2_core
dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
(.clk(dsp_clk),.rst(dsp_rst),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.dac_a(dac_a),.dac_b(dac_b),
.debug(debug_tx_dsp) );
@@ -720,7 +724,7 @@ module u2_core
// VITA Timing
time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
- (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
.pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
// /////////////////////////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp2/top/u2_rev1/.gitignore b/fpga/usrp2/top/u2_rev1/.gitignore
deleted file mode 100644
index de5b50277..000000000
--- a/fpga/usrp2/top/u2_rev1/.gitignore
+++ /dev/null
@@ -1,52 +0,0 @@
-/templates
-/netgen
-/_ngo
-/_xmsgs
-/_pace.ucf
-/*.cmd
-/*.ibs
-/*.lfp
-/*.mfp
-/*.bit
-/*.bin
-/*.stx
-/*.par
-/*.unroutes
-/*.ntrc_log
-/*.ngr
-/*.mrp
-/*.html
-/*.lso
-/*.twr
-/*.bld
-/*.ncd
-/*.txt
-/*.cmd_log
-/*.drc
-/*.map
-/*.twr
-/*.xml
-/*.syr
-/*.ngm
-/*.xst
-/*.csv
-/*.html
-/*.lock
-/*.ncd
-/*.twx
-/*.ise_ISE_Backup
-/*.xml
-/*.ut
-/*.xpi
-/*.ngd
-/*.ncd
-/*.pad
-/*.bgn
-/*.ngc
-/*.pcf
-/*.ngd
-/xst
-/*.log
-/*.rpt
-/*.cel
-/*.restore
diff --git a/fpga/usrp2/top/u2_rev1/Makefile b/fpga/usrp2/top/u2_rev1/Makefile
deleted file mode 100644
index b3245d883..000000000
--- a/fpga/usrp2/top/u2_rev1/Makefile
+++ /dev/null
@@ -1,129 +0,0 @@
-FILENAME=u2_fpga_top
-PARTNUM=xc3s1500-5fg456
-
-all: project command xst ngd ncd ncd2 bit
-
-xst:
- xst -ifn ${FILENAME}.cmd -ofn xst.log
-
-ngd:
- ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
-
-ncd:
- rm -rf ${FILENAME}.ncd
- map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf
-
-# Place and route ncd file into new ncd file
-ncd2:
- par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
-
-bit:
- bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
-
-clean:
- @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
- *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
- *.blc *.bld *.ise_ISE_Backup *~ \
- *.pad *.ngm *.ngd *.par *.pcf *.unroutes \
- *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \
- *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
- output.dat coregen.log *.ngo *.log ${FILENAME}.map \
- ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
-
-command:
- rm -rf ${FILENAME}.cmd
- @echo "identification" >> ${FILENAME}.cmd
- @echo "status" >> ${FILENAME}.cmd
- @echo "time short" >> ${FILENAME}.cmd
- @echo "memory on" >> ${FILENAME}.cmd
- @echo "run " >> ${FILENAME}.cmd
- @echo "-top ${FILENAME}" >> ${FILENAME}.cmd
- @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
- @echo "-ifmt Verilog " >> ${FILENAME}.cmd
- @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd
- @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd
- @echo "-bufg 6" >> ${FILENAME}.cmd
- @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd
-
-project:
- rm -f ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj
- @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj
- @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj
- @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" ' >> ${FILENAME}.prj
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga.ise b/fpga/usrp2/top/u2_rev1/u2_fpga.ise
deleted file mode 100644
index f90caf024..000000000
--- a/fpga/usrp2/top/u2_rev1/u2_fpga.ise
+++ /dev/null
Binary files differ
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga.ucf b/fpga/usrp2/top/u2_rev1/u2_fpga.ucf
deleted file mode 100755
index 5d2124819..000000000
--- a/fpga/usrp2/top/u2_rev1/u2_fpga.ucf
+++ /dev/null
@@ -1,341 +0,0 @@
-NET "adc_a[0]" LOC = "A14" ;
-NET "adc_a[10]" LOC = "D20" ;
-NET "adc_a[11]" LOC = "D19" ;
-NET "adc_a[12]" LOC = "D21" ;
-NET "adc_a[13]" LOC = "E18" ;
-NET "adc_a[1]" LOC = "B14" ;
-NET "adc_a[2]" LOC = "C13" ;
-NET "adc_a[3]" LOC = "D13" ;
-NET "adc_a[4]" LOC = "A13" ;
-NET "adc_a[5]" LOC = "B13" ;
-NET "adc_a[6]" LOC = "E12" ;
-NET "adc_a[7]" LOC = "C22" ;
-NET "adc_a[8]" LOC = "C20" ;
-NET "adc_a[9]" LOC = "C21" ;
-NET "adc_b[0]" LOC = "A12" ;
-NET "adc_b[10]" LOC = "D18" ;
-NET "adc_b[11]" LOC = "B18" ;
-NET "adc_b[12]" LOC = "D17" ;
-NET "adc_b[13]" LOC = "E17" ;
-NET "adc_b[1]" LOC = "E16" ;
-NET "adc_b[2]" LOC = "F12" ;
-NET "adc_b[3]" LOC = "F13" ;
-NET "adc_b[4]" LOC = "F16" ;
-NET "adc_b[5]" LOC = "F17" ;
-NET "adc_b[6]" LOC = "C19" ;
-NET "adc_b[7]" LOC = "B20" ;
-NET "adc_b[8]" LOC = "B19" ;
-NET "adc_b[9]" LOC = "C18" ;
-NET "clk_en[0]" LOC = "C4" ;
-NET "clk_en[1]" LOC = "D1" ;
-NET "clk_sel[0]" LOC = "C3" ;
-NET "clk_sel[1]" LOC = "C2" ;
-NET "dac_a[0]" LOC = "A5" ;
-NET "dac_a[10]" LOC = "L2" ;
-NET "dac_a[11]" LOC = "L4" ;
-NET "dac_a[12]" LOC = "L3" ;
-NET "dac_a[13]" LOC = "L6" ;
-NET "dac_a[14]" LOC = "L5" ;
-NET "dac_a[15]" LOC = "K2" ;
-NET "dac_a[1]" LOC = "B5" ;
-NET "dac_a[2]" LOC = "C5" ;
-NET "dac_a[3]" LOC = "D5" ;
-NET "dac_a[4]" LOC = "A4" ;
-NET "dac_a[5]" LOC = "B4" ;
-NET "dac_a[6]" LOC = "F6" ;
-NET "dac_a[7]" LOC = "D10" ;
-NET "dac_a[8]" LOC = "D9" ;
-NET "dac_a[9]" LOC = "A10" ;
-NET "dac_b[0]" LOC = "D11" ;
-NET "dac_b[10]" LOC = "F9" ;
-NET "dac_b[11]" LOC = "A8" ;
-NET "dac_b[12]" LOC = "B8" ;
-NET "dac_b[13]" LOC = "D7" ;
-NET "dac_b[14]" LOC = "E7" ;
-NET "dac_b[15]" LOC = "B6" ;
-NET "dac_b[1]" LOC = "E11" ;
-NET "dac_b[2]" LOC = "F11" ;
-NET "dac_b[3]" LOC = "B10" ;
-NET "dac_b[4]" LOC = "C10" ;
-NET "dac_b[5]" LOC = "E10" ;
-NET "dac_b[6]" LOC = "F10" ;
-NET "dac_b[7]" LOC = "A9" ;
-NET "dac_b[8]" LOC = "B9" ;
-NET "dac_b[9]" LOC = "E9" ;
-NET "debug[0]" LOC = "N5" ;
-NET "debug[10]" LOC = "R4" ;
-NET "debug[11]" LOC = "T3" ;
-NET "debug[12]" LOC = "U3" ;
-NET "debug[13]" LOC = "M2" ;
-NET "debug[14]" LOC = "M3" ;
-NET "debug[15]" LOC = "M4" ;
-NET "debug[16]" LOC = "M5" ;
-NET "debug[17]" LOC = "M6" ;
-NET "debug[18]" LOC = "N1" ;
-NET "debug[19]" LOC = "N2" ;
-NET "debug[1]" LOC = "N6" ;
-NET "debug[20]" LOC = "N3" ;
-NET "debug[21]" LOC = "T1" ;
-NET "debug[22]" LOC = "T2" ;
-NET "debug[23]" LOC = "U2" ;
-NET "debug[24]" LOC = "T4" ;
-NET "debug[25]" LOC = "U4" ;
-NET "debug[26]" LOC = "T5" ;
-NET "debug[27]" LOC = "T6" ;
-NET "debug[28]" LOC = "U5" ;
-NET "debug[29]" LOC = "V5" ;
-NET "debug[2]" LOC = "P1" ;
-NET "debug[30]" LOC = "W2" ;
-NET "debug[31]" LOC = "W3" ;
-NET "debug[3]" LOC = "P2" ;
-NET "debug[4]" LOC = "P4" ;
-NET "debug[5]" LOC = "P5" ;
-NET "debug[6]" LOC = "R1" ;
-NET "debug[7]" LOC = "R2" ;
-NET "debug[8]" LOC = "P6" ;
-NET "debug[9]" LOC = "R5" ;
-NET "debug_clk[0]" LOC = "N4" ;
-NET "debug_clk[1]" LOC = "M1" ;
-NET "GMII_RXD[0]" LOC = "AA15" ;
-NET "GMII_RXD[1]" LOC = "AB15" ;
-NET "GMII_RXD[2]" LOC = "U14" ;
-NET "GMII_RXD[3]" LOC = "V14" ;
-NET "GMII_RXD[4]" LOC = "U13" ;
-NET "GMII_RXD[5]" LOC = "V13" ;
-NET "GMII_RXD[6]" LOC = "Y13" ;
-NET "GMII_RXD[7]" LOC = "AA13" ;
-NET "GMII_TXD[0]" LOC = "W14" ;
-NET "GMII_TXD[1]" LOC = "AA20" ;
-NET "GMII_TXD[2]" LOC = "AB20" ;
-NET "GMII_TXD[3]" LOC = "Y18" ;
-NET "GMII_TXD[4]" LOC = "AA18" ;
-NET "GMII_TXD[5]" LOC = "AB18" ;
-NET "GMII_TXD[6]" LOC = "V17" ;
-NET "GMII_TXD[7]" LOC = "W17" ;
-NET "io_rx[0]" LOC = "L21" ;
-NET "io_rx[10]" LOC = "F21" ;
-NET "io_rx[11]" LOC = "F20" ;
-NET "io_rx[12]" LOC = "G19" ;
-NET "io_rx[13]" LOC = "G18" ;
-NET "io_rx[14]" LOC = "G17" ;
-NET "io_rx[15]" LOC = "E22" ;
-NET "io_rx[1]" LOC = "L20" ;
-NET "io_rx[2]" LOC = "L19" ;
-NET "io_rx[3]" LOC = "L18" ;
-NET "io_rx[4]" LOC = "L17" ;
-NET "io_rx[5]" LOC = "K22" ;
-NET "io_rx[6]" LOC = "K21" ;
-NET "io_rx[7]" LOC = "K20" ;
-NET "io_rx[8]" LOC = "G22" ;
-NET "io_rx[9]" LOC = "G21" ;
-NET "io_tx[0]" LOC = "K4" ;
-NET "io_tx[10]" LOC = "E1" ;
-NET "io_tx[11]" LOC = "E3" ;
-NET "io_tx[12]" LOC = "F4" ;
-NET "io_tx[13]" LOC = "D2" ;
-NET "io_tx[14]" LOC = "D4" ;
-NET "io_tx[15]" LOC = "E4" ;
-NET "io_tx[1]" LOC = "K3" ;
-NET "io_tx[2]" LOC = "G1" ;
-NET "io_tx[3]" LOC = "G5" ;
-NET "io_tx[4]" LOC = "H5" ;
-NET "io_tx[5]" LOC = "F3" ;
-NET "io_tx[6]" LOC = "F2" ;
-NET "io_tx[7]" LOC = "F5" ;
-NET "io_tx[8]" LOC = "G6" ;
-NET "io_tx[9]" LOC = "E2" ;
-NET "RAM_A[0]" LOC = "N22" ;
-NET "RAM_A[10]" LOC = "P18" ;
-NET "RAM_A[11]" LOC = "R19" ;
-NET "RAM_A[12]" LOC = "P19" ;
-NET "RAM_A[13]" LOC = "R21" ;
-NET "RAM_A[14]" LOC = "R22" ;
-NET "RAM_A[15]" LOC = "T19" ;
-NET "RAM_A[16]" LOC = "T20" ;
-NET "RAM_A[17]" LOC = "U20" ;
-NET "RAM_A[18]" LOC = "W19" ;
-NET "RAM_A[1]" LOC = "N20" ;
-NET "RAM_A[2]" LOC = "T21" ;
-NET "RAM_A[3]" LOC = "M22" ;
-NET "RAM_A[4]" LOC = "N19" ;
-NET "RAM_A[5]" LOC = "N17" ;
-NET "RAM_A[6]" LOC = "N18" ;
-NET "RAM_A[7]" LOC = "P21" ;
-NET "RAM_A[8]" LOC = "P22" ;
-NET "RAM_A[9]" LOC = "P17" ;
-NET "RAM_D[0]" LOC = "Y21" ;
-NET "RAM_D[10]" LOC = "V22" ;
-NET "RAM_D[11]" LOC = "V21" ;
-NET "RAM_D[12]" LOC = "T17" ;
-NET "RAM_D[13]" LOC = "U18" ;
-NET "RAM_D[14]" LOC = "U21" ;
-NET "RAM_D[15]" LOC = "R18" ;
-NET "RAM_D[16]" LOC = "T18" ;
-NET "RAM_D[17]" LOC = "T22" ;
-NET "RAM_D[1]" LOC = "Y20" ;
-NET "RAM_D[2]" LOC = "Y19" ;
-NET "RAM_D[3]" LOC = "W22" ;
-NET "RAM_D[4]" LOC = "Y22" ;
-NET "RAM_D[5]" LOC = "V19" ;
-NET "RAM_D[6]" LOC = "W21" ;
-NET "RAM_D[7]" LOC = "W20" ;
-NET "RAM_D[8]" LOC = "U19" ;
-NET "RAM_D[9]" LOC = "V20" ;
-NET "ser_r[0]" LOC = "AB10" ;
-NET "ser_r[10]" LOC = "W10" ;
-NET "ser_r[11]" LOC = "Y1" ;
-NET "ser_r[12]" LOC = "Y3" ;
-NET "ser_r[13]" LOC = "Y2" ;
-NET "ser_r[14]" LOC = "W4" ;
-NET "ser_r[15]" LOC = "W1" ;
-NET "ser_r[1]" LOC = "AA10" ;
-NET "ser_r[2]" LOC = "U9" ;
-NET "ser_r[3]" LOC = "U6" ;
-NET "ser_r[4]" LOC = "AB11" ;
-NET "ser_r[5]" LOC = "Y7" ;
-NET "ser_r[6]" LOC = "W7" ;
-NET "ser_r[7]" LOC = "AB7" ;
-NET "ser_r[8]" LOC = "AA7" ;
-NET "ser_r[9]" LOC = "W9" ;
-NET "ser_t[0]" LOC = "V7" ;
-NET "ser_t[10]" LOC = "AA6" ;
-NET "ser_t[11]" LOC = "Y6" ;
-NET "ser_t[12]" LOC = "W8" ;
-NET "ser_t[13]" LOC = "V8" ;
-NET "ser_t[14]" LOC = "AB8" ;
-NET "ser_t[15]" LOC = "AA8" ;
-NET "ser_t[1]" LOC = "V10" ;
-NET "ser_t[2]" LOC = "AB4" ;
-NET "ser_t[3]" LOC = "AA4" ;
-NET "ser_t[4]" LOC = "Y5" ;
-NET "ser_t[5]" LOC = "W5" ;
-NET "ser_t[6]" LOC = "AB5" ;
-NET "ser_t[7]" LOC = "AA5" ;
-NET "ser_t[8]" LOC = "W6" ;
-NET "ser_t[9]" LOC = "V6" ;
-NET "clk_muxed" TNM_NET = "clk_muxed";
-TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
-NET "clk_to_mac" TNM_NET = "clk_to_mac";
-TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
-NET "cpld_clk" TNM_NET = "cpld_clk";
-TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
-TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
-NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
-TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
-#PACE: Start of Constraints generated by PACE
-
-#PACE: Start of PACE I/O Pin Assignments
-NET "adc_oen_a" LOC = "E19" ;
-NET "adc_oen_b" LOC = "C17" ;
-NET "adc_ovf_a" LOC = "F18" ;
-NET "adc_ovf_b" LOC = "B17" ;
-NET "adc_pdn_a" LOC = "E20" ;
-NET "adc_pdn_b" LOC = "D15" ;
-NET "clk_fpga_n" LOC = "B11" ;
-NET "clk_fpga_p" LOC = "A11" ;
-NET "clk_func" LOC = "C12" ;
-NET "clk_status" LOC = "B12" ;
-NET "clk_to_mac" LOC = "AB12" ;
-NET "cpld_clk" LOC = "AB14" ;
-NET "cpld_din" LOC = "AA14" ;
-NET "cpld_done" LOC = "V12" ;
-NET "cpld_mode" LOC = "U12" ;
-NET "cpld_start" LOC = "AA9" ;
-NET "exp_pps_in_n" LOC = "V4" ;
-NET "exp_pps_in_p" LOC = "V3" ;
-NET "exp_pps_out_n" LOC = "V2" ;
-NET "exp_pps_out_p" LOC = "V1" ;
-NET "GMII_COL" LOC = "U16" ;
-NET "GMII_CRS" LOC = "U17" ;
-NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_RX_CLK" LOC = "W16" ;
-NET "GMII_RX_DV" LOC = "AB16" ;
-NET "GMII_RX_ER" LOC = "AA16" ;
-NET "GMII_TX_CLK" LOC = "W13" ;
-NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "led1" LOC = "V11" ;
-NET "led2" LOC = "Y12" ;
-NET "MDC" LOC = "V18" ;
-NET "MDIO" LOC = "Y16" | PULLUP ;
-NET "PHY_CLK" LOC = "V15" ;
-NET "PHY_INTn" LOC = "AB13" ;
-NET "PHY_RESETn" LOC = "AA19" ;
-NET "pps_in" LOC = "Y11" ;
-NET "RAM_CE1n" LOC = "N21" ;
-NET "RAM_CENn" LOC = "M18" ;
-NET "RAM_CLK" LOC = "M17" ;
-NET "RAM_LDn" LOC = "M21" ;
-NET "RAM_OEn" LOC = "M19" ;
-NET "RAM_WEn" LOC = "M20" ;
-NET "SCL" LOC = "A7" ;
-NET "SCL_force" LOC = "E8" ;
-NET "sclk" LOC = "K5" ;
-NET "sclk_rx_adc" LOC = "J17" ;
-NET "sclk_rx_dac" LOC = "J19" ;
-NET "sclk_rx_db" LOC = "F19" ;
-NET "sclk_tx_adc" LOC = "H1" ;
-NET "sclk_tx_dac" LOC = "J5" ;
-NET "sclk_tx_db" LOC = "D3" ;
-NET "SDA" LOC = "D8" ;
-NET "SDA_force" LOC = "C11" ;
-NET "sdi" LOC = "J1" ;
-NET "sdi_rx_adc" LOC = "H22" ;
-NET "sdi_rx_dac" LOC = "J21" ;
-NET "sdi_rx_db" LOC = "H19" ;
-NET "sdi_tx_adc" LOC = "J4" ;
-NET "sdi_tx_dac" LOC = "J6" ;
-NET "sdi_tx_db" LOC = "G4" ;
-NET "sdo" LOC = "J2" ;
-NET "sdo_rx_adc" LOC = "H21" ;
-NET "sdo_rx_db" LOC = "G20" ;
-NET "sdo_tx_adc" LOC = "H2" ;
-NET "sdo_tx_db" LOC = "G3" ;
-NET "sen_clk" LOC = "K6" ;
-NET "sen_dac" LOC = "L1" ;
-NET "sen_rx_adc" LOC = "H18" ;
-NET "sen_rx_dac" LOC = "J18" ;
-NET "sen_rx_db" LOC = "D22" ;
-NET "sen_tx_adc" LOC = "G2" ;
-NET "sen_tx_dac" LOC = "H4" ;
-NET "sen_tx_db" LOC = "C1" ;
-NET "ser_enable" LOC = "W11" ;
-NET "ser_loopen" LOC = "Y4" ;
-NET "ser_prbsen" LOC = "AA3" ;
-NET "ser_rklsb" LOC = "V9" ;
-NET "ser_rkmsb" LOC = "Y10" ;
-NET "ser_rx_clk" LOC = "AA11" ;
-NET "ser_rx_en" LOC = "AB9" ;
-NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<8>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<9>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<10>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<11>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<12>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<13>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<14>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-NET "ser_t<15>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ;
-#PACE: Start of PACE Area Constraints
-
-#PACE: Start of PACE Prohibit Constraints
-
-#PACE: End of Constraints generated by PACE
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj b/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj
deleted file mode 100644
index 544415f4d..000000000
--- a/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj
+++ /dev/null
@@ -1,102 +0,0 @@
-verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
-verilog work "../../control_lib/ram_2port.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
-verilog work "../../coregen/fifo_generator_v4_1.v"
-verilog work "../../control_lib/shortfifo.v"
-verilog work "../../control_lib/longfifo.v"
-verilog work "../../sdr_lib/sign_extend.v"
-verilog work "../../sdr_lib/cordic_stage.v"
-verilog work "../../sdr_lib/cic_int_shifter.v"
-verilog work "../../sdr_lib/cic_dec_shifter.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
-verilog work "../../opencores/8b10b/encode_8b10b.v"
-verilog work "../../opencores/8b10b/decode_8b10b.v"
-verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
-verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
-verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
-verilog work "../../eth/rtl/verilog/Reg_int.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
-verilog work "../../control_lib/ss_rcvr.v"
-verilog work "../../control_lib/cascadefifo2.v"
-verilog work "../../control_lib/CRC16_D16.v"
-verilog work "../../timing/time_sender.v"
-verilog work "../../timing/time_receiver.v"
-verilog work "../../serdes/serdes_tx.v"
-verilog work "../../serdes/serdes_rx.v"
-verilog work "../../serdes/serdes_fc_tx.v"
-verilog work "../../serdes/serdes_fc_rx.v"
-verilog work "../../sdr_lib/round.v"
-verilog work "../../sdr_lib/cordic.v"
-verilog work "../../sdr_lib/cic_interp.v"
-verilog work "../../sdr_lib/cic_decim.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
-verilog work "../../eth/rtl/verilog/eth_miim.v"
-verilog work "../../eth/rtl/verilog/RMON.v"
-verilog work "../../eth/rtl/verilog/Phy_int.v"
-verilog work "../../eth/rtl/verilog/MAC_tx.v"
-verilog work "../../eth/rtl/verilog/MAC_rx.v"
-verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
-verilog work "../../control_lib/strobe_gen.v"
-verilog work "../../control_lib/setting_reg.v"
-verilog work "../../control_lib/mux8.v"
-verilog work "../../control_lib/mux4.v"
-verilog work "../../control_lib/icache.v"
-verilog work "../../control_lib/dpram32.v"
-verilog work "../../control_lib/decoder_3_8.v"
-verilog work "../../control_lib/dcache.v"
-verilog work "../../control_lib/buffer_int.v"
-verilog work "../../timing/timer.v"
-verilog work "../../timing/time_sync.v"
-verilog work "../../serdes/serdes.v"
-verilog work "../../sdr_lib/tx_control.v"
-verilog work "../../sdr_lib/rx_control.v"
-verilog work "../../sdr_lib/dsp_core_tx.v"
-verilog work "../../sdr_lib/dsp_core_rx.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
-verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
-verilog work "../../eth/rtl/verilog/MAC_top.v"
-verilog work "../../eth/mac_txfifo_int.v"
-verilog work "../../eth/mac_rxfifo_int.v"
-verilog work "../../control_lib/wb_readback_mux.v"
-verilog work "../../control_lib/wb_1master.v"
-verilog work "../../control_lib/system_control.v"
-verilog work "../../control_lib/settings_bus.v"
-verilog work "../../control_lib/ram_loader.v"
-verilog work "../../control_lib/ram_harv_cache.v"
-verilog work "../../control_lib/nsgpio.v"
-verilog work "../../control_lib/extram_interface.v"
-verilog work "../../control_lib/buffer_pool.v"
-verilog work "../../control_lib/atr_controller.v"
-verilog work "../u2_basic/u2_basic.v"
-verilog work "u2_fpga_top.v"
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga_top.v b/fpga/usrp2/top/u2_rev1/u2_fpga_top.v
deleted file mode 100644
index 63798a0c8..000000000
--- a/fpga/usrp2/top/u2_rev1/u2_fpga_top.v
+++ /dev/null
@@ -1,393 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module u2_fpga_top
- (
- // Misc, debug
- output led1,
- output led2,
- output [31:0] debug,
- output [1:0] debug_clk,
-
- // Expansion
- input exp_pps_in_p, // Diff
- input exp_pps_in_n, // Diff
- output exp_pps_out_p, // Diff
- output exp_pps_out_n, // Diff
-
- // GMII
- // GMII-CTRL
- input GMII_COL,
- input GMII_CRS,
-
- // GMII-TX
- output reg [7:0] GMII_TXD,
- output reg GMII_TX_EN,
- output reg GMII_TX_ER,
- output GMII_GTX_CLK,
- input GMII_TX_CLK, // 100mbps clk
-
- // GMII-RX
- input [7:0] GMII_RXD,
- input GMII_RX_CLK,
- input GMII_RX_DV,
- input GMII_RX_ER,
-
- // GMII-Management
- inout MDIO,
- output MDC,
- input PHY_INTn, // open drain
- output PHY_RESETn,
- input PHY_CLK, // possibly use on-board osc
-
- // RAM
- inout [17:0] RAM_D,
- output [18:0] RAM_A,
- output RAM_CE1n,
- output RAM_CENn,
- output RAM_CLK,
- output RAM_WEn,
- output RAM_OEn,
- output RAM_LDn,
-
- // SERDES
- output ser_enable,
- output ser_prbsen,
- output ser_loopen,
- output ser_rx_en,
-
- output ser_tx_clk,
- output reg [15:0] ser_t,
- output reg ser_tklsb,
- output reg ser_tkmsb,
-
- input ser_rx_clk,
- input [15:0] ser_r,
- input ser_rklsb,
- input ser_rkmsb,
-
- // CPLD interface
- output cpld_start, // AA9
- output cpld_mode, // U12
- output cpld_done, // V12
- input cpld_din, // AA14 Now shared with CFG_Din
- input cpld_clk, // AB14 serial clock
-
- // ADC
- input [13:0] adc_a,
- input adc_ovf_a,
- output adc_oen_a,
- output adc_pdn_a,
-
- input [13:0] adc_b,
- input adc_ovf_b,
- output adc_oen_b,
- output adc_pdn_b,
-
- // DAC
- output [15:0] dac_a,
- output [15:0] dac_b,
-
- // I2C
- inout SCL,
- inout SDA,
- input SCL_force,
- input SDA_force,
-
- // Clock Gen Control
- output [1:0] clk_en,
- output [1:0] clk_sel,
- input clk_func, // FIXME is an input to control the 9510
- input clk_status,
-
- // Clocks
- input clk_fpga_p, // Diff
- input clk_fpga_n, // Diff
- input clk_to_mac,
- input pps_in,
-
- // Generic SPI
- output sclk,
- output sen_clk,
- output sen_dac,
- output sdi,
- input sdo,
-
- // TX DBoard
- output sen_tx_db,
- output sclk_tx_db,
- input sdo_tx_db,
- output sdi_tx_db,
-
- output sen_tx_adc,
- output sclk_tx_adc,
- input sdo_tx_adc,
- output sdi_tx_adc,
-
- output sen_tx_dac,
- output sclk_tx_dac,
- output sdi_tx_dac,
-
- inout [15:0] io_tx,
-
- // RX DBoard
- output sen_rx_db,
- output sclk_rx_db,
- input sdo_rx_db,
- output sdi_rx_db,
-
- output sen_rx_adc,
- output sclk_rx_adc,
- input sdo_rx_adc,
- output sdi_rx_adc,
-
- output sen_rx_dac,
- output sclk_rx_dac,
- output sdi_rx_dac,
-
- inout [15:0] io_rx
- );
-
- // FPGA-specific pins connections
- wire aux_clk = PHY_CLK;
- //wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
- wire cpld_detached = SDA_force; // FIXME Hacked on with Blue Wire
-
- wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
-
- IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
- defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
-
- wire exp_pps_in;
- IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
- defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
-
- wire exp_pps_out;
- OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
- defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
-
- reg [5:0] clock_ready_d;
- always @(posedge aux_clk)
- clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
-
- wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
- wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
-
- wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
- assign adc_oen_a = ~adc_oe_a;
- assign adc_oen_b = ~adc_oe_b;
- assign adc_pdn_a = ~adc_on_a;
- assign adc_pdn_b = ~adc_on_b;
-
- // Handle Clocks
- DCM DCM_INST (.CLKFB(dsp_clk),
- .CLKIN(clk_muxed),
- .DSSEN(0),
- .PSCLK(0),
- .PSEN(0),
- .PSINCDEC(0),
- .RST(dcm_rst),
- .CLKDV(clk_div),
- .CLKFX(),
- .CLKFX180(),
- .CLK0(dcm_out),
- .CLK2X(),
- .CLK2X180(),
- .CLK90(),
- .CLK180(),
- .CLK270(),
- .LOCKED(LOCKED_OUT),
- .PSDONE(),
- .STATUS());
- defparam DCM_INST.CLK_FEEDBACK = "1X";
- defparam DCM_INST.CLKDV_DIVIDE = 2.0;
- defparam DCM_INST.CLKFX_DIVIDE = 1;
- defparam DCM_INST.CLKFX_MULTIPLY = 4;
- defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
- defparam DCM_INST.CLKIN_PERIOD = 10.000;
- defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
- defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
- defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
- defparam DCM_INST.FACTORY_JF = 16'h8080;
- defparam DCM_INST.PHASE_SHIFT = 0;
- defparam DCM_INST.STARTUP_WAIT = "FALSE";
-
- BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
- BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
-
- // I2C -- Don't use external transistors for open drain, the FPGA implements this
- IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
- IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
-
- // LEDs are active low outputs
- wire led1_int, led2_int;
- assign led1 = ~led1_int;
- assign led2 = ~led2_int;
-
- // SPI
- wire miso, mosi, sclk_int;
- assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
-
- assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
- (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
- (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
-
- wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
- wire [7:0] GMII_TXD_unreg;
- wire GMII_GTX_CLK_int;
-
- always @(posedge GMII_GTX_CLK_int)
- begin
- GMII_TX_EN <= GMII_TX_EN_unreg;
- GMII_TX_ER <= GMII_TX_ER_unreg;
- GMII_TXD <= GMII_TXD_unreg;
- end
-
- OFDDRRSE OFDDRRSE_gmii_inst
- (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
- .C0(GMII_GTX_CLK_int), // 0 degree clock input
- .C1(~GMII_GTX_CLK_int), // 180 degree clock input
- .CE(1), // Clock enable input
- .D0(0), // Posedge data input
- .D1(1), // Negedge data input
- .R(0), // Synchronous reset input
- .S(0) // Synchronous preset input
- );
-
- wire ser_tklsb_unreg, ser_tkmsb_unreg;
- wire [15:0] ser_t_unreg;
- wire ser_tx_clk_int;
-
- always @(posedge ser_tx_clk_int)
- begin
- ser_tklsb <= ser_tklsb_unreg;
- ser_tkmsb <= ser_tkmsb_unreg;
- ser_t <= ser_t_unreg;
- end
-
- assign ser_tx_clk = clk_fpga;
-
- reg [15:0] ser_r_int;
- reg ser_rklsb_int, ser_rkmsb_int;
-
- always @(posedge ser_rx_clk)
- begin
- ser_r_int <= ser_r;
- ser_rklsb_int <= ser_rklsb;
- ser_rkmsb_int <= ser_rkmsb;
- end
-
- /*
- OFDDRRSE OFDDRRSE_serdes_inst
- (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
- .C0(ser_tx_clk_int), // 0 degree clock input
- .C1(~ser_tx_clk_int), // 180 degree clock input
- .CE(1), // Clock enable input
- .D0(0), // Posedge data input
- .D1(1), // Negedge data input
- .R(0), // Synchronous reset input
- .S(0) // Synchronous preset input
- );
- */
- u2_basic u2_basic(.dsp_clk (dsp_clk),
- .wb_clk (wb_clk),
- .clock_ready (clock_ready),
- .clk_to_mac (clk_to_mac),
- .pps_in (pps_in),
- .led1 (led1_int),
- .led2 (led2_int),
- .debug (debug[31:0]),
- .debug_clk (debug_clk[1:0]),
- .exp_pps_in (exp_pps_in),
- .exp_pps_out (exp_pps_out),
- .GMII_COL (GMII_COL),
- .GMII_CRS (GMII_CRS),
- .GMII_TXD (GMII_TXD_unreg[7:0]),
- .GMII_TX_EN (GMII_TX_EN_unreg),
- .GMII_TX_ER (GMII_TX_ER_unreg),
- .GMII_GTX_CLK (GMII_GTX_CLK_int),
- .GMII_TX_CLK (GMII_TX_CLK),
- .GMII_RXD (GMII_RXD[7:0]),
- .GMII_RX_CLK (GMII_RX_CLK),
- .GMII_RX_DV (GMII_RX_DV),
- .GMII_RX_ER (GMII_RX_ER),
- .MDIO (MDIO),
- .MDC (MDC),
- .PHY_INTn (PHY_INTn),
- .PHY_RESETn (PHY_RESETn),
- .PHY_CLK (PHY_CLK),
- .ser_enable (ser_enable),
- .ser_prbsen (ser_prbsen),
- .ser_loopen (ser_loopen),
- .ser_rx_en (ser_rx_en),
- .ser_tx_clk (ser_tx_clk_int),
- .ser_t (ser_t_unreg[15:0]),
- .ser_tklsb (ser_tklsb_unreg),
- .ser_tkmsb (ser_tkmsb_unreg),
- .ser_rx_clk (ser_rx_clk),
- .ser_r (ser_r_int[15:0]),
- .ser_rklsb (ser_rklsb_int),
- .ser_rkmsb (ser_rkmsb_int),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .cpld_din (cpld_din),
- .cpld_clk (cpld_clk),
- .cpld_detached (cpld_detached),
- .adc_a (adc_a[13:0]),
- .adc_ovf_a (adc_ovf_a),
- .adc_on_a (adc_on_a),
- .adc_oe_a (adc_oe_a),
- .adc_b (adc_b[13:0]),
- .adc_ovf_b (adc_ovf_b),
- .adc_on_b (adc_on_b),
- .adc_oe_b (adc_oe_b),
- .dac_a (dac_a[15:0]),
- .dac_b (dac_b[15:0]),
- .scl_pad_i (scl_pad_i),
- .scl_pad_o (scl_pad_o),
- .scl_pad_oen_o (scl_pad_oen_o),
- .sda_pad_i (sda_pad_i),
- .sda_pad_o (sda_pad_o),
- .sda_pad_oen_o (sda_pad_oen_o),
- .clk_en (clk_en[1:0]),
- .clk_sel (clk_sel[1:0]),
- .clk_func (clk_func),
- .clk_status (clk_status),
- .sclk (sclk_int),
- .mosi (mosi),
- .miso (miso),
- .sen_clk (sen_clk),
- .sen_dac (sen_dac),
- .sen_tx_db (sen_tx_db),
- .sen_tx_adc (sen_tx_adc),
- .sen_tx_dac (sen_tx_dac),
- .sen_rx_db (sen_rx_db),
- .sen_rx_adc (sen_rx_adc),
- .sen_rx_dac (sen_rx_dac),
- .io_tx (io_tx[15:0]),
- .io_rx (io_rx[15:0]),
- .RAM_D (RAM_D),
- .RAM_A (RAM_A),
- .RAM_CE1n (RAM_CE1n),
- .RAM_CENn (RAM_CENn),
- .RAM_CLK (RAM_CLK),
- .RAM_WEn (RAM_WEn),
- .RAM_OEn (RAM_OEn),
- .RAM_LDn (RAM_LDn),
- .uart_tx_o (),
- .uart_rx_i (),
- .uart_baud_o (),
- .sim_mode (1'b0),
- .clock_divider (2)
- );
-
-endmodule // u2_fpga_top
diff --git a/fpga/usrp2/top/u2_rev2/.gitignore b/fpga/usrp2/top/u2_rev2/.gitignore
deleted file mode 100644
index 432f8fd58..000000000
--- a/fpga/usrp2/top/u2_rev2/.gitignore
+++ /dev/null
@@ -1,57 +0,0 @@
-/*.ptwx
-/*.xrpt
-/*.zip
-/*_xdb
-/templates
-/netgen
-/_ngo
-/_xmsgs
-/_pace.ucf
-/*.cmd
-/*.ibs
-/*.lfp
-/*.mfp
-/*.bit
-/*.bin
-/*.stx
-/*.par
-/*.unroutes
-/*.ntrc_log
-/*.ngr
-/*.mrp
-/*.html
-/*.lso
-/*.twr
-/*.bld
-/*.ncd
-/*.txt
-/*.cmd_log
-/*.drc
-/*.map
-/*.twr
-/*.xml
-/*.syr
-/*.ngm
-/*.xst
-/*.csv
-/*.html
-/*.lock
-/*.ncd
-/*.twx
-/*.ise_ISE_Backup
-/*.xml
-/*.ut
-/*.xpi
-/*.ngd
-/*.ncd
-/*.pad
-/*.bgn
-/*.ngc
-/*.pcf
-/*.ngd
-/xst
-/*.log
-/*.rpt
-/*.cel
-/*.restore
-/build
diff --git a/fpga/usrp2/top/u2_rev2/Makefile b/fpga/usrp2/top/u2_rev2/Makefile
deleted file mode 100644
index 275c24b02..000000000
--- a/fpga/usrp2/top/u2_rev2/Makefile
+++ /dev/null
@@ -1,248 +0,0 @@
-#
-# Copyright 2008 Ettus Research LLC
-#
-# This file is part of GNU Radio
-#
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING. If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-#
-
-##################################################
-# xtclsh Shell and tcl Script Path
-##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
-
-##################################################
-# Project Setup
-##################################################
-BUILD_DIR := build/
-export TOP_MODULE := u2_rev2
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
-
-##################################################
-# Project Properties
-##################################################
-export PROJECT_PROPERTIES := \
-family Spartan3 \
-device xc3s2000 \
-package fg456 \
-speed -5 \
-top_level_module_type "HDL" \
-synthesis_tool "XST (VHDL/Verilog)" \
-simulator "ISE Simulator (VHDL/Verilog)" \
-"Preferred Language" "Verilog" \
-"Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE
-
-##################################################
-# Sources
-##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller.v \
-control_lib/bin2gray.v \
-control_lib/buffer_int.v \
-control_lib/buffer_pool.v \
-control_lib/cascadefifo2.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/fifo_2clock.v \
-control_lib/fifo_2clock_casc.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/longfifo.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio.v \
-control_lib/ram_2port.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-eth/mac_rxfifo_int.v \
-eth/mac_txfifo_int.v \
-eth/rtl/verilog/Clk_ctrl.v \
-eth/rtl/verilog/MAC_rx.v \
-eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
-eth/rtl/verilog/MAC_rx/CRC_chk.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
-eth/rtl/verilog/MAC_top.v \
-eth/rtl/verilog/MAC_tx.v \
-eth/rtl/verilog/MAC_tx/CRC_gen.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
-eth/rtl/verilog/MAC_tx/Random_gen.v \
-eth/rtl/verilog/Phy_int.v \
-eth/rtl/verilog/RMON.v \
-eth/rtl/verilog/RMON/RMON_addr_gen.v \
-eth/rtl/verilog/RMON/RMON_ctrl.v \
-eth/rtl/verilog/Reg_int.v \
-eth/rtl/verilog/eth_miim.v \
-eth/rtl/verilog/flow_ctrl_rx.v \
-eth/rtl/verilog/flow_ctrl_tx.v \
-eth/rtl/verilog/miim/eth_clockgen.v \
-eth/rtl/verilog/miim/eth_outputcontrol.v \
-eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/simple_pic/rtl/simple_pic.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top.v \
-opencores/spi/rtl/verilog/timescale.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-top/u2_core/u2_core.v \
-top/u2_rev2/u2_rev2.ucf \
-top/u2_rev2/u2_rev2.v
-
-##################################################
-# Process Properties
-##################################################
-export SYNTHESIZE_PROPERTIES := \
-"Number of Clock Buffers" 6 \
-"Pack I/O Registers into IOBs" Yes \
-"Optimization Effort" High \
-"Optimize Instantiated Primitives" TRUE \
-"Register Balancing" Yes \
-"Use Clock Enable" Auto \
-"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
-
-export TRANSLATE_PROPERTIES := \
-"Macro Search Path" "$(shell pwd)/../../coregen/"
-
-export MAP_PROPERTIES := \
-"Allow Logic Optimization Across Hierarchy" TRUE \
-"Map to Input Functions" 4 \
-"Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
-"Perform Timing-Driven Packing and Placement" TRUE \
-"Map Effort Level" High \
-"Extra Effort" Normal \
-"Combinatorial Logic Optimization" TRUE \
-"Register Duplication" TRUE
-
-export PLACE_ROUTE_PROPERTIES := \
-"Place & Route Effort Level (Overall)" High
-
-export STATIC_TIMING_PROPERTIES := \
-"Number of Paths in Error/Verbose Report" 10 \
-"Report Type" "Error Report"
-
-export GEN_PROG_FILE_PROPERTIES := \
-"Configuration Rate" 6 \
-"Create Binary Configuration File" TRUE \
-"Done (Output Events)" 5 \
-"Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6
-
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
- @echo make proj, check, synth, bin, or clean
-
-proj:
- PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
-
-check:
- PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
-
-synth:
- PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
-
-bin:
- PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
-
-clean:
- rm -rf $(BUILD_DIR)
-
-
diff --git a/fpga/usrp2/top/u2_rev2/u2_rev2.ucf b/fpga/usrp2/top/u2_rev2/u2_rev2.ucf
deleted file mode 100644
index e18dc6f17..000000000
--- a/fpga/usrp2/top/u2_rev2/u2_rev2.ucf
+++ /dev/null
@@ -1,337 +0,0 @@
-NET "leds[0]" LOC = "F7" ;
-NET "leds[1]" LOC = "E5" ;
-NET "leds[2]" LOC = "B7" ;
-NET "leds[3]" LOC = "C11" ;
-NET "leds[4]" LOC = "AB19" ;
-NET "debug[0]" LOC = "N5" ;
-NET "debug[1]" LOC = "N6" ;
-NET "debug[2]" LOC = "P1" ;
-NET "debug[3]" LOC = "P2" ;
-NET "debug[4]" LOC = "P4" ;
-NET "debug[5]" LOC = "P5" ;
-NET "debug[6]" LOC = "R1" ;
-NET "debug[7]" LOC = "R2" ;
-NET "debug[8]" LOC = "P6" ;
-NET "debug[9]" LOC = "R5" ;
-NET "debug[10]" LOC = "R4" ;
-NET "debug[11]" LOC = "T3" ;
-NET "debug[12]" LOC = "U3" ;
-NET "debug[13]" LOC = "M2" ;
-NET "debug[14]" LOC = "M3" ;
-NET "debug[15]" LOC = "M4" ;
-NET "debug[16]" LOC = "M5" ;
-NET "debug[17]" LOC = "M6" ;
-NET "debug[18]" LOC = "N1" ;
-NET "debug[19]" LOC = "N2" ;
-NET "debug[20]" LOC = "N3" ;
-NET "debug[21]" LOC = "T1" ;
-NET "debug[22]" LOC = "T2" ;
-NET "debug[23]" LOC = "U2" ;
-NET "debug[24]" LOC = "T4" ;
-NET "debug[25]" LOC = "U4" ;
-NET "debug[26]" LOC = "T5" ;
-NET "debug[27]" LOC = "T6" ;
-NET "debug[28]" LOC = "U5" ;
-NET "debug[29]" LOC = "V5" ;
-NET "debug[30]" LOC = "W2" ;
-NET "debug[31]" LOC = "W3" ;
-NET "debug_clk[0]" LOC = "N4" ;
-NET "debug_clk[1]" LOC = "M1" ;
-NET "uart_tx_o" LOC = "C7" ;
-NET "uart_rx_i" LOC = "A3" ;
-NET "exp_pps_in_p" LOC = "V3" ;
-NET "exp_pps_in_n" LOC = "V4" ;
-NET "exp_pps_out_p" LOC = "V1" ;
-NET "exp_pps_out_n" LOC = "V2" ;
-NET "GMII_COL" LOC = "U16" ;
-NET "GMII_CRS" LOC = "U17" ;
-NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "GMII_TX_CLK" LOC = "W13" ;
-NET "GMII_RXD[0]" LOC = "AA15" ;
-NET "GMII_RXD[1]" LOC = "AB15" ;
-NET "GMII_RXD[2]" LOC = "U14" ;
-NET "GMII_RXD[3]" LOC = "V14" ;
-NET "GMII_RXD[4]" LOC = "U13" ;
-NET "GMII_RXD[5]" LOC = "V13" ;
-NET "GMII_RXD[6]" LOC = "Y13" ;
-NET "GMII_RXD[7]" LOC = "AA13" ;
-NET "GMII_RX_CLK" LOC = "W16" ;
-NET "GMII_RX_DV" LOC = "AB16" ;
-NET "GMII_RX_ER" LOC = "AA16" ;
-NET "MDIO" LOC = "Y16" |PULLUP ;
-NET "MDC" LOC = "V18" ;
-NET "PHY_INTn" LOC = "AB13" ;
-NET "PHY_RESETn" LOC = "AA19" ;
-NET "PHY_CLK" LOC = "V15" ;
-NET "RAM_D[0]" LOC = "N20" ;
-NET "RAM_D[1]" LOC = "N21" ;
-NET "RAM_D[2]" LOC = "N22" ;
-NET "RAM_D[3]" LOC = "M17" ;
-NET "RAM_D[4]" LOC = "M18" ;
-NET "RAM_D[5]" LOC = "M19" ;
-NET "RAM_D[6]" LOC = "M20" ;
-NET "RAM_D[7]" LOC = "M21" ;
-NET "RAM_D[8]" LOC = "M22" ;
-NET "RAM_D[9]" LOC = "Y22" ;
-NET "RAM_D[10]" LOC = "Y21" ;
-NET "RAM_D[11]" LOC = "Y20" ;
-NET "RAM_D[12]" LOC = "Y19" ;
-NET "RAM_D[13]" LOC = "W22" ;
-NET "RAM_D[14]" LOC = "W21" ;
-NET "RAM_D[15]" LOC = "W20" ;
-NET "RAM_D[16]" LOC = "W19" ;
-NET "RAM_D[17]" LOC = "V22" ;
-NET "RAM_A[0]" LOC = "U21" ;
-NET "RAM_A[1]" LOC = "T19" ;
-NET "RAM_A[2]" LOC = "V21" ;
-NET "RAM_A[3]" LOC = "V20" ;
-NET "RAM_A[4]" LOC = "T20" ;
-NET "RAM_A[5]" LOC = "T21" ;
-NET "RAM_A[6]" LOC = "T22" ;
-NET "RAM_A[7]" LOC = "T18" ;
-NET "RAM_A[8]" LOC = "R18" ;
-NET "RAM_A[9]" LOC = "P19" ;
-NET "RAM_A[10]" LOC = "P21" ;
-NET "RAM_A[11]" LOC = "P22" ;
-NET "RAM_A[12]" LOC = "N19" ;
-NET "RAM_A[13]" LOC = "N17" ;
-NET "RAM_A[14]" LOC = "N18" ;
-NET "RAM_A[15]" LOC = "T17" ;
-NET "RAM_A[16]" LOC = "U19" ;
-NET "RAM_A[17]" LOC = "U18" ;
-NET "RAM_A[18]" LOC = "V19" ;
-NET "RAM_CE1n" LOC = "U20" ;
-NET "RAM_CENn" LOC = "P18" ;
-NET "RAM_CLK" LOC = "P17" ;
-NET "RAM_WEn" LOC = "R22" ;
-NET "RAM_OEn" LOC = "R21" ;
-NET "RAM_LDn" LOC = "R19" ;
-NET "ser_enable" LOC = "W11" ;
-NET "ser_prbsen" LOC = "AA3" ;
-NET "ser_loopen" LOC = "Y4" ;
-NET "ser_rx_en" LOC = "AB9" ;
-NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
-NET "ser_rx_clk" LOC = "AA11" ;
-NET "ser_r[0]" LOC = "AB10" ;
-NET "ser_r[1]" LOC = "AA10" ;
-NET "ser_r[2]" LOC = "U9" ;
-NET "ser_r[3]" LOC = "U6" ;
-NET "ser_r[4]" LOC = "AB11" ;
-NET "ser_r[5]" LOC = "Y7" ;
-NET "ser_r[6]" LOC = "W7" ;
-NET "ser_r[7]" LOC = "AB7" ;
-NET "ser_r[8]" LOC = "AA7" ;
-NET "ser_r[9]" LOC = "W9" ;
-NET "ser_r[10]" LOC = "W10" ;
-NET "ser_r[11]" LOC = "Y1" ;
-NET "ser_r[12]" LOC = "Y3" ;
-NET "ser_r[13]" LOC = "Y2" ;
-NET "ser_r[14]" LOC = "W4" ;
-NET "ser_r[15]" LOC = "W1" ;
-NET "ser_rklsb" LOC = "V9" ;
-NET "ser_rkmsb" LOC = "Y10" ;
-NET "cpld_start" LOC = "AA9" ;
-NET "cpld_mode" LOC = "U12" ;
-NET "cpld_done" LOC = "V12" ;
-NET "cpld_din" LOC = "AA14" ;
-NET "cpld_clk" LOC = "AB14" ;
-NET "cpld_detached" LOC = "V11" ;
-NET "cpld_init_b" LOC = "W12" ;
-NET "cpld_misc" LOC = "Y12" ;
-NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ;
-NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ;
-NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ;
-NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ;
-NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ;
-NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ;
-NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ;
-NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ;
-NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ;
-NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ;
-NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ;
-NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ;
-NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ;
-NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ;
-NET "adc_ovf_a" LOC = "F18" ;
-NET "adc_oen_a" LOC = "E19" ;
-NET "adc_pdn_a" LOC = "E20" ;
-NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE";
-NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ;
-NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ;
-NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ;
-NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ;
-NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ;
-NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ;
-NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ;
-NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ;
-NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ;
-NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ;
-NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ;
-NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ;
-NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ;
-NET "adc_ovf_b" LOC = "B17" ;
-NET "adc_oen_b" LOC = "C17" ;
-NET "adc_pdn_b" LOC = "D15" ;
-NET "dac_a[0]" LOC = "A5" ;
-NET "dac_a[1]" LOC = "B5" ;
-NET "dac_a[2]" LOC = "C5" ;
-NET "dac_a[3]" LOC = "D5" ;
-NET "dac_a[4]" LOC = "A4" ;
-NET "dac_a[5]" LOC = "B4" ;
-NET "dac_a[6]" LOC = "F6" ;
-NET "dac_a[7]" LOC = "D10" ;
-NET "dac_a[8]" LOC = "D9" ;
-NET "dac_a[9]" LOC = "A10" ;
-NET "dac_a[10]" LOC = "L2" ;
-NET "dac_a[11]" LOC = "L4" ;
-NET "dac_a[12]" LOC = "L3" ;
-NET "dac_a[13]" LOC = "L6" ;
-NET "dac_a[14]" LOC = "L5" ;
-NET "dac_a[15]" LOC = "K2" ;
-NET "dac_b[0]" LOC = "D11" ;
-NET "dac_b[1]" LOC = "E11" ;
-NET "dac_b[2]" LOC = "F11" ;
-NET "dac_b[3]" LOC = "B10" ;
-NET "dac_b[4]" LOC = "C10" ;
-NET "dac_b[5]" LOC = "E10" ;
-NET "dac_b[6]" LOC = "F10" ;
-NET "dac_b[7]" LOC = "A9" ;
-NET "dac_b[8]" LOC = "B9" ;
-NET "dac_b[9]" LOC = "E9" ;
-NET "dac_b[10]" LOC = "F9" ;
-NET "dac_b[11]" LOC = "A8" ;
-NET "dac_b[12]" LOC = "B8" ;
-NET "dac_b[13]" LOC = "D7" ;
-NET "dac_b[14]" LOC = "E7" ;
-NET "dac_b[15]" LOC = "B6" ;
-NET "dac_lock" LOC = "D6" ;
-NET "SCL" LOC = "A7" ;
-NET "SDA" LOC = "D8" ;
-NET "clk_en[0]" LOC = "C4" ;
-NET "clk_en[1]" LOC = "D1" ;
-NET "clk_sel[0]" LOC = "C3" ;
-NET "clk_sel[1]" LOC = "C2" ;
-NET "clk_func" LOC = "C12" ;
-NET "clk_status" LOC = "B12" ;
-NET "clk_fpga_p" LOC = "A11" ;
-NET "clk_fpga_n" LOC = "B11" ;
-NET "clk_to_mac" LOC = "AB12" ;
-NET "pps_in" LOC = "Y11" ;
-NET "sclk" LOC = "K5" ;
-NET "sen_clk" LOC = "K6" ;
-NET "sen_dac" LOC = "L1" ;
-NET "sdi" LOC = "J1" ;
-NET "sdo" LOC = "J2" ;
-NET "sen_tx_db" LOC = "C1" ;
-NET "sclk_tx_db" LOC = "D3" ;
-NET "sdo_tx_db" LOC = "G3" ;
-NET "sdi_tx_db" LOC = "G4" ;
-NET "sen_tx_adc" LOC = "G2" ;
-NET "sclk_tx_adc" LOC = "H1" ;
-NET "sdo_tx_adc" LOC = "H2" ;
-NET "sdi_tx_adc" LOC = "J4" ;
-NET "sen_tx_dac" LOC = "H4" ;
-NET "sclk_tx_dac" LOC = "J5" ;
-NET "sdi_tx_dac" LOC = "J6" ;
-NET "io_tx[0]" LOC = "K4" ;
-NET "io_tx[1]" LOC = "K3" ;
-NET "io_tx[2]" LOC = "G1" ;
-NET "io_tx[3]" LOC = "G5" ;
-NET "io_tx[4]" LOC = "H5" ;
-NET "io_tx[5]" LOC = "F3" ;
-NET "io_tx[6]" LOC = "F2" ;
-NET "io_tx[7]" LOC = "F5" ;
-NET "io_tx[8]" LOC = "G6" ;
-NET "io_tx[9]" LOC = "E2" ;
-NET "io_tx[10]" LOC = "E1" ;
-NET "io_tx[11]" LOC = "E3" ;
-NET "io_tx[12]" LOC = "F4" ;
-NET "io_tx[13]" LOC = "D2" ;
-NET "io_tx[14]" LOC = "D4" ;
-NET "io_tx[15]" LOC = "E4" ;
-NET "sen_rx_db" LOC = "D22" ;
-NET "sclk_rx_db" LOC = "F19" ;
-NET "sdo_rx_db" LOC = "G20" ;
-NET "sdi_rx_db" LOC = "H19" ;
-NET "sen_rx_adc" LOC = "H18" ;
-NET "sclk_rx_adc" LOC = "J17" ;
-NET "sdo_rx_adc" LOC = "H21" ;
-NET "sdi_rx_adc" LOC = "H22" ;
-NET "sen_rx_dac" LOC = "J18" ;
-NET "sclk_rx_dac" LOC = "J19" ;
-NET "sdi_rx_dac" LOC = "J21" ;
-NET "io_rx[0]" LOC = "L21" ;
-NET "io_rx[1]" LOC = "L20" ;
-NET "io_rx[2]" LOC = "L19" ;
-NET "io_rx[3]" LOC = "L18" ;
-NET "io_rx[4]" LOC = "L17" ;
-NET "io_rx[5]" LOC = "K22" ;
-NET "io_rx[6]" LOC = "K21" ;
-NET "io_rx[7]" LOC = "K20" ;
-NET "io_rx[8]" LOC = "G22" ;
-NET "io_rx[9]" LOC = "G21" ;
-NET "io_rx[10]" LOC = "F21" ;
-NET "io_rx[11]" LOC = "F20" ;
-NET "io_rx[12]" LOC = "G19" ;
-NET "io_rx[13]" LOC = "G18" ;
-NET "io_rx[14]" LOC = "G17" ;
-NET "io_rx[15]" LOC = "E22" ;
-
-NET "clk_to_mac" TNM_NET = "clk_to_mac";
-TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
-
-#NET "dsp_clk" TNM_NET = "dsp_clk";
-#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
-
-NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
-TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
-
-NET "cpld_clk" TNM_NET = "cpld_clk";
-TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-
-NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
-TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
-
-NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
-TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
-
-#NET "wb_clk" TNM_NET = "wb_clk";
-#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %;
-
-NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
-NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
-
-#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
-#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
-#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-
-#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/fpga/usrp2/top/u2_rev2/u2_rev2.v b/fpga/usrp2/top/u2_rev2/u2_rev2.v
deleted file mode 100644
index 517285e52..000000000
--- a/fpga/usrp2/top/u2_rev2/u2_rev2.v
+++ /dev/null
@@ -1,417 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module u2_rev2
- (
- // Misc, debug
- output [4:0] leds,
- output [31:0] debug,
- output [1:0] debug_clk,
- output uart_tx_o,
- input uart_rx_i,
-
- // Expansion
- input exp_pps_in_p, // Diff
- input exp_pps_in_n, // Diff
- output exp_pps_out_p, // Diff
- output exp_pps_out_n, // Diff
-
- // GMII
- // GMII-CTRL
- input GMII_COL,
- input GMII_CRS,
-
- // GMII-TX
- output reg [7:0] GMII_TXD,
- output reg GMII_TX_EN,
- output reg GMII_TX_ER,
- output GMII_GTX_CLK,
- input GMII_TX_CLK, // 100mbps clk
-
- // GMII-RX
- input [7:0] GMII_RXD,
- input GMII_RX_CLK,
- input GMII_RX_DV,
- input GMII_RX_ER,
-
- // GMII-Management
- inout MDIO,
- output MDC,
- input PHY_INTn, // open drain
- output PHY_RESETn,
- input PHY_CLK, // possibly use on-board osc
-
- // RAM
- inout [17:0] RAM_D,
- output [18:0] RAM_A,
- output RAM_CE1n,
- output RAM_CENn,
- output RAM_CLK,
- output RAM_WEn,
- output RAM_OEn,
- output RAM_LDn,
-
- // SERDES
- output ser_enable,
- output ser_prbsen,
- output ser_loopen,
- output ser_rx_en,
-
- output ser_tx_clk,
- output reg [15:0] ser_t,
- output reg ser_tklsb,
- output reg ser_tkmsb,
-
- input ser_rx_clk,
- input [15:0] ser_r,
- input ser_rklsb,
- input ser_rkmsb,
-
- // CPLD interface
- output cpld_start, // AA9
- output cpld_mode, // U12
- output cpld_done, // V12
- input cpld_din, // AA14 Now shared with CFG_Din
- input cpld_clk, // AB14 serial clock
- input cpld_detached,// V11 unused
- output cpld_init_b, // W12 unused dual purpose
- output cpld_misc, // Y12
-
- // ADC
- input [13:0] adc_a,
- input adc_ovf_a,
- output adc_oen_a,
- output adc_pdn_a,
-
- input [13:0] adc_b,
- input adc_ovf_b,
- output adc_oen_b,
- output adc_pdn_b,
-
- // DAC
- output reg [15:0] dac_a,
- output reg [15:0] dac_b,
- input dac_lock, // unused for now
-
- // I2C
- inout SCL,
- inout SDA,
-
- // Clock Gen Control
- output [1:0] clk_en,
- output [1:0] clk_sel,
- input clk_func, // FIXME is an input to control the 9510
- input clk_status,
-
- // Clocks
- input clk_fpga_p, // Diff
- input clk_fpga_n, // Diff
- input clk_to_mac,
- input pps_in,
-
- // Generic SPI
- output sclk,
- output sen_clk,
- output sen_dac,
- output sdi,
- input sdo,
-
- // TX DBoard
- output sen_tx_db,
- output sclk_tx_db,
- input sdo_tx_db,
- output sdi_tx_db,
-
- output sen_tx_adc,
- output sclk_tx_adc,
- input sdo_tx_adc,
- output sdi_tx_adc,
-
- output sen_tx_dac,
- output sclk_tx_dac,
- output sdi_tx_dac,
-
- inout [15:0] io_tx,
-
- // RX DBoard
- output sen_rx_db,
- output sclk_rx_db,
- input sdo_rx_db,
- output sdi_rx_db,
-
- output sen_rx_adc,
- output sclk_rx_adc,
- input sdo_rx_adc,
- output sdi_rx_adc,
-
- output sen_rx_dac,
- output sclk_rx_dac,
- output sdi_rx_dac,
-
- inout [15:0] io_rx
- );
-
- assign cpld_init_b = 0;
- // FPGA-specific pins connections
- wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
- wire clk90, clk180, clk270;
-
- IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
- defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
-
- wire exp_pps_in;
- IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
- defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
-
- wire exp_pps_out;
- OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
- defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
-
- reg [5:0] clock_ready_d;
- always @(posedge clk_fpga)
- clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
- wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
-
- wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
- assign adc_oen_a = ~adc_oe_a;
- assign adc_oen_b = ~adc_oe_b;
- assign adc_pdn_a = ~adc_on_a;
- assign adc_pdn_b = ~adc_on_b;
-
- reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
- reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
-
- always @(posedge dsp_clk)
- begin
- adc_a_reg1 <= adc_a;
- adc_b_reg1 <= adc_b;
- adc_ovf_a_reg1 <= adc_ovf_a;
- adc_ovf_b_reg1 <= adc_ovf_b;
- end
-
- always @(posedge dsp_clk)
- begin
- adc_a_reg2 <= adc_a_reg1;
- adc_b_reg2 <= adc_b_reg1;
- adc_ovf_a_reg2 <= adc_ovf_a_reg1;
- adc_ovf_b_reg2 <= adc_ovf_b_reg1;
- end // always @ (posedge dsp_clk)
-
- // Handle Clocks
- DCM DCM_INST (.CLKFB(dsp_clk),
- .CLKIN(clk_fpga),
- .DSSEN(0),
- .PSCLK(0),
- .PSEN(0),
- .PSINCDEC(0),
- .RST(dcm_rst),
- .CLKDV(clk_div),
- .CLKFX(),
- .CLKFX180(),
- .CLK0(dcm_out),
- .CLK2X(),
- .CLK2X180(),
- .CLK90(clk90),
- .CLK180(clk180),
- .CLK270(clk270),
- .LOCKED(LOCKED_OUT),
- .PSDONE(),
- .STATUS());
- defparam DCM_INST.CLK_FEEDBACK = "1X";
- defparam DCM_INST.CLKDV_DIVIDE = 2.0;
- defparam DCM_INST.CLKFX_DIVIDE = 1;
- defparam DCM_INST.CLKFX_MULTIPLY = 4;
- defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
- defparam DCM_INST.CLKIN_PERIOD = 10.000;
- defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
- defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
- defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
- defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
- defparam DCM_INST.FACTORY_JF = 16'h8080;
- defparam DCM_INST.PHASE_SHIFT = 0;
- defparam DCM_INST.STARTUP_WAIT = "FALSE";
-
- BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
- BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
-
- // I2C -- Don't use external transistors for open drain, the FPGA implements this
- IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
- IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
-
- // LEDs are active low outputs
- wire [4:0] leds_int;
- assign leds = 5'b01111 ^ leds_int; // all except eth are active-low
-
- // SPI
- wire miso, mosi, sclk_int;
- assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
-
- assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
- (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
- (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
-
- wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
- wire [7:0] GMII_TXD_unreg;
- wire GMII_GTX_CLK_int;
-
- always @(posedge GMII_GTX_CLK_int)
- begin
- GMII_TX_EN <= GMII_TX_EN_unreg;
- GMII_TX_ER <= GMII_TX_ER_unreg;
- GMII_TXD <= GMII_TXD_unreg;
- end
-
- OFDDRRSE OFDDRRSE_gmii_inst
- (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port)
- .C0(GMII_GTX_CLK_int), // 0 degree clock input
- .C1(~GMII_GTX_CLK_int), // 180 degree clock input
- .CE(1), // Clock enable input
- .D0(0), // Posedge data input
- .D1(1), // Negedge data input
- .R(0), // Synchronous reset input
- .S(0) // Synchronous preset input
- );
-
- wire ser_tklsb_unreg, ser_tkmsb_unreg;
- wire [15:0] ser_t_unreg;
- wire ser_tx_clk_int;
-
- always @(posedge ser_tx_clk_int)
- begin
- ser_tklsb <= ser_tklsb_unreg;
- ser_tkmsb <= ser_tkmsb_unreg;
- ser_t <= ser_t_unreg;
- end
-
- assign ser_tx_clk = clk_fpga;
-
- reg [15:0] ser_r_int;
- reg ser_rklsb_int, ser_rkmsb_int;
-
- always @(posedge ser_rx_clk)
- begin
- ser_r_int <= ser_r;
- ser_rklsb_int <= ser_rklsb;
- ser_rkmsb_int <= ser_rkmsb;
- end
-
- wire [15:0] dac_a_int, dac_b_int;
- always @(negedge dsp_clk) dac_a <= dac_a_int;
- always @(negedge dsp_clk) dac_b <= dac_b_int;
-
- /*
- OFDDRRSE OFDDRRSE_serdes_inst
- (.Q(ser_tx_clk), // Data output (connect directly to top-level port)
- .C0(ser_tx_clk_int), // 0 degree clock input
- .C1(~ser_tx_clk_int), // 180 degree clock input
- .CE(1), // Clock enable input
- .D0(0), // Posedge data input
- .D1(1), // Negedge data input
- .R(0), // Synchronous reset input
- .S(0) // Synchronous preset input
- );
- */
- u2_core #(.RAM_SIZE(32768))
- u2_core(.dsp_clk (dsp_clk),
- .wb_clk (wb_clk),
- .clock_ready (clock_ready),
- .clk_to_mac (clk_to_mac),
- .pps_in (pps_in),
- .leds (leds_int),
- .debug (debug[31:0]),
- .debug_clk (debug_clk[1:0]),
- .exp_pps_in (exp_pps_in),
- .exp_pps_out (exp_pps_out),
- .GMII_COL (GMII_COL),
- .GMII_CRS (GMII_CRS),
- .GMII_TXD (GMII_TXD_unreg[7:0]),
- .GMII_TX_EN (GMII_TX_EN_unreg),
- .GMII_TX_ER (GMII_TX_ER_unreg),
- .GMII_GTX_CLK (GMII_GTX_CLK_int),
- .GMII_TX_CLK (GMII_TX_CLK),
- .GMII_RXD (GMII_RXD[7:0]),
- .GMII_RX_CLK (GMII_RX_CLK),
- .GMII_RX_DV (GMII_RX_DV),
- .GMII_RX_ER (GMII_RX_ER),
- .MDIO (MDIO),
- .MDC (MDC),
- .PHY_INTn (PHY_INTn),
- .PHY_RESETn (PHY_RESETn),
- .ser_enable (ser_enable),
- .ser_prbsen (ser_prbsen),
- .ser_loopen (ser_loopen),
- .ser_rx_en (ser_rx_en),
- .ser_tx_clk (ser_tx_clk_int),
- .ser_t (ser_t_unreg[15:0]),
- .ser_tklsb (ser_tklsb_unreg),
- .ser_tkmsb (ser_tkmsb_unreg),
- .ser_rx_clk (ser_rx_clk),
- .ser_r (ser_r_int[15:0]),
- .ser_rklsb (ser_rklsb_int),
- .ser_rkmsb (ser_rkmsb_int),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .cpld_din (cpld_din),
- .cpld_clk (cpld_clk),
- .cpld_detached (cpld_detached),
- .cpld_misc (cpld_misc),
- .cpld_init_b (cpld_init_b),
- .por (~POR),
- .config_success (config_success),
- .adc_a (adc_a_reg2),
- .adc_ovf_a (adc_ovf_a_reg2),
- .adc_on_a (adc_on_a),
- .adc_oe_a (adc_oe_a),
- .adc_b (adc_b_reg2),
- .adc_ovf_b (adc_ovf_b_reg2),
- .adc_on_b (adc_on_b),
- .adc_oe_b (adc_oe_b),
- .dac_a (dac_a_int),
- .dac_b (dac_b_int),
- .scl_pad_i (scl_pad_i),
- .scl_pad_o (scl_pad_o),
- .scl_pad_oen_o (scl_pad_oen_o),
- .sda_pad_i (sda_pad_i),
- .sda_pad_o (sda_pad_o),
- .sda_pad_oen_o (sda_pad_oen_o),
- .clk_en (clk_en[1:0]),
- .clk_sel (clk_sel[1:0]),
- .clk_func (clk_func),
- .clk_status (clk_status),
- .sclk (sclk_int),
- .mosi (mosi),
- .miso (miso),
- .sen_clk (sen_clk),
- .sen_dac (sen_dac),
- .sen_tx_db (sen_tx_db),
- .sen_tx_adc (sen_tx_adc),
- .sen_tx_dac (sen_tx_dac),
- .sen_rx_db (sen_rx_db),
- .sen_rx_adc (sen_rx_adc),
- .sen_rx_dac (sen_rx_dac),
- .io_tx (io_tx[15:0]),
- .io_rx (io_rx[15:0]),
- .RAM_D (RAM_D),
- .RAM_A (RAM_A),
- .RAM_CE1n (RAM_CE1n),
- .RAM_CENn (RAM_CENn),
- .RAM_CLK (RAM_CLK),
- .RAM_WEn (RAM_WEn),
- .RAM_OEn (RAM_OEn),
- .RAM_LDn (RAM_LDn),
- .uart_tx_o (uart_tx_o),
- .uart_rx_i (uart_rx_i),
- .uart_baud_o (),
- .sim_mode (1'b0),
- .clock_divider (2)
- );
-
-endmodule // u2_rev2
diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/u2_rev3/Makefile
index 867fb5cab..af93700c5 100644
--- a/fpga/usrp2/top/u2_rev3/Makefile
+++ b/fpga/usrp2/top/u2_rev3/Makefile
@@ -70,6 +70,7 @@ control_lib/ram_harv_cache.v \
control_lib/ram_loader.v \
control_lib/setting_reg.v \
control_lib/settings_bus.v \
+control_lib/settings_bus_crossclock.v \
control_lib/srl.v \
control_lib/system_control.v \
control_lib/wb_1master.v \
@@ -134,6 +135,8 @@ coregen/fifo_xlnx_64x36_2clk.v \
coregen/fifo_xlnx_64x36_2clk.xco \
coregen/fifo_xlnx_16x19_2clk.v \
coregen/fifo_xlnx_16x19_2clk.xco \
+coregen/fifo_xlnx_16x40_2clk.v \
+coregen/fifo_xlnx_16x40_2clk.xco \
extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 20:00:21 +0000