diff options
Diffstat (limited to 'fpga/usrp2/top')
67 files changed, 1227 insertions, 4367 deletions
diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/B100/.gitignore index 1b2211df0..1b2211df0 100644 --- a/fpga/usrp2/top/u1e_passthru/.gitignore +++ b/fpga/usrp2/top/B100/.gitignore diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile new file mode 100644 index 000000000..ca6ec9320 --- /dev/null +++ b/fpga/usrp2/top/B100/Makefile @@ -0,0 +1,97 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u1plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpif/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan3A" \ +device XC3S1400A \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1plus.v \ +u1plus_core.v \ +u1plus.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPIF_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile new file mode 100755 index 000000000..b2ccc8b49 --- /dev/null +++ b/fpga/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf new file mode 100644 index 000000000..b2a455f6d --- /dev/null +++ b/fpga/usrp2/top/B100/timing.ucf @@ -0,0 +1,5 @@ +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; diff --git a/fpga/usrp2/top/B100/u1plus.ucf b/fpga/usrp2/top/B100/u1plus.ucf new file mode 100644 index 000000000..cd89878e3 --- /dev/null +++ b/fpga/usrp2/top/B100/u1plus.ucf @@ -0,0 +1,203 @@ +## Main Clock +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + +## UART +NET "FPGA_TXD" LOC = "H16" ; +NET "FPGA_RXD" LOC = "H12" ; + +## I2C +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; + +## CGEN +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "cgen_st_status" LOC = "P6" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "cgen_sync_b" LOC = "H15" ; + +## FPGA Config +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +#NET "fpga_cfg_init_b" LOC = "T12" ; + +## MISC +#NET "mystery_bus<2>" LOC = "T11" ; +#NET "mystery_bus<1>" LOC = "C4" ; +#NET "mystery_bus<0>" LOC = "E7" ; +NET "reset_n" LOC = "D5" ; +NET "PPS_IN" LOC = "M14" ; +NET "reset_codec" LOC = "B14" ; + +## GPIF +NET "GPIF_D<15>" LOC = "P7" ; +NET "GPIF_D<14>" LOC = "N8" ; +NET "GPIF_D<13>" LOC = "T5" ; +NET "GPIF_D<12>" LOC = "T6" ; +NET "GPIF_D<11>" LOC = "N6" ; +NET "GPIF_D<10>" LOC = "P5" ; +NET "GPIF_D<9>" LOC = "R3" ; +NET "GPIF_D<8>" LOC = "T3" ; +NET "GPIF_D<7>" LOC = "N12" ; +NET "GPIF_D<6>" LOC = "P13" ; +NET "GPIF_D<5>" LOC = "P11" ; +NET "GPIF_D<4>" LOC = "R9" ; +NET "GPIF_D<3>" LOC = "T9" ; +NET "GPIF_D<2>" LOC = "N9" ; +NET "GPIF_D<1>" LOC = "P9" ; +NET "GPIF_D<0>" LOC = "P8" ; + +NET "GPIF_CTL<3>" LOC = "N5" ; +NET "GPIF_CTL<2>" LOC = "M11" ; +NET "GPIF_CTL<1>" LOC = "M9" ; +NET "GPIF_CTL<0>" LOC = "M7" ; + +NET "GPIF_RDY<3>" LOC = "N11" ; +NET "GPIF_RDY<2>" LOC = "T10" ; +NET "GPIF_RDY<1>" LOC = "T4" ; +NET "GPIF_RDY<0>" LOC = "R5" ; + +NET "FX2_PA7_FLAGD" LOC = "P12" ; +NET "FX2_PA6_PKTEND" LOC = "R11" ; +NET "FX2_PA2_SLOE" LOC = "P10" ; + +NET "IFCLK" LOC = "T8" ; + +## LEDs +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; + +## Debug bus +NET "debug_clk<0>" LOC = "K15" ; +NET "debug_clk<1>" LOC = "K14" ; +NET "debug<0>" LOC = "K16" ; +NET "debug<1>" LOC = "J16" ; +NET "debug<2>" LOC = "C16" ; +NET "debug<3>" LOC = "C15" ; +NET "debug<4>" LOC = "E13" ; +NET "debug<5>" LOC = "D14" ; +NET "debug<6>" LOC = "D16" ; +NET "debug<7>" LOC = "D15" ; +NET "debug<8>" LOC = "E14" ; +NET "debug<9>" LOC = "F13" ; +NET "debug<10>" LOC = "G13" ; +NET "debug<11>" LOC = "F14" ; +NET "debug<12>" LOC = "E16" ; +NET "debug<13>" LOC = "F15" ; +NET "debug<14>" LOC = "H13" ; +NET "debug<15>" LOC = "G14" ; +NET "debug<16>" LOC = "G16" ; +NET "debug<17>" LOC = "F16" ; +NET "debug<18>" LOC = "J12" ; +NET "debug<19>" LOC = "J13" ; +NET "debug<20>" LOC = "L14" ; +NET "debug<21>" LOC = "L16" ; +NET "debug<22>" LOC = "M15" ; +NET "debug<23>" LOC = "M16" ; +NET "debug<24>" LOC = "L13" ; +NET "debug<25>" LOC = "K13" ; +NET "debug<26>" LOC = "P16" ; +NET "debug<27>" LOC = "N16" ; +NET "debug<28>" LOC = "R15" ; +NET "debug<29>" LOC = "P15" ; +NET "debug<30>" LOC = "N13" ; +NET "debug<31>" LOC = "N14" ; + +## ADC +NET "adc<11>" LOC = "B15" ; +NET "adc<10>" LOC = "A8" ; +NET "adc<9>" LOC = "B8" ; +NET "adc<8>" LOC = "C8" ; +NET "adc<7>" LOC = "D8" ; +NET "adc<6>" LOC = "C9" ; +NET "adc<5>" LOC = "A9" ; +NET "adc<4>" LOC = "C10" ; +NET "adc<3>" LOC = "D9" ; +NET "adc<2>" LOC = "A3" ; +NET "adc<1>" LOC = "B3" ; +NET "adc<0>" LOC = "A4" ; +NET "RXSYNC" LOC = "D10" ; + +## DAC +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "dac<0>" LOC = "J1" ; +NET "dac<1>" LOC = "H3" ; +NET "dac<2>" LOC = "J3" ; +NET "dac<3>" LOC = "G2" ; +NET "dac<4>" LOC = "H1" ; +NET "dac<5>" LOC = "N3" ; +NET "dac<6>" LOC = "M4" ; +NET "dac<7>" LOC = "R1" ; +NET "dac<8>" LOC = "P2" ; +NET "dac<9>" LOC = "P1" ; +NET "dac<10>" LOC = "M1" ; +NET "dac<11>" LOC = "N1" ; +NET "dac<12>" LOC = "M3" ; +NET "dac<13>" LOC = "L4" ; + +## TX DB +NET "io_tx<0>" LOC = "K4" ; +NET "io_tx<1>" LOC = "L3" ; +NET "io_tx<2>" LOC = "L2" ; +NET "io_tx<3>" LOC = "F1" ; +NET "io_tx<4>" LOC = "F3" ; +NET "io_tx<5>" LOC = "G3" ; +NET "io_tx<6>" LOC = "E3" ; +NET "io_tx<7>" LOC = "E2" ; +NET "io_tx<8>" LOC = "E4" ; +NET "io_tx<9>" LOC = "F4" ; +NET "io_tx<10>" LOC = "D1" ; +NET "io_tx<11>" LOC = "E1" ; +NET "io_tx<12>" LOC = "D4" ; +NET "io_tx<13>" LOC = "D3" ; +NET "io_tx<14>" LOC = "C2" ; +NET "io_tx<15>" LOC = "C1" ; + +## RX DB +NET "io_rx<0>" LOC = "D7" ; +NET "io_rx<1>" LOC = "C6" ; +NET "io_rx<2>" LOC = "A6" ; +NET "io_rx<3>" LOC = "B6" ; +NET "io_rx<4>" LOC = "E9" ; +NET "io_rx<5>" LOC = "A7" ; +NET "io_rx<6>" LOC = "C7" ; +NET "io_rx<7>" LOC = "B10" ; +NET "io_rx<8>" LOC = "A10" ; +NET "io_rx<9>" LOC = "C11" ; +NET "io_rx<10>" LOC = "A11" ; +NET "io_rx<11>" LOC = "D11" ; +NET "io_rx<12>" LOC = "B12" ; +NET "io_rx<13>" LOC = "A12" ; +NET "io_rx<14>" LOC = "A14" ; +NET "io_rx<15>" LOC = "A13" ; + +## SPI +#NET "SEN_AUX" LOC = "C12" ; +#NET "SCLK_AUX" LOC = "D12" ; +#NET "MISO_AUX" LOC = "J5" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_CODEC" LOC = "G4" ; + +NET "MISO_RX_DB" LOC = "E6" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; + +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; + +## Dedicated pins +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; + +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "T15" ; diff --git a/fpga/usrp2/top/B100/u1plus.v b/fpga/usrp2/top/B100/u1plus.v new file mode 100644 index 000000000..5e3200580 --- /dev/null +++ b/fpga/usrp2/top/B100/u1plus.v @@ -0,0 +1,173 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1plus + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output FPGA_TXD, input FPGA_RXD, + + // GPIF + inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, + output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE, + input IFCLK, + + inout SDA_FPGA, inout SCL_FPGA, // I2C + + output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI + output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI + output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] dac, output TXSYNC, output TXBLANK, + input [11:0] adc, input RXSYNC, + + input PPS_IN, + input reset_n, output reset_codec + ); + + assign reset_codec = 1; // Believed to be active low + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, reset; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); + + reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0; + assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | + (~SEN_CODEC & MISO_CODEC); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // RX ADC -- handles deinterleaving + + reg [11:0] rx_i, rx_q; + wire [11:0] rx_a, rx_b; + + genvar j; + generate + for(j=0;j<12;j=j+1) + begin : gen_adcin + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock + .Q1(rx_b[j]), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(adc[j]), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_adcin + endgenerate + + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock + .Q1(rxsync_1), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(RXSYNC), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + always @(posedge clk_fpga) + if(rxsync_0) + begin + rx_i <= rx_b; + rx_q <= rx_a; + end + else + begin + rx_i <= rx_a; + rx_q <= rx_b; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), + .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}), + .gpif_clk(IFCLK), + + .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), + .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(rx_i), .rx_q(rx_q), + .pps_in(PPS_IN) ); + +endmodule // u1plus diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v new file mode 100644 index 000000000..8a02f0fb8 --- /dev/null +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -0,0 +1,409 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module u1plus_core + (input clk_fpga, input rst_fpga, + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPIF + inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + output [2:0] gpif_misc, input gpif_clk, + + inout db_sda, inout db_scl, + output sclk, output [15:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_underrun, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + input pps_in + ); + + localparam TXFIFOSIZE = 11; + localparam RXFIFOSIZE = 11; + + // 64 total regs in address space + localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) + localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) + localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) + localparam SR_TIME64 = 40; // 6 regs (+0 to +5) + localparam SR_CLEAR_RX_FIFO = 48; // 1 reg + localparam SR_CLEAR_TX_FIFO = 49; // 1 reg + localparam SR_GLOBAL_RESET = 50; // 1 reg + localparam SR_REG_TEST32 = 52; // 1 reg + + wire [7:0] COMPAT_NUM = 8'd3; + + wire wb_clk = clk_fpga; + wire wb_rst, global_reset; + + wire pps_int; + wire [63:0] vita_time, vita_time_pps; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire [31:0] debug0; + wire [31:0] debug1; + + wire [31:0] debug_vt; + wire gpif_rst; + + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + reg [7:0] frames_per_packet; + + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(global_reset)); + + reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); + wire [15:0] test_len; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPIF Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + + wire bus_error; + wire clear_tx, clear_rx; + + setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_rx)); + + setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpif (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d), + .gpif_ctl(gpif_ctl), .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), .triggers(8'd0), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy), + + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), + .debug0(debug0), .debug1(debug1)); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx; + wire strobe_rx, run_rx; + wire [31:0] debug_rx_dsp, vr_debug; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun_dsp), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .rx_data_o(rx_data), .rx_dst_rdy_i(rx_dst_rdy), .rx_src_rdy_o(rx_src_rdy), + .debug(vr_debug) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [15:0] tx_i_int, tx_q_int; + wire run_tx; + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .underrun(tx_underrun_dsp), .run(run_tx), + .debug(debug_vt)); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + xfer_rate <= 0; + frames_per_packet <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_RX_FRAMELEN : + frames_per_packet <= s0_dat_mosi[7:0]; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; + assign test_len = reg_test[15:0]; + + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #8 + 9 + + // only have 64 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi), + .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + // ///////////////////////////////////////////////////////////////////////// + // Readback mux 32 -- Slave #7 + + wire [31:0] reg_test32; + + setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(reg_test32),.changed()); + + wb_readback_mux_16LE readback_mux_32 + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + + .word00(vita_time[63:32]), .word01(vita_time[31:0]), + .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), + .word04(reg_test32), .word05(32'b0), + .word06(32'b0), .word07(32'b0), + .word08(32'b0), .word09(32'b0), + .word10(32'b0), .word11(32'b0), + .word12(32'b0), .word13(32'b0), + .word14(32'b0), .word15(32'b0) + ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { gpif_clk, clk_fpga }; + assign debug = debug0; + assign debug_gpio_0 = 0; + assign debug_gpio_1 = 0; + //assign {io_tx,io_rx} = {debug1}; + +endmodule // u1plus_core diff --git a/fpga/usrp2/top/u1e/.gitignore b/fpga/usrp2/top/E1x0/.gitignore index 8d872713e..8d872713e 100644 --- a/fpga/usrp2/top/u1e/.gitignore +++ b/fpga/usrp2/top/E1x0/.gitignore diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/E1x0/Makefile index 5d721979b..5d721979b 100644 --- a/fpga/usrp2/top/u1e/Makefile +++ b/fpga/usrp2/top/E1x0/Makefile diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/E1x0/Makefile.passthru index f2d835608..f2d835608 100644 --- a/fpga/usrp2/top/u1e_passthru/Makefile +++ b/fpga/usrp2/top/E1x0/Makefile.passthru diff --git a/fpga/usrp2/top/u1e/README b/fpga/usrp2/top/E1x0/README index 14c7a4955..14c7a4955 100644 --- a/fpga/usrp2/top/u1e/README +++ b/fpga/usrp2/top/E1x0/README diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/E1x0/cmdfile index 291c723b8..291c723b8 100644 --- a/fpga/usrp2/top/u1e/cmdfile +++ b/fpga/usrp2/top/E1x0/cmdfile diff --git a/fpga/usrp2/top/u1e/core_compile b/fpga/usrp2/top/E1x0/core_compile index dc0cd081e..dc0cd081e 100755 --- a/fpga/usrp2/top/u1e/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile diff --git a/fpga/usrp2/top/u1e/make.sim b/fpga/usrp2/top/E1x0/make.sim index 1c163884c..1c163884c 100644 --- a/fpga/usrp2/top/u1e/make.sim +++ b/fpga/usrp2/top/E1x0/make.sim diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/E1x0/passthru.ucf index 64e6f0440..64e6f0440 100644 --- a/fpga/usrp2/top/u1e_passthru/passthru.ucf +++ b/fpga/usrp2/top/E1x0/passthru.ucf diff --git a/fpga/usrp2/top/E1x0/passthru.v b/fpga/usrp2/top/E1x0/passthru.v new file mode 100644 index 000000000..486257366 --- /dev/null +++ b/fpga/usrp2/top/E1x0/passthru.v @@ -0,0 +1,35 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio145, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio145; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru diff --git a/fpga/usrp2/top/u1e/tb_u1e.v b/fpga/usrp2/top/E1x0/tb_u1e.v index 5fc8134fb..188190f04 100644 --- a/fpga/usrp2/top/u1e/tb_u1e.v +++ b/fpga/usrp2/top/E1x0/tb_u1e.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ps / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf index 8df28c9d3..8df28c9d3 100644 --- a/fpga/usrp2/top/u1e/timing.ucf +++ b/fpga/usrp2/top/E1x0/timing.ucf diff --git a/fpga/usrp2/top/u1e/u1e.ucf b/fpga/usrp2/top/E1x0/u1e.ucf index 0c487a601..0c487a601 100644 --- a/fpga/usrp2/top/u1e/u1e.ucf +++ b/fpga/usrp2/top/E1x0/u1e.ucf diff --git a/fpga/usrp2/top/u1e/u1e.v b/fpga/usrp2/top/E1x0/u1e.v index 445b14a03..adf42fd07 100644 --- a/fpga/usrp2/top/u1e/u1e.v +++ b/fpga/usrp2/top/E1x0/u1e.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v index d10a3ab30..4c513587b 100644 --- a/fpga/usrp2/top/u1e/u1e_core.v +++ b/fpga/usrp2/top/E1x0/u1e_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module u1e_core diff --git a/fpga/usrp2/top/u2plus/.gitignore b/fpga/usrp2/top/N2x0/.gitignore index 1b2211df0..1b2211df0 100644 --- a/fpga/usrp2/top/u2plus/.gitignore +++ b/fpga/usrp2/top/N2x0/.gitignore diff --git a/fpga/usrp2/top/u2plus/Makefile.N200 b/fpga/usrp2/top/N2x0/Makefile.N200R3 index 9175f9304..a525836ed 100644 --- a/fpga/usrp2/top/u2plus/Makefile.N200 +++ b/fpga/usrp2/top/N2x0/Makefile.N200R3 @@ -6,7 +6,7 @@ # Project Setup ################################################## TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200) +BUILD_DIR = $(abspath build$(ISE)-N200R3) ################################################## # Include other makefiles diff --git a/fpga/usrp2/top/u1e_ethdebug/Makefile b/fpga/usrp2/top/N2x0/Makefile.N200R4 index 751b52970..0ca40e1bd 100644 --- a/fpga/usrp2/top/u1e_ethdebug/Makefile +++ b/fpga/usrp2/top/N2x0/Makefile.N200R4 @@ -5,14 +5,26 @@ ################################################## # Project Setup ################################################## -TOP_MODULE = u1e -BUILD_DIR = $(abspath build$(ISE)) +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R4) ################################################## # Include other makefiles ################################################## include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties @@ -20,8 +32,8 @@ include ../Makefile.common export PROJECT_PROPERTIES := \ family "Spartan-3A DSP" \ device xc3sd1800a \ -package cs484 \ -speed -4 \ +package fg676 \ +speed -5 \ top_level_module_type "HDL" \ synthesis_tool "XST (VHDL/Verilog)" \ simulator "ISE Simulator (VHDL/Verilog)" \ @@ -33,10 +45,15 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -u1e.v \ -u1e.ucf +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf -SOURCES = $(abspath $(TOP_SRCS)) +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) ################################################## # Process Properties @@ -49,7 +66,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" @@ -77,7 +95,6 @@ GEN_PROG_FILE_PROPERTIES = \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" +"Enable Outputs (Output Events)" 6 SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/N2x0/Makefile.N210R3 index 38400ce62..e29251e1c 100644 --- a/fpga/usrp2/top/u2plus/Makefile +++ b/fpga/usrp2/top/N2x0/Makefile.N210R3 @@ -6,7 +6,7 @@ # Project Setup ################################################## TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)) +BUILD_DIR = $(abspath build$(ISE)-N210R3) ################################################## # Include other makefiles diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R4 b/fpga/usrp2/top/N2x0/Makefile.N210R4 new file mode 100644 index 000000000..01a9e19fd --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile.N210R4 @@ -0,0 +1,100 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R4) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/N2x0/bootloader.rmi index e5be670fb..e5be670fb 100644 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ b/fpga/usrp2/top/N2x0/bootloader.rmi diff --git a/fpga/usrp2/top/N2x0/capture_ddrlvds.v b/fpga/usrp2/top/N2x0/capture_ddrlvds.v new file mode 100644 index 000000000..e261dcbe8 --- /dev/null +++ b/fpga/usrp2/top/N2x0/capture_ddrlvds.v @@ -0,0 +1,55 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(posedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/N2x0/u2plus.ucf index 5fbe55c26..5fbe55c26 100755 --- a/fpga/usrp2/top/u2plus/u2plus.ucf +++ b/fpga/usrp2/top/N2x0/u2plus.ucf diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/N2x0/u2plus.v index 7c2270df6..be6cdeeca 100644 --- a/fpga/usrp2/top/u2plus/u2plus.v +++ b/fpga/usrp2/top/N2x0/u2plus.v @@ -1,4 +1,22 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps +//`define LVDS 1 //`define DCM_FOR_RAMCLK ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index ee5d7efcd..8a7c6ddee 100644 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // //////////////////////////////////////////////////////////////////////////////// // Module Name: u2_core // //////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u2_rev3/.gitignore b/fpga/usrp2/top/USRP2/.gitignore index f50a2b7e5..f50a2b7e5 100644 --- a/fpga/usrp2/top/u2_rev3/.gitignore +++ b/fpga/usrp2/top/USRP2/.gitignore diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/USRP2/Makefile index e9b43491a..e9b43491a 100644 --- a/fpga/usrp2/top/u2_rev3/Makefile +++ b/fpga/usrp2/top/USRP2/Makefile diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index 0e6120ec6..ca9762ac5 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // //////////////////////////////////////////////////////////////////////////////// // Module Name: u2_core // //////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/USRP2/u2_rev3.ucf index 8017f61ff..8017f61ff 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/fpga/usrp2/top/USRP2/u2_rev3.ucf diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/USRP2/u2_rev3.v index bc7ae5f16..4b0bb5541 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.v +++ b/fpga/usrp2/top/USRP2/u2_rev3.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/eth_test/.gitignore b/fpga/usrp2/top/eth_test/.gitignore deleted file mode 100644 index b30397081..000000000 --- a/fpga/usrp2/top/eth_test/.gitignore +++ /dev/null @@ -1,43 +0,0 @@ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/fpga/usrp2/top/eth_test/eth_sim_top.v b/fpga/usrp2/top/eth_test/eth_sim_top.v deleted file mode 100644 index 640a4e60f..000000000 --- a/fpga/usrp2/top/eth_test/eth_sim_top.v +++ /dev/null @@ -1,437 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_basic -////////////////////////////////////////////////////////////////////////////////// - -module eth_sim_top - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output led1, - output led2, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - input PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] ser_debug; - - ////////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - parameter dw = 32; // Data bus width - parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i; - wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; - wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel; - wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack; - wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb; - wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc; - wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err; - wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty; - wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we; - - wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01), - .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010), - .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty) - ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we; - wire [3:0] iram_wr_sel; - wire [aw-1:0] iram_wr_adr, iram_rd_adr; - wire [dw-1:0] iram_wr_dat, iram_rd_dat; - - wire bus_error, proc_int; - - assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0; - assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack; - - ram_loader #(.AWIDTH(16)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start), - .mode_o(cpld_mode), - .done_o(cpld_done), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr), - .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel), - .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr), - .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - assign proc_int = 1'b0; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - ram_wb_harvard #(.AWIDTH(14)) - ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat), - .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb), - .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel), - - .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - // Buffer Pool, slave #1 - wire rd0_read, rd0_ready, rd0_done, rd0_empty; - wire rd1_read, rd1_ready, rd1_done, rd1_empty; - wire rd2_read, rd2_ready, rd2_done, rd2_empty; - wire rd3_read, rd3_ready, rd3_done, rd3_empty; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - -/* - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk),.stream_rst(dsp_rst), - // Write Interfaces - .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(), - .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(), - .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(), - .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(), - // Read Interfaces - .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty), - .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty), - .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty), - .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty) - ); -*/ - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i), - .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack), - - .wb_err_o(s2_err),.wb_int_o(s2_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(st_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d; - assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d; - - simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a), - .gpio(/* io_tx[7:0]*/) ); - - simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b), - .gpio(/* io_tx[15:8] */) ); - - simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c), - .gpio(/* io_rx[7:0] */) ); - - simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d), - .gpio(/* io_rx[15:8]*/) ); - - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Output control lines, SLAVE #5 - wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0]; - assign {led2, led1} = misc_outs[1:0]; - - wb_output_pins32 control_lines - (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i), - .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc), - .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Ethernet slave, #6 - eth_wrapper eth_wrapper - (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(), - .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode - .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER), - .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - // FIFO Interfaces - .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(), - .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(), - // Wishbone - .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack) - ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - /////////////////////////////////////////////////////////////////////////// - // DSP - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_a; - adc_a_reg2 <= adc_a_reg1; - adc_b_reg1 <= adc_b; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg1 <= adc_ovf_b; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done), - .rx_ready_i(wr1_ready),.rx_full_i(wr1_full), - .overrun() ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done), - .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty), - .underrun() ); - - assign dsp_rst = wb_rst; - - ///////////////////////////////////////////////////////////////////////////////////// - // SERDES - serdes_tx serdes_tx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done), - .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty) - ); - - serdes_rx serdes_rx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done) - ); - - // Debug Pins - wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst}, - {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached}, - {8'hAF}, - {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}}; - - wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst}, - {iram_rd_adr[15:8]}, - {iram_rd_adr[7:0]}, - {serdes_outs}}; - - assign io_rx = ser_debug[31:16]; - assign io_tx = ser_debug[15:0]; - - assign debug = debug_wb; - - assign debug_clk[0] = wb_clk; - assign debug_clk[1] = dsp_clk; - -endmodule // eth_test - - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v") -// verilog-library-extensions:(".v" ".h") -// End: diff --git a/fpga/usrp2/top/eth_test/eth_tb.v b/fpga/usrp2/top/eth_test/eth_tb.v deleted file mode 100644 index 451ce1e7e..000000000 --- a/fpga/usrp2/top/eth_test/eth_tb.v +++ /dev/null @@ -1,257 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -// Nearly everything is an input - -module eth_tb(); - // Misc, debug - wire led1; - wire led2; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_oen_a; - wire adc_pdn_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_oen_b; - wire adc_pdn_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - wire clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk, wb_rst; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #7 clk_fpga = ~clk_fpga; - - - wire div_clk; - reg [2:0] div_ctr = 0; - - always @(posedge clk_fpga or negedge clk_fpga) - if(div_ctr==5) - div_ctr = 0; - else - div_ctr = div_ctr + 1; - assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2); - - assign dsp_clk = clk_fpga; - assign wb_clk = clock_ready ? div_clk : aux_clk; - - initial - $monitor($time, ,clock_ready); - - initial begin - $dumpfile("eth_tb.vcd"); - $dumpvars(0,eth_tb); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - eth_sim_top eth_sim_top(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .led1 (led1), - .led2 (led2), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_oen_a (adc_oen_a), - .adc_pdn_a (adc_pdn_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_oen_b (adc_oen_b), - .adc_pdn_b (adc_pdn_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0])); - - // Experimental printf-like function - always @(posedge wb_clk) - begin - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000)) - $write("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100)) - $display("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004)) - $write("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104)) - $display("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008)) - $display(""); - end - - -endmodule // u2_sim_top - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v") -// verilog-library-extensions:(".v" ".h") -// End: diff --git a/fpga/usrp2/top/safe_u2plus/.gitignore b/fpga/usrp2/top/safe_u2plus/.gitignore deleted file mode 100644 index a96f0be92..000000000 --- a/fpga/usrp2/top/safe_u2plus/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -build* -*impact* diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile deleted file mode 100644 index b72241050..000000000 --- a/fpga/usrp2/top/safe_u2plus/Makefile +++ /dev/null @@ -1,245 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u2plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2plus/capture_ddrlvds.v \ -top/safe_u2plus/u2plus.ucf \ -top/safe_u2plus/safe_u2plus.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v deleted file mode 100644 index dca9688c5..000000000 --- a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [5:1] leds, // LED4 is shared w/INIT_B - output ETH_LED - ); - - wire clk_fpga; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - reg [31:0] ctr; - - always @(posedge clk_fpga) - ctr <= ctr + 1; - - assign {leds,ETH_LED} = ~ctr[29:24]; - -endmodule // safe_u2plus diff --git a/fpga/usrp2/top/safe_u2plus/u2plus.ucf b/fpga/usrp2/top/safe_u2plus/u2plus.ucf deleted file mode 100755 index 0a9460d86..000000000 --- a/fpga/usrp2/top/safe_u2plus/u2plus.ucf +++ /dev/null @@ -1,401 +0,0 @@ -## Main 100 MHz Clock -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; - -## ADC -#NET "ADC_clkout_p" LOC = "P1" ; -#NET "ADC_clkout_n" LOC = "P2" ; -#NET "ADCA_12_p" LOC = "Y1" ; -#NET "ADCA_12_n" LOC = "Y2" ; -#NET "ADCA_10_p" LOC = "W3" ; -#NET "ADCA_10_n" LOC = "W4" ; -#NET "ADCA_8_p" LOC = "T7" ; -#NET "ADCA_8_n" LOC = "U6" ; -#NET "ADCA_6_p" LOC = "U5" ; -#NET "ADCA_6_n" LOC = "V5" ; -#NET "ADCA_4_p" LOC = "T10" ; -#NET "ADCA_4_n" LOC = "T9" ; -#NET "ADCA_2_p" LOC = "V1" ; -#NET "ADCA_2_n" LOC = "V2" ; -#NET "ADCA_0_p" LOC = "R8" ; -#NET "ADCA_0_n" LOC = "R7" ; -#NET "ADCB_2_p" LOC = "U7" ; -#NET "ADCB_2_n" LOC = "U8" ; -#NET "ADCB_0_p" LOC = "AA2" ; -#NET "ADCB_0_n" LOC = "AA3" ; -#NET "ADCB_4_p" LOC = "AE1" ; -#NET "ADCB_4_n" LOC = "AE2" ; -#NET "ADCB_6_p" LOC = "W1" ; -#NET "ADCB_6_n" LOC = "W2" ; -#NET "ADCB_8_p" LOC = "U3" ; -#NET "ADCB_8_n" LOC = "V4" ; -#NET "ADCB_10_p" LOC = "J1" ; -#NET "ADCB_10_n" LOC = "K1" ; -#NET "ADCB_12_p" LOC = "J3" ; -#NET "ADCB_12_n" LOC = "J2" ; - -## DAC -#NET "DAC_LOCK" LOC = "P4" ; -#NET "DACA<0>" LOC = "P8" ; -#NET "DACA<1>" LOC = "P9" ; -#NET "DACA<2>" LOC = "R5" ; -#NET "DACA<3>" LOC = "R6" ; -#NET "DACA<4>" LOC = "P7" ; -#NET "DACA<5>" LOC = "P6" ; -#NET "DACA<6>" LOC = "T3" ; -#NET "DACA<7>" LOC = "T4" ; -#NET "DACA<8>" LOC = "R3" ; -#NET "DACA<9>" LOC = "R4" ; -#NET "DACA<10>" LOC = "R2" ; -#NET "DACA<11>" LOC = "N1" ; -#NET "DACA<12>" LOC = "N2" ; -#NET "DACA<13>" LOC = "N5" ; -#NET "DACA<14>" LOC = "N4" ; -#NET "DACA<15>" LOC = "M2" ; -#NET "DACB<0>" LOC = "M5" ; -#NET "DACB<1>" LOC = "M6" ; -#NET "DACB<2>" LOC = "M4" ; -#NET "DACB<3>" LOC = "M3" ; -#NET "DACB<4>" LOC = "M8" ; -#NET "DACB<5>" LOC = "M7" ; -#NET "DACB<6>" LOC = "L4" ; -#NET "DACB<7>" LOC = "L3" ; -#NET "DACB<8>" LOC = "K3" ; -#NET "DACB<9>" LOC = "K2" ; -#NET "DACB<10>" LOC = "K5" ; -#NET "DACB<11>" LOC = "K4" ; -#NET "DACB<12>" LOC = "M10" ; -#NET "DACB<13>" LOC = "M9" ; -#NET "DACB<14>" LOC = "J5" ; -#NET "DACB<15>" LOC = "J4" ; - -## TX DB GPIO -#NET "io_tx<15>" LOC = "K6" ; -#NET "io_tx<14>" LOC = "L7" ; -#NET "io_tx<13>" LOC = "H2" ; -#NET "io_tx<12>" LOC = "H1" ; -#NET "io_tx<11>" LOC = "L10" ; -#NET "io_tx<10>" LOC = "L9" ; -#NET "io_tx<9>" LOC = "G3" ; -#NET "io_tx<8>" LOC = "F3" ; -#NET "io_tx<7>" LOC = "K7" ; -#NET "io_tx<6>" LOC = "J6" ; -#NET "io_tx<5>" LOC = "E1" ; -#NET "io_tx<4>" LOC = "F2" ; -#NET "io_tx<3>" LOC = "J7" ; -#NET "io_tx<2>" LOC = "H6" ; -#NET "io_tx<1>" LOC = "F5" ; -#NET "io_tx<0>" LOC = "G4" ; - -## RX DB GPIO -#NET "io_rx<15>" LOC = "AD1" ; -#NET "io_rx<14>" LOC = "AD2" ; -#NET "io_rx<13>" LOC = "AC2" ; -#NET "io_rx<12>" LOC = "AC3" ; -#NET "io_rx<11>" LOC = "W7" ; -#NET "io_rx<10>" LOC = "W6" ; -#NET "io_rx<9>" LOC = "U9" ; -#NET "io_rx<8>" LOC = "V8" ; -#NET "io_rx<7>" LOC = "AB1" ; -#NET "io_rx<6>" LOC = "AC1" ; -#NET "io_rx<5>" LOC = "V7" ; -#NET "io_rx<4>" LOC = "V6" ; -#NET "io_rx<3>" LOC = "Y5" ; -#NET "io_rx<2>" LOC = "R10" ; -#NET "io_rx<1>" LOC = "R1" ; -#NET "io_rx<0>" LOC = "M1" ; - -## MISC -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -#NET "FPGA_RESET" LOC = "K24" ; - -## Debug -#NET "debug_clk<0>" LOC = "AA10" ; -#NET "debug_clk<1>" LOC = "AD11" ; -#NET "debug<0>" LOC = "AC19" ; -#NET "debug<1>" LOC = "AF20" ; -#NET "debug<2>" LOC = "AE20" ; -#NET "debug<3>" LOC = "AC16" ; -#NET "debug<4>" LOC = "AB16" ; -#NET "debug<5>" LOC = "AF19" ; -#NET "debug<6>" LOC = "AE19" ; -#NET "debug<7>" LOC = "V15" ; -#NET "debug<8>" LOC = "U15" ; -#NET "debug<9>" LOC = "AE17" ; -#NET "debug<10>" LOC = "AD17" ; -#NET "debug<11>" LOC = "V14" ; -#NET "debug<12>" LOC = "W15" ; -#NET "debug<13>" LOC = "AC15" ; -#NET "debug<14>" LOC = "AD14" ; -#NET "debug<15>" LOC = "AC14" ; -#NET "debug<16>" LOC = "AC11" ; -#NET "debug<17>" LOC = "AB12" ; -#NET "debug<18>" LOC = "AC12" ; -#NET "debug<19>" LOC = "V13" ; -#NET "debug<20>" LOC = "W13" ; -#NET "debug<21>" LOC = "AE8" ; -#NET "debug<22>" LOC = "AF8" ; -#NET "debug<23>" LOC = "V12" ; -#NET "debug<24>" LOC = "W12" ; -#NET "debug<25>" LOC = "AB9" ; -#NET "debug<26>" LOC = "AC9" ; -#NET "debug<27>" LOC = "AC8" ; -#NET "debug<28>" LOC = "AB7" ; -#NET "debug<29>" LOC = "V11" ; -#NET "debug<30>" LOC = "U11" ; -#NET "debug<31>" LOC = "Y10" ; - -## UARTS -#NET "TXD<3>" LOC = "AD20" ; -#NET "TXD<2>" LOC = "AC20" ; -#NET "TXD<1>" LOC = "AD19" ; -#NET "RXD<3>" LOC = "AF17" ; -#NET "RXD<2>" LOC = "AF15" ; -#NET "RXD<1>" LOC = "AD12" ; - -## AD9510 -#NET "CLK_STATUS" LOC = "AD22" ; -#NET "CLK_FUNC" LOC = "AC21" ; -#NET "clk_sel<0>" LOC = "AE21" ; -#NET "clk_sel<1>" LOC = "AD21" ; -#NET "clk_en<1>" LOC = "AA17" ; -#NET "clk_en<0>" LOC = "Y17" ; - -## I2C -#NET "SDA" LOC = "V16" ; -#NET "SCL" LOC = "U16" ; - -## Timing -#NET "PPS_IN" LOC = "AB6" ; -#NET "PPS2_IN" LOC = "AA20" ; - -## SPI -#NET "SEN_CLK" LOC = "AA18" ; -#NET "MOSI_CLK" LOC = "W17" ; -#NET "SCLK_CLK" LOC = "V17" ; -#NET "MISO_CLK" LOC = "AC10" ; - -#NET "SEN_DAC" LOC = "AE7" ; -#NET "SCLK_DAC" LOC = "AF5" ; -#NET "MOSI_DAC" LOC = "AE6" ; -#NET "MISO_DAC" LOC = "Y3" ; - -#NET "SCLK_ADC" LOC = "B1" ; -#NET "MOSI_ADC" LOC = "J8" ; -#NET "SEN_ADC" LOC = "J9" ; - -#NET "MOSI_TX_ADC" LOC = "V10" ; -#NET "SEN_TX_ADC" LOC = "W10" ; -#NET "SCLK_TX_ADC" LOC = "AC6" ; -#NET "MISO_TX_ADC" LOC = "G1" ; - -#NET "MOSI_TX_DAC" LOC = "AD6" ; -#NET "SEN_TX_DAC" LOC = "AE4" ; -#NET "SCLK_TX_DAC" LOC = "AF4" ; - -#NET "SCLK_TX_DB" LOC = "AE3" ; -#NET "MOSI_TX_DB" LOC = "AF3" ; -#NET "SEN_TX_DB" LOC = "W9" ; -#NET "MISO_TX_DB" LOC = "AA5" ; - -#NET "MOSI_RX_ADC" LOC = "E3" ; -#NET "SCLK_RX_ADC" LOC = "F4" ; -#NET "SEN_RX_ADC" LOC = "D3" ; -#NET "MISO_RX_ADC" LOC = "C1" ; - -#NET "SCLK_RX_DAC" LOC = "E4" ; -#NET "SEN_RX_DAC" LOC = "K9" ; -#NET "MOSI_RX_DAC" LOC = "K8" ; - -#NET "SCLK_RX_DB" LOC = "G6" ; -#NET "MOSI_RX_DB" LOC = "H7" ; -#NET "SEN_RX_DB" LOC = "B2" ; -#NET "MISO_RX_DB" LOC = "H4" ; - -## ETH PHY -#NET "CLK_TO_MAC" LOC = "P26" ; - -#NET "GMII_TXD<7>" LOC = "G21" ; -#NET "GMII_TXD<6>" LOC = "C26" ; -#NET "GMII_TXD<5>" LOC = "C25" ; -#NET "GMII_TXD<4>" LOC = "J21" ; -#NET "GMII_TXD<3>" LOC = "H21" ; -#NET "GMII_TXD<2>" LOC = "D25" ; -#NET "GMII_TXD<1>" LOC = "D24" ; -#NET "GMII_TXD<0>" LOC = "E26" ; -#NET "GMII_TX_EN" LOC = "D26" ; -#NET "GMII_TX_ER" LOC = "J19" ; -#NET "GMII_GTX_CLK" LOC = "J20" ; -#NET "GMII_TX_CLK" LOC = "P25" ; - -#NET "GMII_RX_CLK" LOC = "P21" ; -#NET "GMII_RXD<7>" LOC = "G22" ; -#NET "GMII_RXD<6>" LOC = "K19" ; -#NET "GMII_RXD<5>" LOC = "K18" ; -#NET "GMII_RXD<4>" LOC = "E24" ; -#NET "GMII_RXD<3>" LOC = "F23" ; -#NET "GMII_RXD<2>" LOC = "L18" ; -#NET "GMII_RXD<1>" LOC = "L17" ; -#NET "GMII_RXD<0>" LOC = "F25" ; -#NET "GMII_RX_DV" LOC = "F24" ; -#NET "GMII_RX_ER" LOC = "L20" ; -#NET "GMII_CRS" LOC = "K20" ; -#NET "GMII_COL" LOC = "G23" ; - -#NET "PHY_INTn" LOC = "L22" ; -#NET "MDIO" LOC = "K21" ; -#NET "MDC" LOC = "J23" ; -#NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" ; - -## MIMO Interface -#NET "exp_time_out_p" LOC = "Y14" ; -#NET "exp_time_out_n" LOC = "AA14" ; -#NET "exp_time_in_p" LOC = "N18" ; -#NET "exp_time_in_n" LOC = "N17" ; -#NET "exp_user_out_p" LOC = "AF14" ; -#NET "exp_user_out_n" LOC = "AE14" ; -#NET "exp_user_in_p" LOC = "L24" ; -#NET "exp_user_in_n" LOC = "M23" ; - -## SERDES -#NET "ser_enable" LOC = "R20" ; -#NET "ser_prbsen" LOC = "U23" ; -#NET "ser_loopen" LOC = "R19" ; -#NET "ser_rx_en" LOC = "Y21" ; -#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -#NET "ser_t<15>" LOC = "V23" ; -#NET "ser_t<14>" LOC = "U22" ; -#NET "ser_t<13>" LOC = "V24" ; -#NET "ser_t<12>" LOC = "V25" ; -#NET "ser_t<11>" LOC = "W23" ; -#NET "ser_t<10>" LOC = "V22" ; -#NET "ser_t<9>" LOC = "T18" ; -#NET "ser_t<8>" LOC = "T17" ; -#NET "ser_t<7>" LOC = "Y24" ; -#NET "ser_t<6>" LOC = "Y25" ; -#NET "ser_t<5>" LOC = "U21" ; -#NET "ser_t<4>" LOC = "T20" ; -#NET "ser_t<3>" LOC = "Y22" ; -#NET "ser_t<2>" LOC = "Y23" ; -#NET "ser_t<1>" LOC = "U19" ; -#NET "ser_t<0>" LOC = "U18" ; -#NET "ser_tkmsb" LOC = "AA24" ; -#NET "ser_tklsb" LOC = "AA25" ; -#NET "ser_rx_clk" LOC = "P18" ; -#NET "ser_r<15>" LOC = "V21" ; -#NET "ser_r<14>" LOC = "U20" ; -#NET "ser_r<13>" LOC = "AA22" ; -#NET "ser_r<12>" LOC = "AA23" ; -#NET "ser_r<11>" LOC = "V18" ; -#NET "ser_r<10>" LOC = "V19" ; -#NET "ser_r<9>" LOC = "AB23" ; -#NET "ser_r<8>" LOC = "AC26" ; -#NET "ser_r<7>" LOC = "AB26" ; -#NET "ser_r<6>" LOC = "AD26" ; -#NET "ser_r<5>" LOC = "AC25" ; -#NET "ser_r<4>" LOC = "W20" ; -#NET "ser_r<3>" LOC = "W21" ; -#NET "ser_r<2>" LOC = "AC23" ; -#NET "ser_r<1>" LOC = "AC24" ; -#NET "ser_r<0>" LOC = "AE26" ; -#NET "ser_rkmsb" LOC = "AD25" ; -#NET "ser_rklsb" LOC = "Y20" ; - -## SRAM -#NET "RAM_D<35>" LOC = "K16" ; -#NET "RAM_D<34>" LOC = "D20" ; -#NET "RAM_D<33>" LOC = "C20" ; -#NET "RAM_D<32>" LOC = "E21" ; -#NET "RAM_D<31>" LOC = "D21" ; -#NET "RAM_D<30>" LOC = "C21" ; -#NET "RAM_D<29>" LOC = "B21" ; -#NET "RAM_D<28>" LOC = "H17" ; -#NET "RAM_D<27>" LOC = "G17" ; -#NET "RAM_D<26>" LOC = "B23" ; -#NET "RAM_D<25>" LOC = "A22" ; -#NET "RAM_D<24>" LOC = "D23" ; -#NET "RAM_D<23>" LOC = "C23" ; -#NET "RAM_D<22>" LOC = "D22" ; -#NET "RAM_D<21>" LOC = "C22" ; -#NET "RAM_D<20>" LOC = "F19" ; -#NET "RAM_D<19>" LOC = "G20" ; -#NET "RAM_D<18>" LOC = "F20" ; -#NET "RAM_D<17>" LOC = "F7" ; -#NET "RAM_D<16>" LOC = "E7" ; -#NET "RAM_D<15>" LOC = "G9" ; -#NET "RAM_D<14>" LOC = "H9" ; -#NET "RAM_D<13>" LOC = "G10" ; -#NET "RAM_D<12>" LOC = "H10" ; -#NET "RAM_D<11>" LOC = "A4" ; -#NET "RAM_D<10>" LOC = "B4" ; -#NET "RAM_D<9>" LOC = "C5" ; -#NET "RAM_D<8>" LOC = "D6" ; -#NET "RAM_D<7>" LOC = "J11" ; -#NET "RAM_D<6>" LOC = "K11" ; -#NET "RAM_D<5>" LOC = "B7" ; -#NET "RAM_D<4>" LOC = "C7" ; -#NET "RAM_D<3>" LOC = "B6" ; -#NET "RAM_D<2>" LOC = "C6" ; -#NET "RAM_D<1>" LOC = "C8" ; -#NET "RAM_D<0>" LOC = "D8" ; -#NET "RAM_A<0>" LOC = "C11" ; -#NET "RAM_A<1>" LOC = "E12" ; -#NET "RAM_A<2>" LOC = "F12" ; -#NET "RAM_A<3>" LOC = "D13" ; -#NET "RAM_A<4>" LOC = "C12" ; -#NET "RAM_A<5>" LOC = "A12" ; -#NET "RAM_A<6>" LOC = "B12" ; -#NET "RAM_A<7>" LOC = "E14" ; -#NET "RAM_A<8>" LOC = "F14" ; -#NET "RAM_A<9>" LOC = "B15" ; -#NET "RAM_A<10>" LOC = "A15" ; -#NET "RAM_A<11>" LOC = "D16" ; -#NET "RAM_A<12>" LOC = "C15" ; -#NET "RAM_A<13>" LOC = "D17" ; -#NET "RAM_A<14>" LOC = "C16" ; -#NET "RAM_A<15>" LOC = "F15" ; -#NET "RAM_A<16>" LOC = "C17" ; -#NET "RAM_A<17>" LOC = "B17" ; -#NET "RAM_A<18>" LOC = "B18" ; -#NET "RAM_A<19>" LOC = "A18" ; -#NET "RAM_A<20>" LOC = "D18" ; -#NET "RAM_BWn<3>" LOC = "D9" ; -#NET "RAM_BWn<2>" LOC = "A9" ; -#NET "RAM_BWn<1>" LOC = "B9" ; -#NET "RAM_BWn<0>" LOC = "G12" ; -#NET "RAM_ZZ" LOC = "J12" ; -#NET "RAM_LDn" LOC = "H12" ; -#NET "RAM_OEn" LOC = "C10" ; -#NET "RAM_WEn" LOC = "D10" ; -#NET "RAM_CENn" LOC = "B10" ; -#NET "RAM_CLK" LOC = "A10" ; - -## SPI Flash -#NET "flash_miso" LOC = "AF24" ; -#NET "flash_clk" LOC = "AE24" ; -#NET "flash_mosi" LOC = "AB15" ; -#NET "flash_cs" LOC = "AA7" ; - -## MISC FPGA, unused for now -##NET "PROG_B" LOC = "A2" ; -##NET "PUDC_B" LOC = "G8" ; -##NET "DONE" LOC = "AB21" ; -##NET "INIT_B" LOC = "AA15" ; - - -##NET "unnamed_net19" LOC = "AE9" ; # VS1 -##NET "unnamed_net18" LOC = "AF9" ; # VS0 -##NET "unnamed_net17" LOC = "AA12" ; # VS2 -##NET "unnamed_net16" LOC = "Y7" ; # M2 -##NET "unnamed_net15" LOC = "AC4" ; # M1 -##NET "unnamed_net14" LOC = "AD4" ; # M0 -##NET "unnamed_net13" LOC = "D4" ; # TMS -##NET "unnamed_net12" LOC = "E23" ; # TDO -##NET "unnamed_net11" LOC = "G7" ; # TDI -##NET "unnamed_net10" LOC = "A25" ; # TCK -##NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/fpga/usrp2/top/single_u2_sim/single_u2_sim.v b/fpga/usrp2/top/single_u2_sim/single_u2_sim.v deleted file mode 100644 index 2a7b24849..000000000 --- a/fpga/usrp2/top/single_u2_sim/single_u2_sim.v +++ /dev/null @@ -1,324 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module single_u2_sim(); - // Misc, debug - wire [7:0] leds; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_on_a, adc_oe_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_on_b, adc_oe_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - reg clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #6 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #5 clk_fpga = ~clk_fpga; - - initial clk_to_mac = 0; - always #4 clk_to_mac = ~clk_to_mac; - - wire div_clk, dsp_clk; - reg [7:0] div_ctr = 0; - - assign dsp_clk = clock_ready ? clk_fpga : aux_clk; - assign wb_clk = div_clk; - -`define CLK_DIV_2 1 -//`define CLK_DIV_3 - -`ifdef CLK_DIV_2 - localparam clock_divider = 4'd2; - always @(posedge dsp_clk) - div_ctr <= div_ctr + 1; - assign div_clk = div_ctr[0]; -`endif - -`ifdef CLK_DIV_3 - localparam clock_divider = 2; - always @(posedge dsp_clk or negedge dsp_clk) - if(div_ctr == 5) - div_ctr <= 0; - else - div_ctr <= div_ctr + 1; - assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); -`endif - - initial - $monitor($time, ,clock_ready); - - always #1000000 $monitor("Time in ns ",$time); - - initial begin - @(negedge cpld_done); - @(posedge cpld_done); - $dumpfile("single_u2_sim.lxt"); - $dumpvars(0,single_u2_sim); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - serdes_model serdes_model - (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), - .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), - .even(0),.error(0) ); - - adc_model adc_model - (.clk(dsp_clk),.rst(0), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); - - wire [2:0] speed; - phy_sim phy_model - (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), - .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), - .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), - .Crs(GMII_CRS), .Col(GMII_COL), - .Speed(speed), .Done(0) ); - pullup p3(MDIO); - - miim_model miim_model - (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), - .phy_intn_o(PHY_INTn),.speed_o(speed) ); - - xlnx_glbl glbl (.GSR(),.GTS()); - - wire RAM_MODE = 1'b0; - cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), - .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), - .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), - .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); - - M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), - .SDA(SDA),.SCL(SCL),.RESET(0)); - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o; - wire sda_pad_i, sda_pad_o, sda_pad_oen_o; - - pullup p1(SCL); - pullup p2(SDA); - - assign scl_pad_i = SCL; - assign sda_pad_i = SDA; - - assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; - assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; - - // printf output - wire uart_baud_o, uart_tx_o, uart_rx_i; - assign uart_rx_i = 1'b1; - - uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); - - // End the simulation - always @(posedge wb_clk) - if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) - begin - $display($time, "Finish called.",); - $finish; - end - - u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_init_b (1), - .por (0), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (uart_baud_o), - .sim_mode (1'b1), - .clock_divider (clock_divider) - ); - -endmodule // single_u2_sim diff --git a/fpga/usrp2/top/tcl/ise_helper.tcl b/fpga/usrp2/top/tcl/ise_helper.tcl index a4bee76b8..f11596f8b 100644 --- a/fpga/usrp2/top/tcl/ise_helper.tcl +++ b/fpga/usrp2/top/tcl/ise_helper.tcl @@ -1,8 +1,6 @@ # # Copyright 2008 Ettus Research LLC # -# This file is part of GNU Radio -# # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 3, or (at your option) diff --git a/fpga/usrp2/top/u1e_ethdebug/.gitignore b/fpga/usrp2/top/u1e_ethdebug/.gitignore deleted file mode 100644 index 8d872713e..000000000 --- a/fpga/usrp2/top/u1e_ethdebug/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -build -*.log -*.cmd -tb_u1e -*.lxt diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf deleted file mode 100644 index d6a2ea4ed..000000000 --- a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf +++ /dev/null @@ -1,88 +0,0 @@ - -## GPMC -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -NET "EM_NCS6" LOC = "E17" ; -NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_CLK" LOC = "F11" ; -NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE<1>" LOC = "D14" ; -#NET "EM_NBE<0>" LOC = "A13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_NWP" LOC = "F13" ; -NET "overo_gpio64" LOC = "A4" ; # nRESET -NET "overo_gpio176" LOC = "B4" ; # IRQ - -## Debug pins -NET "debug_led<3>" LOC = "Y15" ; -NET "debug_led<2>" LOC = "K16" ; -NET "debug_led<1>" LOC = "J17" ; -NET "debug_led<0>" LOC = "H22" ; -NET "debug<0>" LOC = "G22" ; -NET "debug<1>" LOC = "H17" ; -NET "debug<2>" LOC = "H18" ; -NET "debug<3>" LOC = "K20" ; -NET "debug<4>" LOC = "J20" ; -NET "debug<5>" LOC = "K19" ; -NET "debug<6>" LOC = "K18" ; -NET "debug<7>" LOC = "L22" ; -NET "debug<8>" LOC = "K22" ; -NET "debug<9>" LOC = "N22" ; -NET "debug<10>" LOC = "M22" ; -NET "debug<11>" LOC = "N20" ; -NET "debug<12>" LOC = "N19" ; -NET "debug<13>" LOC = "R22" ; -NET "debug<14>" LOC = "P22" ; -NET "debug<15>" LOC = "N17" ; -NET "debug<16>" LOC = "P16" ; -NET "debug<17>" LOC = "U22" ; -NET "debug<18>" LOC = "P19" ; -NET "debug<19>" LOC = "R18" ; -NET "debug<20>" LOC = "U20" ; -NET "debug<21>" LOC = "T20" ; -NET "debug<22>" LOC = "R19" ; -NET "debug<23>" LOC = "R20" ; -NET "debug<24>" LOC = "W22" ; -NET "debug<25>" LOC = "Y22" ; -NET "debug<26>" LOC = "T18" ; -NET "debug<27>" LOC = "T17" ; -NET "debug<28>" LOC = "W19" ; -NET "debug<29>" LOC = "V20" ; -NET "debug<30>" LOC = "Y21" ; -NET "debug<31>" LOC = "AA22" ; -NET "debug_clk<0>" LOC = "N18" ; -NET "debug_clk<1>" LOC = "M17" ; - -NET "debug_pb" LOC = "C22" ; diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.v b/fpga/usrp2/top/u1e_ethdebug/u1e.v deleted file mode 100644 index 2a543a313..000000000 --- a/fpga/usrp2/top/u1e_ethdebug/u1e.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -//`define DCM 1 - -module u1e - (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input debug_pb, - - // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, - input EM_NADV_ALE, - - input overo_gpio64, input overo_gpio176 - ); - - assign debug_clk = {EM_CLK, EM_NADV_ALE}; - - assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; - - assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, - { EM_A[10], EM_A[7:1] }, - { EM_D[15:8] }, - { EM_D[7:0] } }; - - -endmodule // u1e diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v deleted file mode 100644 index 12e4db017..000000000 --- a/fpga/usrp2/top/u1e_passthru/passthru.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module passthru - (input overo_gpio145, - output cgen_sclk, - output cgen_sen_b, - output cgen_mosi, - input fpga_cfg_din, - input fpga_cfg_cclk - ); - - assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio145; - assign cgen_mosi = fpga_cfg_din; - - -endmodule // passthru diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile deleted file mode 100644 index 334089839..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile +++ /dev/null @@ -1,253 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_2rx_iad/u2_core.v \ -top/u2_rev3_2rx_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/README b/fpga/usrp2/top/u2_rev3_2rx_iad/README deleted file mode 100644 index 3efc5305b..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/README +++ /dev/null @@ -1,32 +0,0 @@ -This is a custom build for USRP2 FPGA. It allows using a BasicRX or -LFRX board and feed two independent, real signals. In addition, instead -of the CIC/HB decimator, which optimizes frequency response, it uses an -integrate and dump decimator, which optimizes for time-domain impulse -response. - -These changes have been made in dsp_core_rx.v: - -* A second DDC has been added, sharing a frequency register with - the existing DDC. - -* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... - into the receive FIFO. This limits the host configured decimation - to 8 intead of 4. Use gr.deinterleave to recover the streams. - -* The ADCs are hardcoded: - - RX_A ==> DDC #1 I-input - 0 ==> DDC #1 Q-input - RX_B ==> DDC #2 I-input - 0 ==> DDC #2 Q-input - - Thus, the input mux has been disabled. - -* The CIC/HB decimator has been replaced by an integrate and dump at - the decimation rate. - -* To assist with meeting timing, the external RAM has been disabled. - -The basic application is to coherently sample two real IF streams and -downconvert to baseband, while minimizing the impulse response duration -of the resampling filters. diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile b/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v deleted file mode 100644 index 4a945bd1a..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v +++ /dev/null @@ -1,212 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output reg [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b; - wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b; - wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - -`ifdef MUXCTRL - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); -`endif - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - -`ifdef MUXCTRL - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) -`else // !`ifdef MUXCTRL - always @(posedge clk) - begin - adc_i <= adc_a_ofs; - adc_q <= adc_b_ofs; - end -`endif // !`ifdef MUXCTRL - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - // Route I,0 to first CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_a(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_a),.yo(q_cordic_a),.zo() ); - - // Route Q,0 to second CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_b(.clock(clk), .reset(rst), .enable(run), - .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_b),.yo(q_cordic_b),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - wire strobe_iad_o; - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_a), - .stb_o(strobe_iad_o),.integ_o(i_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_a), - .stb_o(),.integ_o(q_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_b), - .stb_o(),.integ_o(i_iad_b) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_b), - .stb_o(),.integ_o(q_iad_b) ); - - round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a)); - round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a)); - round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b)); - round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b)); - - reg [31:0] sample_out_a, sample_out_b, sample_out; - reg stb_d1, stb_d2, stb_d3, stb_d4, stb_d5; - reg strobe_out; - - // Register samples on strobe_iad - // Output A on d1 - // Output B on d5 - always @(posedge clk) - begin - stb_d1 <= strobe_iad_o; - stb_d2 <= stb_d1; - stb_d3 <= stb_d2; - stb_d4 <= stb_d3; - stb_d5 <= stb_d4; - end - - always @(posedge clk) - if (strobe_iad_o) - begin - // Streaming GPIO - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0], - q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] }; - sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0], - q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] }; - end - - always @(posedge clk) - begin - if (stb_d1) - sample <= sample_out_a; - else if (stb_d5) - sample <= sample_out_b; - strobe_out <= stb_d1|stb_d5; - end - - assign strobe = strobe_out; - assign debug = 0; - -endmodule // dsp_core_rx diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav deleted file mode 100644 index 12f746860..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav +++ /dev/null @@ -1,106 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -@22 -dsp_core_tb.rx_path.adc_a[13:0] -dsp_core_tb.rx_path.adc_b[13:0] -@28 -dsp_core_tb.rx_path.adc_ovf_a -dsp_core_tb.rx_path.adc_ovf_b -@22 -dsp_core_tb.rx_path.io_rx[15:0] -@200 -- -@22 -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe -@200 -- -@22 -dsp_core_tb.rx_path.phase_inc[31:0] -dsp_core_tb.rx_path.scale_i[15:0] -dsp_core_tb.rx_path.scale_q[15:0] -@28 -dsp_core_tb.rx_path.enable_hb1 -dsp_core_tb.rx_path.enable_hb2 -@22 -dsp_core_tb.rx_path.cic_decim[7:0] -dsp_core_tb.rx_path.adc_a_ofs[13:0] -dsp_core_tb.rx_path.adc_b_ofs[13:0] -dsp_core_tb.rx_path.muxctrl[3:0] -@200 -- -@22 -dsp_core_tb.rx_path.adc_i[13:0] -dsp_core_tb.rx_path.adc_q[13:0] -dsp_core_tb.rx_path.phase[31:0] -dsp_core_tb.rx_path.prod_i[35:0] -dsp_core_tb.rx_path.prod_q[35:0] -@8420 -dsp_core_tb.rx_path.i_cordic_a[23:0] -dsp_core_tb.rx_path.q_cordic_a[23:0] -dsp_core_tb.rx_path.i_cordic_b[23:0] -dsp_core_tb.rx_path.q_cordic_b[23:0] -@22 -dsp_core_tb.rx_path.decim_rate[9:0] -@28 -dsp_core_tb.rx_path.strobe_iad -@22 -dsp_core_tb.rx_path.i_iad_a[31:0] -dsp_core_tb.rx_path.q_iad_a[31:0] -@23 -dsp_core_tb.rx_path.i_iad_b[31:0] -@22 -dsp_core_tb.rx_path.q_iad_b[31:0] -@28 -dsp_core_tb.rx_path.strobe_iad_o -@8420 -dsp_core_tb.rx_path.i_out_a[15:0] -dsp_core_tb.rx_path.q_out_a[15:0] -dsp_core_tb.rx_path.i_out_b[15:0] -dsp_core_tb.rx_path.q_out_b[15:0] -@28 -dsp_core_tb.rx_path.gpio_ena[1:0] -@22 -dsp_core_tb.rx_path.sample_out_a[31:0] -dsp_core_tb.rx_path.sample_out_b[31:0] -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe_out -dsp_core_tb.rx_path.stb_d1 -dsp_core_tb.rx_path.stb_d2 -dsp_core_tb.rx_path.stb_d3 -dsp_core_tb.rx_path.stb_d4 -dsp_core_tb.rx_path.stb_d5 -@200 -- --FIFO Bus -@22 -dsp_core_tb.master_time[31:0] -dsp_core_tb.wr_dat[31:0] -@28 -dsp_core_tb.wr_done -dsp_core_tb.wr_error -dsp_core_tb.wr_full -dsp_core_tb.wr_ready -dsp_core_tb.wr_write diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v deleted file mode 100644 index d947df40a..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v +++ /dev/null @@ -1,233 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - - reg [31:0] master_time = 0; - always @(posedge clk) - master_time <= master_time + 1; - - reg wr_ready = 1; - reg wr_full = 0; - - wire [31:0] wr_dat; - wire wr_write; - wire wr_done; - wire wr_error; - wire [15:0] fifo_occupied; - wire fifo_full; - wire fifo_empty; - - rx_control rx_buffer - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time), - .overrun(), // unconnected output - .wr_dat_o(wr_dat), - .wr_write_o(wr_write), - .wr_done_o(wr_done), - .wr_error_o(wr_error), - .wr_ready_i(wr_ready), - .wr_full_i(wr_full), - .sample(sample), - .run(), // unconnected output, supposed to drive 'run' - .strobe(stb), - .fifo_occupied(fifo_occupied), - .fifo_full(fifo_full), - .fifo_empty(fifo_empty), - .debug_rx() // unconnected output - ); - - - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(10); - set_zero_len(990); - set_rx_muxctrl(1); - set_ddc_freq(32'h10000000); - set_rx_scale_iq(1243, 1243); - set_decim(1, 1, 1); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v b/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v deleted file mode 100644 index fc5e3c1ed..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v +++ /dev/null @@ -1,68 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [13:0] adc_b_int = 0; - - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - adc_b_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - adc_b_int <= amplitude >> 2; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - adc_b_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - assign adc_b = adc_b_int + dc_offset_b; - - // Ignore for now - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v b/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v deleted file mode 100755 index 3d96a4e0e..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v +++ /dev/null @@ -1,789 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, - s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; - wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; - wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; - - wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), - .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), - .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), - .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), - .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), - .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), - .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), - .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), - .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), - .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), - .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), - .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), - .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), - .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), - .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), - .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // Buffer Pool, slave #1 - wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; - wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; - wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; - wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), - .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), - .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), - .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), - .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), - .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), - .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), - .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), - // Read Interfaces - .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), - .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), - .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), - .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), - .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), - .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), - .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), - .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) - ); - - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Buffer Pool Status -- Slave #5 - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), - .wb_rst_i(wb_rst), - .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), - .wb_dat_o(s5_dat_i), - .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) - ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Slave, #6 Ethernet MAC, see below - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; - - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; - wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; - wire [31:0] Tx_mac_data, Rx_mac_data; - wire [1:0] Tx_mac_BE, Rx_mac_BE; - wire rst_mac; - - oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); - - MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) - MAC_top - (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), - .rst_mac(rst_mac),.rst_user(dsp_rst), - .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), - .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), - .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), - .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), - .Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), - .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), - .debug0(debug_mac0),.debug1(debug_mac1) ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - mac_rxfifo_int mac_rxfifo_int - (.clk(dsp_clk),.rst(dsp_rst), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), - .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), - .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), - .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), - .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); - - mac_txfifo_int mac_txfifo_int - (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), - .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), - .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; - - simple_pic #(.is(16),.dwidth(32)) simple_pic - (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - assign s8_err = 0; - assign s8_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - assign s9_err = 0; - assign s9_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), - .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - assign s10_err = 0; - assign s10_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), - .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - assign s11_err = 0; - assign s11_rty = 0; - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), - .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - assign s12_err = 0; - assign s12_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we), - .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i), - .wb_ack_o(s13_ack) ); - assign s13_err = 0; - assign s13_rty = 0; - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), - .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - // dummy_rx dsp_core_rx - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), - .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), - .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), - .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - -`ifdef EXTRAM - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), - .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign s14_err = 0; assign s14_rty = 0; - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; -`endif - -`ifdef DEBUG - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; - assign debug_clk[1] = dsp_clk; - - assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; -`endif - -endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh b/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/fpga/usrp2/top/u2_rev3_iad/.gitignore b/fpga/usrp2/top/u2_rev3_iad/.gitignore deleted file mode 100644 index e4daaf1ea..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/build -/*.vcd -/dsp_core_tb -/*.dat diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile deleted file mode 100644 index 15df9e43e..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/Makefile +++ /dev/null @@ -1,253 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/fpga/usrp2/top/u2_rev3_iad/cmdfile b/fpga/usrp2/top/u2_rev3_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v deleted file mode 100644 index 2882464ba..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v +++ /dev/null @@ -1,158 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic, q_cordic; - wire [31:0] i_iad, q_iad; - wire [15:0] i_out, q_out; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - cordic_z24 #(.bitwidth(24)) - cordic(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]), - .xo(i_cordic),.yo(q_cordic),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic), - .stb_o(strobe),.integ_o(i_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic), - .stb_o(),.integ_o(q_iad) ); - - round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out)); - round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out)); - - // Streaming GPIO - // - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - - reg [31:0] sample_reg; - always @(posedge clk) - begin - sample_reg[31:17] <= i_out[15:1]; - sample_reg[15:1] <= q_out[15:1]; - sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; - sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; - end - - assign sample = sample_reg; - assign debug = {clk, rst, run, strobe}; - -endmodule // dsp_core_rx diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav deleted file mode 100644 index 17c90cdd7..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav +++ /dev/null @@ -1,61 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -- -@24 -dsp_core_tb.rx_path.decim_rate[9:0] -@200 -- -@8420 -dsp_core_tb.adc_a[13:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.adc_a_ofs[13:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_cordic[23:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_iad[31:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.i_out[15:0] -@20000 -- -@200 -- -@28 -dsp_core_tb.stb -@200 -- diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v deleted file mode 100644 index 4d5a5b537..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v +++ /dev/null @@ -1,196 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(1); - set_zero_len(999); - set_rx_muxctrl(1); - set_ddc_freq(0); - set_rx_scale_iq(1243, 1243); - set_decim(0, 1, 3); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/fpga/usrp2/top/u2_rev3_iad/impulse.v b/fpga/usrp2/top/u2_rev3_iad/impulse.v deleted file mode 100644 index 7f0cdc9be..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/impulse.v +++ /dev/null @@ -1,63 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - - // Ignore for now - assign adc_b = dc_offset_b; - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/fpga/usrp2/top/u2_rev3_iad/wave.sh b/fpga/usrp2/top/u2_rev3_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/fpga/usrp2/top/u2plus/capture_ddrlvds.v b/fpga/usrp2/top/u2plus/capture_ddrlvds.v deleted file mode 100644 index b9f53ff8c..000000000 --- a/fpga/usrp2/top/u2plus/capture_ddrlvds.v +++ /dev/null @@ -1,39 +0,0 @@ - - -module capture_ddrlvds - #(parameter WIDTH=7) - (input clk, - input ssclk_p, - input ssclk_n, - input [WIDTH-1:0] in_p, - input [WIDTH-1:0] in_n, - output reg [(2*WIDTH)-1:0] out); - - wire [WIDTH-1:0] ddr_dat; - wire ssclk_regional; - wire ssclk_io; - wire ssclk; - wire [(2*WIDTH)-1:0] out_pre1; - reg [(2*WIDTH)-1:0] out_pre2; - - IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); - - genvar i; - generate - for(i = 0; i < WIDTH; i = i + 1) - begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds - (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); - IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 - (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), - .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); - end - endgenerate - - always @(negedge clk) - out_pre2 <= out_pre1; - - always @(posedge clk) - out <= out_pre2; - -endmodule // capture_ddrlvds |