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-rwxr-xr-x[-rw-r--r--]fpga/usrp2/top/u2_rev3/u2_core.v50
-rw-r--r--fpga/usrp2/top/u2_rev3/u2_core_udp.v119
2 files changed, 82 insertions, 87 deletions
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
index b67d8edd6..9ba3cc136 100644..100755
--- a/fpga/usrp2/top/u2_rev3/u2_core.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core.v
@@ -277,33 +277,33 @@ module u2_core
// ///////////////////////////////////////////////////////////////////
// RAM Loader
- wire [31:0] ram_loader_dat, iwb_dat;
- wire [15:0] ram_loader_adr, iwb_adr;
+ wire [31:0] ram_loader_dat, if_dat;
+ wire [15:0] ram_loader_adr;
+ wire [14:0] if_adr;
wire [3:0] ram_loader_sel;
- wire ram_loader_stb, ram_loader_we, ram_loader_ack;
+ wire ram_loader_stb, ram_loader_we;
wire iwb_ack, iwb_stb;
ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
- ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
+ .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
+ .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
+ .wb_we(ram_loader_we),
+ .ram_loader_done(ram_loader_done),
// CPLD Interface
- .cfg_clk_i(cpld_clk),
- .cfg_data_i(cpld_din),
- .start_o(cpld_start_int),
- .mode_o(cpld_mode_int),
- .done_o(cpld_done_int),
- .detached_i(cpld_detached),
- // Wishbone Interface
- .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
- .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
- .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
- .ram_loader_done_o(ram_loader_done));
-
+ .cpld_clk(cpld_clk),
+ .cpld_din(cpld_din),
+ .cpld_start(cpld_start_int),
+ .cpld_mode(cpld_mode_int),
+ .cpld_done(cpld_done_int),
+ .cpld_detached(cpld_detached));
+
// /////////////////////////////////////////////////////////////////////////
// Processor
aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
// Instruction Wishbone bus to I-RAM
- .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
- .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ .if_adr(if_adr),
+ .if_dat(if_dat),
// Data Wishbone bus to system bus fabric
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -317,16 +317,16 @@ module u2_core
// I-port connects directly to processor and ram loader
wire flush_icache;
- ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
- .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+ .ram_loader_we_i(ram_loader_we),
.ram_loader_done_i(ram_loader_done),
- .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
- .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+ .if_adr(if_adr),
+ .if_data(if_dat),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
@@ -622,7 +622,7 @@ module u2_core
// ///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
-
+/*
localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes
wire [15:0] bus2ram, ram2bus;
@@ -650,6 +650,7 @@ module u2_core
.sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
.sram_mode(),.sram_zz() );
+*/
assign RAM_CE1n = 0;
assign RAM_D[17:16] = 2'bzz;
@@ -700,7 +701,8 @@ module u2_core
{ wr2_flags, rd2_flags },
{ GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
- assign debug_gpio_0 = debug_mac; //eth_mac_debug;
+ assign debug_gpio_0 = 0;
+ //debug_mac; //eth_mac_debug;
assign debug_gpio_1 = 0;
endmodule // u2_core
diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
index cb0ed78c7..b79cab5fb 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
@@ -180,6 +180,11 @@ module u2_core
wire [31:0] irq;
wire [63:0] vita_time;
+ wire run_rx, run_tx;
+ reg run_rx_d1;
+ always @(posedge dsp_clk)
+ run_rx_d1 <= run_rx;
+
// ///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
localparam dw = 32; // Data bus width
@@ -279,33 +284,33 @@ module u2_core
// ///////////////////////////////////////////////////////////////////
// RAM Loader
- wire [31:0] ram_loader_dat, iwb_dat;
- wire [15:0] ram_loader_adr, iwb_adr;
+ wire [31:0] ram_loader_dat, if_dat;
+ wire [15:0] ram_loader_adr;
+ wire [14:0] if_adr;
wire [3:0] ram_loader_sel;
- wire ram_loader_stb, ram_loader_we, ram_loader_ack;
+ wire ram_loader_stb, ram_loader_we;
wire iwb_ack, iwb_stb;
ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
- ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
+ .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
+ .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
+ .wb_we(ram_loader_we),
+ .ram_loader_done(ram_loader_done),
// CPLD Interface
- .cfg_clk_i(cpld_clk),
- .cfg_data_i(cpld_din),
- .start_o(cpld_start_int),
- .mode_o(cpld_mode_int),
- .done_o(cpld_done_int),
- .detached_i(cpld_detached),
- // Wishbone Interface
- .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
- .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
- .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
- .ram_loader_done_o(ram_loader_done));
-
+ .cpld_clk(cpld_clk),
+ .cpld_din(cpld_din),
+ .cpld_start(cpld_start_int),
+ .cpld_mode(cpld_mode_int),
+ .cpld_done(cpld_done_int),
+ .cpld_detached(cpld_detached));
+
// /////////////////////////////////////////////////////////////////////////
// Processor
aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
// Instruction Wishbone bus to I-RAM
- .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
- .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ .if_adr(if_adr),
+ .if_dat(if_dat),
// Data Wishbone bus to system bus fabric
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -319,16 +324,16 @@ module u2_core
// I-port connects directly to processor and ram loader
wire flush_icache;
- ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
- .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+ .ram_loader_we_i(ram_loader_we),
.ram_loader_done_i(ram_loader_done),
- .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
- .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+ .if_adr(if_adr),
+ .if_data(if_dat),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
@@ -461,11 +466,20 @@ module u2_core
.tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
.debug(debug_udp) );
+ wire [35:0] tx_err_data, udp1_tx_data;
+ wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+ .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+ fifo36_mux #(.prio(0)) mux_err_stream
+ (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
+ .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
+ .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+ .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
@@ -509,12 +523,13 @@ module u2_core
// In Rev3 there are only 6 leds, and the highest one is on the ETH connector
wire [7:0] led_src, led_sw;
- wire [7:0] led_hw = {clk_status,serdes_link_up};
+ wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0};
setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(led_sw),.changed());
- setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(led_src),.changed());
+
+ setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110))
+ sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed());
assign leds = (led_src & led_hw) | (~led_src & led_sw);
@@ -565,11 +580,6 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// ATR Controller, Slave #11
- wire run_rx, run_tx;
- reg run_rx_d1;
- always @(posedge dsp_clk)
- run_rx_d1 <= run_rx;
-
atr_controller atr_controller
(.clk_i(wb_clk),.rst_i(wb_rst),
.adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
@@ -638,40 +648,26 @@ module u2_core
// DSP TX
wire [35:0] tx_data;
- wire [99:0] tx1_data;
- wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
-
- wire [31:0] debug_vtc, debug_vtd, debug_vt;
+ wire tx_src_rdy, tx_dst_rdy;
+ wire [31:0] debug_vt;
fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
- vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
- .debug(debug_vtd) );
-
- vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .vita_time(vita_time),.underrun(underrun),
- .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
- .debug(debug_vtc) );
-
- assign debug_vt = debug_vtc | debug_vtd;
-
- dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
- (.clk(dsp_clk),.rst(dsp_rst),
+ vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ .REPORT_ERROR(1), .PROT_ENG_FLAGS(1))
+ vita_tx_chain
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .vita_time(vita_time),
+ .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+ .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(dac_a),.dac_b(dac_b),
- .debug(debug_tx_dsp) );
-
+ .underrun(underrun), .run(run_tx),
+ .debug(debug_vt));
+
assign dsp_rst = wb_rst;
// ///////////////////////////////////////////////////////////////////////////////////
@@ -773,8 +769,7 @@ endmodule // u2_core
{ s6_adr[15:8] },
{ s6_adr[7:0] },
{ 6'd0, mdio_cpy, MDC } };
-*/
-/*
+
assign debug = { { GMII_TXD },
{ 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
{ wr2_flags, rd2_flags },
@@ -783,7 +778,6 @@ endmodule // u2_core
{ 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
{ wr2_flags, rd2_flags },
{ GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
- */
// assign debug = debug_udp;
// assign debug = vrc_debug;
@@ -794,9 +788,8 @@ endmodule // u2_core
{wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}};
*/
// assign debug_gpio_1 = {vita_time[63:32] };
-
-/*
- assign debug_gpio_1 = { { tx_f19_data[15:8] },
+/*
+ assign debug_gpio_1 = { { tx_f19_data[15:8] },
{ tx_f19_data[7:0] },
{ 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] },
{ 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } };
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-30 01:28:54 +0000