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-rw-r--r--fpga/usrp2/top/safe_u2plus/Makefile1
-rw-r--r--fpga/usrp2/top/u1e/Makefile1
-rw-r--r--fpga/usrp2/top/u1e/u1e_core.v100
-rw-r--r--fpga/usrp2/top/u1e_passthru/Makefile3
-rw-r--r--fpga/usrp2/top/u2_rev3/Makefile1
-rw-r--r--fpga/usrp2/top/u2_rev3/u2_core.v210
-rw-r--r--fpga/usrp2/top/u2_rev3/u2_rev3.v2
-rw-r--r--fpga/usrp2/top/u2_rev3_2rx_iad/Makefile1
-rw-r--r--fpga/usrp2/top/u2_rev3_iad/Makefile1
-rw-r--r--fpga/usrp2/top/u2plus/Makefile1
-rw-r--r--fpga/usrp2/top/u2plus/u2plus_core.v209
11 files changed, 205 insertions, 325 deletions
diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile
index 62a02ff40..b72241050 100644
--- a/fpga/usrp2/top/safe_u2plus/Makefile
+++ b/fpga/usrp2/top/safe_u2plus/Makefile
@@ -117,7 +117,6 @@ coregen/fifo_xlnx_512x36_2clk.v \
coregen/fifo_xlnx_512x36_2clk.xco \
coregen/fifo_xlnx_64x36_2clk.v \
coregen/fifo_xlnx_64x36_2clk.xco \
-extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/u1e/Makefile
index 3cb9fd8f3..5d721979b 100644
--- a/fpga/usrp2/top/u1e/Makefile
+++ b/fpga/usrp2/top/u1e/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
include ../../gpmc/Makefile.srcs
##################################################
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v
index 7d5924bea..b3d71b4ab 100644
--- a/fpga/usrp2/top/u1e/u1e_core.v
+++ b/fpga/usrp2/top/u1e/u1e_core.v
@@ -1,9 +1,5 @@
-//`define LOOPBACK 1
-//`define TIMED 1
-`define DSP 1
-
module u1e_core
(input clk_fpga, input rst_fpga,
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -48,13 +44,18 @@ module u1e_core
wire pps_int;
wire [63:0] vita_time, vita_time_pps;
reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate;
+ wire [7:0] test_rate;
+ wire [3:0] test_ctrl;
wire [7:0] set_addr;
wire [31:0] set_data;
wire set_stb;
wire [31:0] debug_vt;
-
+ wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
+ assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp;
+ assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
+
setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(global_reset));
@@ -79,7 +80,6 @@ module u1e_core
tx_err_src_rdy, tx_err_dst_rdy;
reg [15:0] tx_frame_len;
wire [15:0] rx_frame_len;
- wire [7:0] rate;
wire bus_error;
wire clear_tx, clear_rx;
@@ -111,62 +111,15 @@ module u1e_core
.rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
.tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+ .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
+
+ .test_rate(test_rate), .test_ctrl(test_ctrl),
.debug(debug_gpmc));
wire rx_sof = rx_data[32];
wire rx_eof = rx_data[33];
wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
-`ifdef LOOPBACK
- wire [7:0] WHOAMI = 1;
-
- fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
- .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
- assign tx_underrun = 0;
- assign rx_overrun = 0;
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // LOOPBACK
-
-`ifdef TIMED
- wire [7:0] WHOAMI = 2;
-
- // TX side
- wire tx_enable;
-
- fifo_pacer tx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
- .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
- .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
- .underrun(tx_underrun), .overrun());
-
- packet_verifier32 pktver32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
- .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
- // RX side
- wire rx_enable;
-
- packet_generator32 pktgen32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
- .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
-
- fifo_pacer rx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
- .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
- .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
- .underrun(), .overrun(rx_overrun));
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // `ifdef TIMED
-
-`ifdef DSP
- wire [7:0] WHOAMI = 0;
-
wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug;
// /////////////////////////////////////////////////////////////////////////
@@ -189,7 +142,7 @@ module u1e_core
vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .vita_time(vita_time), .overrun(rx_overrun),
+ .vita_time(vita_time), .overrun(rx_overrun_dsp),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
.debug_rx(vrc_debug));
@@ -199,7 +152,6 @@ module u1e_core
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
.data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy),
- .fifo_occupied(), .fifo_full(), .fifo_empty(),
.debug_rx(vrf_debug) );
fifo36_mux #(.prio(0)) mux_err_stream
@@ -225,29 +177,12 @@ module u1e_core
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(tx_i_int),.dac_b(tx_q_int),
- .underrun(underrun), .run(run_tx),
+ .underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
assign tx_i = tx_i_int[15:2];
assign tx_q = tx_q_int[15:2];
-`else // !`ifdef DSP
- // Dummy DSP signal generator for test purposes
- wire [23:0] tx_i_int, tx_q_int;
- wire [23:0] freq = {reg_test,8'd0};
- reg [23:0] phase;
-
- always @(posedge wb_clk)
- phase <= phase + freq;
-
- cordic_z24 #(.bitwidth(24)) tx_cordic
- (.clock(wb_clk), .reset(wb_rst), .enable(1),
- .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
-
- assign tx_i = tx_i_int[23:10];
- assign tx_q = tx_q_int[23:10];
-`endif // !`ifdef DSP
-
// /////////////////////////////////////////////////////////////////////////////////////
// Wishbone Intercon, single master
wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
@@ -320,7 +255,6 @@ module u1e_core
// Slave 0, Misc LEDs, Switches, controls
localparam REG_LEDS = 7'd0; // out
- localparam REG_SWITCHES = 7'd2; // in
localparam REG_CGEN_CTRL = 7'd4; // out
localparam REG_CGEN_ST = 7'd6; // in
localparam REG_TEST = 7'd8; // out
@@ -353,20 +287,18 @@ module u1e_core
xfer_rate <= s0_dat_mosi;
endcase // case (s0_adr[6:0])
- assign tx_enable = xfer_rate[15];
- assign rx_enable = xfer_rate[14];
- assign rate = xfer_rate[7:0];
+ assign test_ctrl = xfer_rate[11:8];
+ assign test_rate = xfer_rate[7:0];
assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]};
assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds :
- (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
(s0_adr[6:0] == REG_TEST) ? reg_test :
(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
- (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+ (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } :
16'hBEEF;
assign s0_ack = s0_stb & s0_cyc;
@@ -475,10 +407,14 @@ module u1e_core
assign debug_clk = { EM_CLK, clk_fpga };
+/*
assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
{ tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
{ EM_D } };
+*/
+ assign debug = debug_gpmc;
+
assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]},
{2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile
index d1950629b..f2d835608 100644
--- a/fpga/usrp2/top/u1e_passthru/Makefile
+++ b/fpga/usrp2/top/u1e_passthru/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
include ../../gpmc/Makefile.srcs
##################################################
@@ -51,7 +50,7 @@ passthru.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \
$(GPMC_SRCS)
##################################################
diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/u2_rev3/Makefile
index 05ada2476..e9b43491a 100644
--- a/fpga/usrp2/top/u2_rev3/Makefile
+++ b/fpga/usrp2/top/u2_rev3/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
include ../../extramfifo/Makefile.srcs
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
index ab2ed49f0..79470de9e 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core.v
@@ -3,7 +3,6 @@
// ////////////////////////////////////////////////////////////////////////////////
module u2_core
- #(parameter RAM_SIZE=16384, parameter RAM_AW=14)
(// Clocks
input dsp_clk,
input wb_clk,
@@ -137,20 +136,24 @@ module u2_core
input [3:0] clock_divider
);
- localparam SR_BUF_POOL = 64; // Uses 1 reg
+ localparam SR_MISC = 0; // Uses 9 regs
+ localparam SR_BUF_POOL = 64; // Uses 4 regs
localparam SR_UDP_SM = 96; // 64 regs
- localparam SR_RX_DSP = 160; // 16
- localparam SR_RX_CTRL = 176; // 16
+ localparam SR_RX_DSP0 = 160; // 16
+ localparam SR_RX_CTRL0 = 176; // 16
localparam SR_TIME64 = 192; // 3
localparam SR_SIMTIMER = 198; // 2
localparam SR_TX_DSP = 208; // 16
localparam SR_TX_CTRL = 224; // 16
-
+ localparam SR_RX_DSP1 = 240;
+ localparam SR_RX_CTRL1 = 32;
+
+
// FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
- localparam DSP_TX_FIFOSIZE = 10;
+ // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
localparam DSP_RX_FIFOSIZE = 10;
- localparam ETH_TX_FIFOSIZE = 10;
+ localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo?
@@ -159,13 +162,14 @@ module u2_core
wire [31:0] set_data, set_data_dsp;
wire set_stb, set_stb_dsp;
- wire ram_loader_done;
- wire ram_loader_rst, wb_rst, dsp_rst;
- assign dsp_rst = wb_rst;
-
+ wire ram_loader_done, ram_loader_rst;
+ wire wb_rst;
+ wire dsp_rst = wb_rst;
+
wire [31:0] status;
wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
- wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+ wire proc_int, overrun0, overrun1, underrun;
+ wire uart_tx_int, uart_rx_int;
wire [31:0] debug_gpio_0, debug_gpio_1;
wire [31:0] atr_lines;
@@ -182,10 +186,8 @@ module u2_core
wire [31:0] irq;
wire [63:0] vita_time, vita_time_pps;
- wire run_rx, run_tx;
- reg run_rx_d1;
- always @(posedge dsp_clk)
- run_rx_d1 <= run_rx;
+ wire run_rx0, run_rx1, run_tx;
+ reg run_rx0_d1, run_rx1_d1;
// ///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
@@ -291,7 +293,7 @@ module u2_core
wire [15:0] ram_loader_adr;
wire [3:0] ram_loader_sel;
wire ram_loader_stb, ram_loader_we;
- ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE))
+ ram_loader #(.AWIDTH(aw),.RAM_SIZE(16384))
ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
.wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
.wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
@@ -324,21 +326,21 @@ module u2_core
// I-port connects directly to processor and ram loader
wire flush_icache;
- ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
- .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat),
+ .ram_loader_adr_i(ram_loader_adr[13:0]), .ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
.ram_loader_we_i(ram_loader_we),
.ram_loader_done_i(ram_loader_done),
.if_adr(16'b0), .if_data(),
- .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+ .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
.flush_icache(flush_icache));
- setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(flush_icache));
// /////////////////////////////////////////////////////////////////////////
@@ -347,15 +349,13 @@ module u2_core
wire rd1_ready_i, rd1_ready_o;
wire rd2_ready_i, rd2_ready_o;
wire rd3_ready_i, rd3_ready_o;
- wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags;
- wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+ wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
wire wr0_ready_i, wr0_ready_o;
wire wr1_ready_i, wr1_ready_o;
wire wr2_ready_i, wr2_ready_o;
wire wr3_ready_i, wr3_ready_o;
- wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags;
- wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+ wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
wire [35:0] tx_err_data;
wire tx_err_src_rdy, tx_err_dst_rdy;
@@ -373,14 +373,15 @@ module u2_core
.status(status), .sys_int_o(buffer_int), .debug(router_debug),
- .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
- .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o),
- .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+ .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
+ .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),
+ .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),
+ .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
.err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
- .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
- .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
- .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
+ .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
+ .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+ .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
);
// /////////////////////////////////////////////////////////////////////////
@@ -416,7 +417,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = 32'd4;
+ localparam compat_num = 32'd5;
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -432,56 +433,21 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
- wire [18:0] rx_f19_data, tx_f19_data;
- wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
-
- simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+ simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE),
+ .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19
(.clk125(clk_to_mac), .reset(wb_rst),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.sys_clk(dsp_clk),
- .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
- .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+ .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+ .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
.wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
.mdio(MDIO), .mdc(MDC),
.debug(debug_mac));
- wire [35:0] rx_f36_data, tx_f36_data;
- wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
-
- wire [18:0] _rx_f19_data;
- wire _rx_f19_src_rdy, _rx_f19_dst_rdy;
-
- //mac rx to eth input...
- fifo19_rxrealign fifo19_rxrealign
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
- .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
-
- fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
- .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
-
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
- .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-
- //eth output to mac tx...
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
-
- fifo36_to_fifo19 eth_out_fifo36_to_fifo19
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
- .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
-
// /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
@@ -504,13 +470,13 @@ module u2_core
wire phy_reset;
assign PHY_RESETn = ~phy_reset;
- setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
.in(set_data),.out(clock_outs),.changed());
- setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(serdes_outs),.changed());
- setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(adc_outs),.changed());
- setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phy_reset),.changed());
// /////////////////////////////////////////////////////////////////////////
@@ -520,12 +486,12 @@ module u2_core
// In Rev3 there are only 6 leds, and the highest one is on the ETH connector
wire [7:0] led_src, led_sw;
- wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0};
+ wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0};
- setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(led_sw),.changed());
- setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110))
+ setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110))
sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed());
assign leds = (led_src & led_hw) | (~led_src & led_sw);
@@ -537,7 +503,7 @@ module u2_core
wire underrun_wb, overrun_wb, pps_wb;
oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb));
- oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb));
+ oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb));
oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb));
assign irq= {{8'b0},
@@ -580,7 +546,7 @@ module u2_core
(.clk_i(wb_clk),.rst_i(wb_rst),
.adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
.we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
- .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+ .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
// //////////////////////////////////////////////////////////////////////////
// Time Sync, Slave #12
@@ -601,50 +567,60 @@ module u2_core
assign sd_dat_i[31:8] = 0;
// /////////////////////////////////////////////////////////////////////////
- // DSP RX
- wire [31:0] sample_rx, sample_tx;
- wire strobe_rx, strobe_tx;
- wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy;
- wire [99:0] rx_data;
- wire [35:0] rx1_data;
-
- dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+ // DSP RX 0
+ wire [31:0] sample_rx0;
+ wire clear_rx0, strobe_rx0;
+
+ always @(posedge dsp_clk)
+ run_rx0_d1 <= run_rx0;
+
+ dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
- .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
- .debug(debug_rx_dsp) );
+ .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
+ .debug() );
- wire [31:0] vrc_debug;
- wire clear_rx;
-
- setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear
+ setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0
(.clk(dsp_clk),.rst(dsp_rst),
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
- .out(),.changed(clear_rx));
+ .out(),.changed(clear_rx0));
- vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
+ vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .vita_time(vita_time), .overrun(overrun),
- .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
- .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy),
- .debug_rx(vrc_debug));
+ .vita_time(vita_time), .overrun(overrun0),
+ .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
+ .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
+ .debug() );
- wire [3:0] vita_state;
+ // /////////////////////////////////////////////////////////////////////////
+ // DSP RX 1
+ wire [31:0] sample_rx1;
+ wire clear_rx1, strobe_rx1;
+
+ always @(posedge dsp_clk)
+ run_rx1_d1 <= run_rx1;
- vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
+ dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+ (.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
- .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
- .fifo_occupied(), .fifo_full(), .fifo_empty(),
- .debug_rx(vita_state) );
+ .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+ .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
+ .debug() );
+
+ setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+ .out(),.changed(clear_rx1));
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
- .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
- .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+ vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .vita_time(vita_time), .overrun(overrun1),
+ .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
+ .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
+ .debug() );
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
@@ -672,10 +648,10 @@ module u2_core
.RAM_LDn(RAM_LDn),
.RAM_OEn(RAM_OEn),
.RAM_CE1n(RAM_CE1n),
- .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}),
+ .datain(rd1_dat),
.src_rdy_i(rd1_ready_o),
.dst_rdy_o(rd1_ready_i),
- .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}),
+ .dataout(tx_data),
.src_rdy_o(tx_src_rdy),
.dst_rdy_i(tx_dst_rdy),
.debug(debug_extfifo),
@@ -701,9 +677,9 @@ module u2_core
serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes
(.clk(dsp_clk),.rst(dsp_rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
- .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+ .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
- .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+ .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
.serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
@@ -725,7 +701,7 @@ module u2_core
// Debug Pins
assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac};
- assign debug = 32'd0; // debug_extfifo;
+ assign debug = 32'd0;
assign debug_gpio_0 = 32'd0;
assign debug_gpio_1 = 32'd0;
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v
index 759f7b7b8..bc7ae5f16 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.v
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v
@@ -471,7 +471,7 @@ module u2_rev3
//
- u2_core #(.RAM_SIZE(16384), .RAM_AW(14))
+ u2_core
u2_core(.dsp_clk (dsp_clk),
.wb_clk (wb_clk),
.clock_ready (clock_ready),
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
index 5b7ed5a8e..334089839 100644
--- a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
@@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile
index 5ae8846dd..15df9e43e 100644
--- a/fpga/usrp2/top/u2_rev3_iad/Makefile
+++ b/fpga/usrp2/top/u2_rev3_iad/Makefile
@@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile
index c38bd3ec1..38400ce62 100644
--- a/fpga/usrp2/top/u2plus/Makefile
+++ b/fpga/usrp2/top/u2plus/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
include ../../extramfifo/Makefile.srcs
diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v
index 3edb539f7..ec54de73e 100644
--- a/fpga/usrp2/top/u2plus/u2plus_core.v
+++ b/fpga/usrp2/top/u2plus/u2plus_core.v
@@ -131,20 +131,24 @@ module u2plus_core
output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi
);
- localparam SR_BUF_POOL = 64; // router
+ localparam SR_MISC = 0; // Uses 9 regs
+ localparam SR_BUF_POOL = 64; // Uses 4 regs
localparam SR_UDP_SM = 96; // 64 regs
- localparam SR_RX_DSP = 160; // 16
- localparam SR_RX_CTRL = 176; // 16
+ localparam SR_RX_DSP0 = 160; // 16
+ localparam SR_RX_CTRL0 = 176; // 16
localparam SR_TIME64 = 192; // 3
localparam SR_SIMTIMER = 198; // 2
localparam SR_TX_DSP = 208; // 16
localparam SR_TX_CTRL = 224; // 16
-
+ localparam SR_RX_DSP1 = 240;
+ localparam SR_RX_CTRL1 = 32;
+
+
// FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
- localparam DSP_TX_FIFOSIZE = 10;
+ // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
localparam DSP_RX_FIFOSIZE = 10;
- localparam ETH_TX_FIFOSIZE = 10;
+ localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo?
@@ -153,18 +157,19 @@ module u2plus_core
wire [31:0] set_data, set_data_dsp;
wire set_stb, set_stb_dsp;
- reg wb_rst; wire dsp_rst;
-
+ reg wb_rst;
+ wire dsp_rst = wb_rst;
+
wire [31:0] status;
wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
- wire proc_int, overrun, underrun;
+ wire proc_int, overrun0, overrun1, underrun;
wire [3:0] uart_tx_int, uart_rx_int;
wire [31:0] debug_gpio_0, debug_gpio_1;
wire [31:0] atr_lines;
wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
- debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+ debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2;
wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
@@ -174,7 +179,9 @@ module u2plus_core
wire epoch;
wire [31:0] irq;
wire [63:0] vita_time, vita_time_pps;
- wire run_rx, run_tx;
+
+ wire run_rx0, run_rx1, run_tx;
+ reg run_rx0_d1, run_rx1_d1;
// ///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
@@ -341,15 +348,13 @@ module u2plus_core
wire rd1_ready_i, rd1_ready_o;
wire rd2_ready_i, rd2_ready_o;
wire rd3_ready_i, rd3_ready_o;
- wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags;
- wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+ wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
wire wr0_ready_i, wr0_ready_o;
wire wr1_ready_i, wr1_ready_o;
wire wr2_ready_i, wr2_ready_o;
wire wr3_ready_i, wr3_ready_o;
- wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags;
- wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+ wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
wire [35:0] tx_err_data;
wire tx_err_src_rdy, tx_err_dst_rdy;
@@ -367,14 +372,15 @@ module u2plus_core
.status(status), .sys_int_o(buffer_int), .debug(router_debug),
- .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
- .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o),
- .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+ .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
+ .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),
+ .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),
+ .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
.err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
- .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
- .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
- .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
+ .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
+ .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+ .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
);
// /////////////////////////////////////////////////////////////////////////
@@ -410,12 +416,12 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = 32'd4;
+ localparam compat_num = 32'd5;
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
-
+
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
@@ -426,56 +432,21 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
- wire [18:0] rx_f19_data, tx_f19_data;
- wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
-
- simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+ simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE),
+ .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19
(.clk125(clk_to_mac), .reset(wb_rst),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.sys_clk(dsp_clk),
- .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
- .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+ .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+ .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
.wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
.mdio(MDIO), .mdc(MDC),
.debug(debug_mac));
- wire [35:0] rx_f36_data, tx_f36_data;
- wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
-
- wire [18:0] _rx_f19_data;
- wire _rx_f19_src_rdy, _rx_f19_dst_rdy;
-
- //mac rx to eth input...
- fifo19_rxrealign fifo19_rxrealign
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
- .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
-
- fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
- .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
-
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
- .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-
- //eth output to mac tx...
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
-
- fifo36_to_fifo19 eth_out_fifo36_to_fifo19
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
- .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
-
// /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
@@ -498,15 +469,15 @@ module u2plus_core
wire phy_reset;
assign PHY_RESETn = ~phy_reset;
- setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
.in(set_data),.out(clock_outs),.changed());
- setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(serdes_outs),.changed());
- setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(adc_outs),.changed());
- setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phy_reset),.changed());
- setting_reg #(.my_addr(5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(bldr_done),.changed());
// /////////////////////////////////////////////////////////////////////////
@@ -516,12 +487,12 @@ module u2plus_core
// In Rev3 there are only 6 leds, and the highest one is on the ETH connector
wire [7:0] led_src, led_sw;
- wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0};
+ wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0};
- setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(led_sw),.changed());
- setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110))
+ setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110))
sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed());
assign leds = (led_src & led_hw) | (~led_src & led_sw);
@@ -533,7 +504,7 @@ module u2plus_core
wire underrun_wb, overrun_wb, pps_wb;
oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb));
- oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb));
+ oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb));
oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb));
assign irq= {{8'b0},
@@ -572,15 +543,11 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// ATR Controller, Slave #11
- reg run_rx_d1;
- always @(posedge dsp_clk)
- run_rx_d1 <= run_rx;
-
atr_controller atr_controller
(.clk_i(wb_clk),.rst_i(wb_rst),
.adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
.we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
- .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+ .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
// //////////////////////////////////////////////////////////////////////////
// Time Sync, Slave #12
@@ -605,50 +572,60 @@ module u2plus_core
.sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );
// /////////////////////////////////////////////////////////////////////////
- // DSP RX
- wire [31:0] sample_rx, sample_tx;
- wire strobe_rx, strobe_tx;
- wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy;
- wire [99:0] rx_data;
- wire [35:0] rx1_data;
-
- dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+ // DSP RX 0
+ wire [31:0] sample_rx0;
+ wire clear_rx0, strobe_rx0;
+
+ always @(posedge dsp_clk)
+ run_rx0_d1 <= run_rx0;
+
+ dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
- .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
- .debug(debug_rx_dsp) );
+ .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
+ .debug() );
- wire [31:0] vrc_debug;
- wire clear_rx;
-
- setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear
+ setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0
(.clk(dsp_clk),.rst(dsp_rst),
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
- .out(),.changed(clear_rx));
+ .out(),.changed(clear_rx0));
- vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
+ vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .vita_time(vita_time), .overrun(overrun),
- .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
- .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy),
- .debug_rx(vrc_debug));
+ .vita_time(vita_time), .overrun(overrun0),
+ .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
+ .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
+ .debug() );
- wire [3:0] vita_state;
+ // /////////////////////////////////////////////////////////////////////////
+ // DSP RX 1
+ wire [31:0] sample_rx1;
+ wire clear_rx1, strobe_rx1;
+
+ always @(posedge dsp_clk)
+ run_rx1_d1 <= run_rx1;
- vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
+ dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+ (.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
- .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
- .fifo_occupied(), .fifo_full(), .fifo_empty(),
- .debug_rx(vita_state) );
+ .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+ .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
+ .debug() );
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
- .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
- .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+ setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+ .out(),.changed(clear_rx1));
+
+ vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .vita_time(vita_time), .overrun(overrun1),
+ .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
+ .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
+ .debug() );
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
@@ -678,10 +655,10 @@ module u2plus_core
.RAM_LDn(RAM_LDn),
.RAM_OEn(RAM_OEn),
.RAM_CE1n(RAM_CE1n),
- .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}),
+ .datain(rd1_dat),
.src_rdy_i(rd1_ready_o),
.dst_rdy_o(rd1_ready_i),
- .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}),
+ .dataout(tx_data),
.src_rdy_o(tx_src_rdy),
.dst_rdy_i(tx_dst_rdy),
.debug(debug_extfifo),
@@ -701,17 +678,15 @@ module u2plus_core
.underrun(underrun), .run(run_tx),
.debug(debug_vt));
- assign dsp_rst = wb_rst;
-
// ///////////////////////////////////////////////////////////////////////////////////
// SERDES
serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes
(.clk(dsp_clk),.rst(dsp_rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
- .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+ .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
- .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+ .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
.serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
@@ -720,18 +695,18 @@ module u2plus_core
// VITA Timing
wire [31:0] debug_sync;
-
+
time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
(.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
.pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
.exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
.debug(debug_sync));
-
+
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac};
- assign debug = 32'd0; // debug_extfifo;
+ assign debug = 32'd0;
assign debug_gpio_0 = 32'd0;
assign debug_gpio_1 = 32'd0;
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-26 14:14:32 +0000