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-rw-r--r--fpga/usrp2/top/safe_u2plus/Makefile1
-rw-r--r--fpga/usrp2/top/u1e/u1e_core.v99
-rw-r--r--fpga/usrp2/top/u1e_passthru/Makefile3
-rw-r--r--fpga/usrp2/top/u2_rev3/Makefile1
-rw-r--r--fpga/usrp2/top/u2_rev3/u2_core.v69
-rw-r--r--fpga/usrp2/top/u2_rev3_2rx_iad/Makefile1
-rw-r--r--fpga/usrp2/top/u2_rev3_iad/Makefile1
-rw-r--r--fpga/usrp2/top/u2plus/Makefile1
-rw-r--r--fpga/usrp2/top/u2plus/u2plus_core.v69
9 files changed, 41 insertions, 204 deletions
diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile
index 62a02ff40..b72241050 100644
--- a/fpga/usrp2/top/safe_u2plus/Makefile
+++ b/fpga/usrp2/top/safe_u2plus/Makefile
@@ -117,7 +117,6 @@ coregen/fifo_xlnx_512x36_2clk.v \
coregen/fifo_xlnx_512x36_2clk.xco \
coregen/fifo_xlnx_64x36_2clk.v \
coregen/fifo_xlnx_64x36_2clk.xco \
-extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v
index 7d5924bea..a5a477202 100644
--- a/fpga/usrp2/top/u1e/u1e_core.v
+++ b/fpga/usrp2/top/u1e/u1e_core.v
@@ -1,9 +1,5 @@
-//`define LOOPBACK 1
-//`define TIMED 1
-`define DSP 1
-
module u1e_core
(input clk_fpga, input rst_fpga,
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -48,13 +44,18 @@ module u1e_core
wire pps_int;
wire [63:0] vita_time, vita_time_pps;
reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate;
+ wire [7:0] test_rate;
+ wire [3:0] test_ctrl;
wire [7:0] set_addr;
wire [31:0] set_data;
wire set_stb;
wire [31:0] debug_vt;
-
+ wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
+ assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp;
+ assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
+
setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(global_reset));
@@ -79,7 +80,6 @@ module u1e_core
tx_err_src_rdy, tx_err_dst_rdy;
reg [15:0] tx_frame_len;
wire [15:0] rx_frame_len;
- wire [7:0] rate;
wire bus_error;
wire clear_tx, clear_rx;
@@ -111,62 +111,15 @@ module u1e_core
.rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
.tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+ .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
+
+ .test_rate(test_rate), .test_ctrl(test_ctrl),
.debug(debug_gpmc));
wire rx_sof = rx_data[32];
wire rx_eof = rx_data[33];
wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
-`ifdef LOOPBACK
- wire [7:0] WHOAMI = 1;
-
- fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
- .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
- assign tx_underrun = 0;
- assign rx_overrun = 0;
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // LOOPBACK
-
-`ifdef TIMED
- wire [7:0] WHOAMI = 2;
-
- // TX side
- wire tx_enable;
-
- fifo_pacer tx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
- .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
- .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
- .underrun(tx_underrun), .overrun());
-
- packet_verifier32 pktver32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
- .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
- // RX side
- wire rx_enable;
-
- packet_generator32 pktgen32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
- .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
-
- fifo_pacer rx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
- .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
- .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
- .underrun(), .overrun(rx_overrun));
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // `ifdef TIMED
-
-`ifdef DSP
- wire [7:0] WHOAMI = 0;
-
wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug;
// /////////////////////////////////////////////////////////////////////////
@@ -189,7 +142,7 @@ module u1e_core
vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .vita_time(vita_time), .overrun(rx_overrun),
+ .vita_time(vita_time), .overrun(rx_overrun_dsp),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
.debug_rx(vrc_debug));
@@ -225,29 +178,12 @@ module u1e_core
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(tx_i_int),.dac_b(tx_q_int),
- .underrun(underrun), .run(run_tx),
+ .underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
assign tx_i = tx_i_int[15:2];
assign tx_q = tx_q_int[15:2];
-`else // !`ifdef DSP
- // Dummy DSP signal generator for test purposes
- wire [23:0] tx_i_int, tx_q_int;
- wire [23:0] freq = {reg_test,8'd0};
- reg [23:0] phase;
-
- always @(posedge wb_clk)
- phase <= phase + freq;
-
- cordic_z24 #(.bitwidth(24)) tx_cordic
- (.clock(wb_clk), .reset(wb_rst), .enable(1),
- .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
-
- assign tx_i = tx_i_int[23:10];
- assign tx_q = tx_q_int[23:10];
-`endif // !`ifdef DSP
-
// /////////////////////////////////////////////////////////////////////////////////////
// Wishbone Intercon, single master
wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
@@ -320,7 +256,6 @@ module u1e_core
// Slave 0, Misc LEDs, Switches, controls
localparam REG_LEDS = 7'd0; // out
- localparam REG_SWITCHES = 7'd2; // in
localparam REG_CGEN_CTRL = 7'd4; // out
localparam REG_CGEN_ST = 7'd6; // in
localparam REG_TEST = 7'd8; // out
@@ -353,20 +288,18 @@ module u1e_core
xfer_rate <= s0_dat_mosi;
endcase // case (s0_adr[6:0])
- assign tx_enable = xfer_rate[15];
- assign rx_enable = xfer_rate[14];
- assign rate = xfer_rate[7:0];
+ assign test_ctrl = xfer_rate[11:8];
+ assign test_rate = xfer_rate[7:0];
assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]};
assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds :
- (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
(s0_adr[6:0] == REG_TEST) ? reg_test :
(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
- (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+ (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } :
16'hBEEF;
assign s0_ack = s0_stb & s0_cyc;
@@ -475,10 +408,14 @@ module u1e_core
assign debug_clk = { EM_CLK, clk_fpga };
+/*
assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
{ tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
{ EM_D } };
+*/
+ assign debug = debug_gpmc;
+
assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]},
{2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile
index d1950629b..f2d835608 100644
--- a/fpga/usrp2/top/u1e_passthru/Makefile
+++ b/fpga/usrp2/top/u1e_passthru/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
include ../../gpmc/Makefile.srcs
##################################################
@@ -51,7 +50,7 @@ passthru.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \
$(GPMC_SRCS)
##################################################
diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/u2_rev3/Makefile
index 05ada2476..e9b43491a 100644
--- a/fpga/usrp2/top/u2_rev3/Makefile
+++ b/fpga/usrp2/top/u2_rev3/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
include ../../extramfifo/Makefile.srcs
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
index 10bfd5ffb..79470de9e 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core.v
@@ -152,7 +152,7 @@ module u2_core
// FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
// localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
- localparam DSP_RX_FIFOSIZE = 9;
+ localparam DSP_RX_FIFOSIZE = 10;
localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
@@ -433,56 +433,21 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
- wire [18:0] rx_f19_data, tx_f19_data;
- wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
-
- simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+ simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE),
+ .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19
(.clk125(clk_to_mac), .reset(wb_rst),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.sys_clk(dsp_clk),
- .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
- .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+ .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+ .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
.wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
.mdio(MDIO), .mdc(MDC),
.debug(debug_mac));
- wire [35:0] rx_f36_data, tx_f36_data;
- wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
-
- wire [18:0] _rx_f19_data;
- wire _rx_f19_src_rdy, _rx_f19_dst_rdy;
-
- //mac rx to eth input...
- fifo19_rxrealign fifo19_rxrealign
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
- .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
-
- fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
- .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
-
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
- .dataout(wr2_dat), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-
- //eth output to mac tx...
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rd2_dat), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
-
- fifo36_to_fifo19 eth_out_fifo36_to_fifo19
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
- .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
-
// /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
@@ -604,8 +569,7 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
wire [31:0] sample_rx0;
- wire [35:0] rx0_data;
- wire clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy;
+ wire clear_rx0, strobe_rx0;
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
@@ -622,24 +586,18 @@ module u2_core
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
.out(),.changed(clear_rx0));
- vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0
+ vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
(.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
- .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy),
+ .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
.debug() );
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
- .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy),
- .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
-
// /////////////////////////////////////////////////////////////////////////
// DSP RX 1
wire [31:0] sample_rx1;
- wire [35:0] rx1_data;
- wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy;
+ wire clear_rx1, strobe_rx1;
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
@@ -656,19 +614,14 @@ module u2_core
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
.out(),.changed(clear_rx1));
- vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1
+ vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
(.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
- .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy),
+ .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
.debug() );
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
- .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
- .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o));
-
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
index 5b7ed5a8e..334089839 100644
--- a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
@@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile
index 5ae8846dd..15df9e43e 100644
--- a/fpga/usrp2/top/u2_rev3_iad/Makefile
+++ b/fpga/usrp2/top/u2_rev3_iad/Makefile
@@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile
index c38bd3ec1..38400ce62 100644
--- a/fpga/usrp2/top/u2plus/Makefile
+++ b/fpga/usrp2/top/u2plus/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
include ../../extramfifo/Makefile.srcs
diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v
index 1d568030e..ec54de73e 100644
--- a/fpga/usrp2/top/u2plus/u2plus_core.v
+++ b/fpga/usrp2/top/u2plus/u2plus_core.v
@@ -147,7 +147,7 @@ module u2plus_core
// FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
// localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
- localparam DSP_RX_FIFOSIZE = 9;
+ localparam DSP_RX_FIFOSIZE = 10;
localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
@@ -432,56 +432,21 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
- wire [18:0] rx_f19_data, tx_f19_data;
- wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
-
- simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+ simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE),
+ .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19
(.clk125(clk_to_mac), .reset(wb_rst),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.sys_clk(dsp_clk),
- .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
- .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+ .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+ .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
.wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
.mdio(MDIO), .mdc(MDC),
.debug(debug_mac));
- wire [35:0] rx_f36_data, tx_f36_data;
- wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
-
- wire [18:0] _rx_f19_data;
- wire _rx_f19_src_rdy, _rx_f19_dst_rdy;
-
- //mac rx to eth input...
- fifo19_rxrealign fifo19_rxrealign
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
- .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
-
- fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
- .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
-
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
- .dataout(wr2_dat), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-
- //eth output to mac tx...
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(rd2_dat), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
-
- fifo36_to_fifo19 eth_out_fifo36_to_fifo19
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
- .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
-
// /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
@@ -609,8 +574,7 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
wire [31:0] sample_rx0;
- wire [35:0] rx0_data;
- wire clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy;
+ wire clear_rx0, strobe_rx0;
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
@@ -627,24 +591,18 @@ module u2plus_core
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
.out(),.changed(clear_rx0));
- vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0
+ vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
(.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
- .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy),
+ .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
.debug() );
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
- .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy),
- .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
-
// /////////////////////////////////////////////////////////////////////////
// DSP RX 1
wire [31:0] sample_rx1;
- wire [35:0] rx1_data;
- wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy;
+ wire clear_rx1, strobe_rx1;
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
@@ -661,19 +619,14 @@ module u2plus_core
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
.out(),.changed(clear_rx1));
- vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1
+ vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
(.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
- .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy),
+ .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
.debug() );
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
- .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
- .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o));
-
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 01:05:40 +0000