diff options
Diffstat (limited to 'fpga/usrp2/top/u2plus')
| -rw-r--r-- | fpga/usrp2/top/u2plus/.gitignore | 1 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/Makefile | 98 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/bootloader.rmi | 256 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/capture_ddrlvds.v | 39 | ||||
| -rwxr-xr-x | fpga/usrp2/top/u2plus/u2plus.ucf | 424 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus.v | 450 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus_core.v | 708 |
7 files changed, 1976 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u2plus/.gitignore b/fpga/usrp2/top/u2plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/u2plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile new file mode 100644 index 000000000..38400ce62 --- /dev/null +++ b/fpga/usrp2/top/u2plus/Makefile @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi new file mode 100644 index 000000000..a0a3e13c5 --- /dev/null +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -0,0 +1,256 @@ +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4b10400_3a0b0b0b_0bae940c_82700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4ee2d_88080b0b_80088408; +defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; +defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; +defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; +defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; +defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; +defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; +defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88; +defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06; +defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; +defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; +defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; +defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; +defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; +defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_80738306_0b0b0bae_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_a82d5050_0b0b0b9e_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_da2d5050_0b0b0b9f_88087575_80088408; +defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; +defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; +defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae900c_810b0b0b; +defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; +defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; +defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_8e3f0410_81f33f9e; +defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; +defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; +defparam bootram.RAM0.INIT_23=256'hd00c8290_a0800bb5_b5cc0c82_0b0b0b0b_38838080_08822eb9_a138ae94_9008802e; +defparam bootram.RAM0.INIT_24=256'h80808480_b5d00cf8_8082800b_cc0cf880_0b0b0bb5_8080a40b_0c04f880_800bb5d4; +defparam bootram.RAM0.INIT_25=256'h0ba6c00b_d00c0b0b_80940bb5_0c80c0a8_0b0bb5cc_808c0b0b_0480c0a8_0bb5d40c; +defparam bootram.RAM0.INIT_26=256'hae9c0c70_92388412_5270802e_08700852_a338ae9c_d8335170_ff3d0db5_b5d40c04; +defparam bootram.RAM0.INIT_27=256'hc808802e_0b0b0bb5_04803d0d_833d0d04_0bb5d834_70f03881_70085252_2dae9c08; +defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5c8_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; +defparam bootram.RAM0.INIT_29=256'h518bc33f_d0055273_3fb23dfe_5254868c_59923d70_3dfee005_d03d0db2_3d0d0404; +defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_c33fa6c4_52735198_38765378_ff74278f_775482ff_8008b238; +defparam bootram.RAM0.INIT_2B=256'hb039fc3d_858a3fff_39a6fc51_a6c85184_3f91d13f_c4518598_068f38a6_812e0981; +defparam bootram.RAM0.INIT_2C=256'h3fa78051_ef3f86e5_85e63f8e_81e08c0c_8b3f800b_80e4518a_81e08c0c_0d81ff0b; +defparam bootram.RAM0.INIT_2D=256'h51547380_70810651_08708d2a_3f81b8b4_805182ed_81ff0655_ee3f8008_84e23f83; +defparam bootram.RAM0.INIT_2E=256'h80805380_82c33f83_a6388151_8008802e_5190c43f_81fc8080_5184bd3f_c338a7ac; +defparam bootram.RAM0.INIT_2F=256'h88518484_3f8a39a8_735191a0_5184913f_d33fa7cc_8eb93f90_fc808051_ffff5281; +defparam bootram.RAM0.INIT_30=256'h5183e53f_9938a98c_8008802e_518faf3f_3fb0800a_e05183f8_74b238a8_3ffea13f; +defparam bootram.RAM0.INIT_31=256'h8fd53f80_98800a51_5183cd3f_e73fa9c4_800a5190_88ee3fb0_3f82ac51_815181f9; +defparam bootram.RAM0.INIT_32=256'h5183a53f_ca3faac0_800a518d_ffff5298_80805380_83ba3f83_38aa9451_08802eaa; +defparam bootram.RAM0.INIT_33=256'h80085480_518f983f_81fc8080_5183913f_ba39aba0_3faae451_b33f8fd8_82ac5188; +defparam bootram.RAM0.INIT_34=256'hac5187f8_82ea3f82_3faac051_80518d8f_5281fc80_5380ffff_38838080_08802eb5; +defparam bootram.RAM0.INIT_35=256'h82c63ffc_39a88851_3f81548a_80518fe4_5187e93f_db3f82ac_a7cc5182_3f8f9d3f; +defparam bootram.RAM0.INIT_36=256'hb7387581_54807425_74ff1656_5a575758_7a7c7f7f_04f83d0d_0c863d0d_e33f7380; +defparam bootram.RAM0.INIT_37=256'hff065185_05527781_538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473; +defparam bootram.RAM0.INIT_38=256'h04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a51878c_81ff0654_de3f8008; +defparam bootram.RAM0.INIT_39=256'hd051ff89_81f75280_3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533; +defparam bootram.RAM0.INIT_3A=256'h70525684_02a70533_3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d; +defparam bootram.RAM0.INIT_3B=256'h3f800881_755183c1_76537b52_77259738_2e9e3880_56547380_81ff0670_fe3f8008; +defparam bootram.RAM0.INIT_3C=256'h5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056; +defparam bootram.RAM0.INIT_3D=256'h3d0d04fb_75800c88_83388156_2e098106_567480de_883d3356_a03f800b_80d051ff; +defparam bootram.RAM0.INIT_3E=256'h5581c03f_06537652_157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779; +defparam bootram.RAM0.INIT_3F=256'h800b800c_5181a43f_3f8a5272_705253cb_0d747653_0d04fe3d_800c873d_e539800b; +defparam bootram.RAM1.INIT_00=256'h81135374_55558439_76787055_04fc3d0d_3f833d0d_528051de_ff3d0d73_843d0d04; +defparam bootram.RAM1.INIT_01=256'h863d0d04_3473800c_e7388073_2e098106_0652718a_800881ff_80087334_5181bc3f; +defparam bootram.RAM1.INIT_02=256'h0d04ff3d_1234823d_0533aea0_7251028f_04803d0d_3f833d0d_528051c9_ff3d0d73; +defparam bootram.RAM1.INIT_03=256'hfe3d0d80_833d0d04_0c545151_05702272_7610abdc_82908005_14708429_0d738429; +defparam bootram.RAM1.INIT_04=256'h3d0d04fc_25e73884_13538273_51cc3f81_13335272_c43faea4_33527251_53aea013; +defparam bootram.RAM1.INIT_05=256'h527351df_0687388d_812e0981_14335372_9438aea0_2e098106_5654748a_3d0d7678; +defparam bootram.RAM1.INIT_06=256'h3d0d04ff_8c150c86_2ef83874_08537280_55538414_82908005_14708429_3f738429; +defparam bootram.RAM1.INIT_07=256'h0c833d0d_90120880_802ef838_12085170_05535188_29829080_29147084_3d0d7384; +defparam bootram.RAM1.INIT_08=256'haea80570_84517010_71258338_06515184_a408708f_880c81b8_800b81a8_04ff3d0d; +defparam bootram.RAM1.INIT_09=256'h04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c_0c70882a_0681a880_227081ff; +defparam bootram.RAM1.INIT_0A=256'h06515151_862a7081_a8900870_81863881_5171802e_55535481_05970533_76780288; +defparam bootram.RAM1.INIT_0B=256'h51515170_2a708106_90087081_900c81a8_900b81a8_a88c0c81_10810781_70f13872; +defparam bootram.RAM1.INIT_0C=256'h3880e851_71802eb1_802eba38_51515170_70813251_2a708106_90087087_f13881a8; +defparam bootram.RAM1.INIT_0D=256'h81a88c08_5170f138_81065151_70812a70_81a89008_81a8900c_38a05170_71812e83; +defparam bootram.RAM1.INIT_0E=256'h3d0d04fd_70800c85_81a8900c_3980c00b_39815188_ff1252cc_81055634_51707470; +defparam bootram.RAM1.INIT_0F=256'h38721081_515170f1_70810651_0870862a_5481a890_05335553_02880597_3d0d7678; +defparam bootram.RAM1.INIT_10=256'h06515151_812a7081_a8900870_a8900c81_90517081_2e843881_d0517180_a88c0c81; +defparam bootram.RAM1.INIT_11=256'h2e80c538_cf387180_70802e80_51515151_06708132_872a7081_a8900870_70f13881; +defparam bootram.RAM1.INIT_12=256'h70810651_0870812a_0c81a890_7081a890_83389051_5171812e_8c0c80d0_733381a8; +defparam bootram.RAM1.INIT_13=256'h14ff1353_2e8e3881_51517080_81325151_70810670_0870872a_3881a890_515170f1; +defparam bootram.RAM1.INIT_14=256'h81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80_80c00b81_81518a39_54ffb739; +defparam bootram.RAM1.INIT_15=256'h31515186_ac087074_085381b8_3881b8ac_7174259b_a2387052_51525470_70810a06; +defparam bootram.RAM1.INIT_16=256'h06515252_117081ff_0533ffa9_3d0d028f_3d0d04ff_52e23985_f1388112_8d9f7127; +defparam bootram.RAM1.INIT_17=256'h800c833d_06515170_127081ff_268938d0_515171b9_7081ff06_9638c912_7180da26; +defparam bootram.RAM1.INIT_18=256'h17335353_38810b81_810682ef_71ba2e09_5358ff53_56807633_0d797b58_0d04f93d; +defparam bootram.RAM1.INIT_19=256'h51545271_51515153_7080c406_abed1133_72197033_7081ff06_38728114_71782eaa; +defparam bootram.RAM1.INIT_1A=256'h82173352_2b9ff006_3f800884_3351fefb_d8388116_33515271_38721670_802e82bd; +defparam bootram.RAM1.INIT_1B=256'h8a388316_fd537482_33575354_10178b11_84190c70_06720570_800881ff_52feec3f; +defparam bootram.RAM1.INIT_1C=256'h06730585_2b83fe80_3f800888_5253febb_06841733_2bbfe080_3f80088c_3351fecb; +defparam bootram.RAM1.INIT_1D=256'h06730588_800881ff_53fe983f_86173352_f0067305_08842b9f_fea93f80_17335253; +defparam bootram.RAM1.INIT_1E=256'h71773474_80081252_52fdf83f_88173352_2b9ff006_3f800884_3351fe87_180c8716; +defparam bootram.RAM1.INIT_1F=256'h5152fdcf_33555256_70810552_17711970_068c1908_057081ff_38741089_742780d2; +defparam bootram.RAM1.INIT_20=256'h701a7081_08157033_74348c17_08135372_fdc13f80_72335253_2b9ff006_3f800884; +defparam bootram.RAM1.INIT_21=256'h78337205_08881808_b0388417_087526ff_51528417_5a525b51_7081ff06_ff068119; +defparam bootram.RAM1.INIT_22=256'h3f800884_5354fcf3_56545b51_1a891133_ff067310_70307081_54730519_71882a05; +defparam bootram.RAM1.INIT_23=256'h06893885_722e0981_52fb5377_81ff0651_80081270_52fce43f_8a153352_2b9ff006; +defparam bootram.RAM1.INIT_24=256'h515170f1_70810651_0870882a_0d82e090_0d04803d_800c893d_39805372_39fe5383; +defparam bootram.RAM1.INIT_25=256'he0900870_07535382_0780c080_7a8c8006_7880ff06_02930533_04fe3d0d_38823d0d; +defparam bootram.RAM1.INIT_26=256'h0c718280_0682e098_0c7581ff_7182e090_82e0800c_70f13876_06515151_882a7081; +defparam bootram.RAM1.INIT_27=256'h82e08008_5170f138_81065151_70882a70_82e09008_802e9638_0c725172_0782e090; +defparam bootram.RAM1.INIT_28=256'hff873f86_80528051_88548053_0c888055_0b82e094_fc3d0d81_843d0d04_5170800c; +defparam bootram.RAM1.INIT_29=256'h840c7c88_8b0b82e0_82e0900c_0c88800b_0b82e098_fee43f80_3d0d7d56_3d0d04f6; +defparam bootram.RAM1.INIT_2A=256'h7e558054_0cfeb33f_0b82e090_900c8aa8_a80b82e0_e0980c88_0c810b82_2b82e080; +defparam bootram.RAM1.INIT_2B=256'h82e08808_e08c0858_fe983f82_82e0900c_0c8a800b_0b82e090_d3388880_73762780; +defparam bootram.RAM1.INIT_2C=256'h52717327_38705380_70732783_52579053_3d767531_80085b88_085a82e0_5982e084; +defparam bootram.RAM1.INIT_2D=256'h980c8c3d_800b82e0_54ffa939_ec397214_34811252_70810557_51703375_91387117; +defparam bootram.RAM1.INIT_2E=256'h70335154_57557417_84059d05_d23f8002_526851fe_545780c0_0d883d70_0d04ea3d; +defparam bootram.RAM1.INIT_2F=256'h85388154_2e098106_54738199_16703351_06943874_aa2e0981_9d387381_7381ff2e; +defparam bootram.RAM1.INIT_30=256'h527951fe_70545484_3d0d863d_3d0d04f9_73800c98_d1388054_55be7527_8b398115; +defparam bootram.RAM1.INIT_31=256'h893d0d04_5574800c_06833881_752e0981_f73f8008_52735185_8453abe8_823f8055; +defparam bootram.RAM1.INIT_32=256'h72812a88_832a8406_872a0771_2a820671_05337085_3d0d0297_940c04fd_810b81e0; +defparam bootram.RAM1.INIT_33=256'h70720778_2b80c006_ff067685_07077081_a0067173_0674832b_07731090_06717307; +defparam bootram.RAM1.INIT_34=256'hd00a0681_fe3d0d74_853d0d04_52555552_52535155_c0800c51_81ff0682_872b0770; +defparam bootram.RAM1.INIT_35=256'hb251ff87_51ff8c3f_923f8199_81aa51ff_51ff983f_9e3f81ff_81ff51ff_d00a0753; +defparam bootram.RAM1.INIT_36=256'h51fee83f_feed3fb2_81ff0651_fef53f72_ff065252_882a7081_ff813f72_3f80e151; +defparam bootram.RAM1.INIT_37=256'hca3f81a1_3fb051fe_5253fecf_7081ff06_3f72902a_2a51fedb_e23f7298_818151fe; +defparam bootram.RAM1.INIT_38=256'h3f8051fe_a051feab_51feb03f_feb53f80_ba3fa051_3f8e51fe_8051febf_51fec43f; +defparam bootram.RAM1.INIT_39=256'h8025ab38_08880508_fc050c8c_800b8c08_0cf93d0d_8c08028c_0d04ff39_a63f843d; +defparam bootram.RAM1.INIT_3A=256'h08f4050c_38810b8c_fc050888_050c8c08_0b8c08f4_88050c80_08308c08_8c088805; +defparam bootram.RAM1.INIT_3B=256'h050c800b_308c088c_088c0508_25ab388c_8c050880_050c8c08_088c08fc_8c08f405; +defparam bootram.RAM1.INIT_3C=256'h0c80538c_8c08fc05_08f00508_f0050c8c_810b8c08_05088838_0c8c08fc_8c08f005; +defparam bootram.RAM1.INIT_3D=256'h802e8c38_08fc0508_050c548c_708c08f8_a73f8008_05085181_528c0888_088c0508; +defparam bootram.RAM1.INIT_3E=256'h028c0cfb_0c048c08_893d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM1.INIT_3F=256'h0c810b8c_8c088805_88050830_93388c08_05088025_0c8c0888_8c08fc05_3d0d800b; +defparam bootram.RAM2.INIT_00=256'h8c050852_81538c08_088c050c_0508308c_388c088c_0880258c_8c088c05_08fc050c; +defparam bootram.RAM2.INIT_01=256'hf8050830_8c388c08_0508802e_548c08fc_08f8050c_8008708c_0851ad3f_8c088805; +defparam bootram.RAM2.INIT_02=256'h810b8c08_0cfd3d0d_8c08028c_0d8c0c04_0c54873d_05087080_0c8c08f8_8c08f805; +defparam bootram.RAM2.INIT_03=256'h802ea338_08fc0508_27ac388c_08880508_8c05088c_050c8c08_0b8c08f8_fc050c80; +defparam bootram.RAM2.INIT_04=256'h08fc050c_0508108c_0c8c08fc_8c088c05_8c050810_99388c08_8c050824_800b8c08; +defparam bootram.RAM2.INIT_05=256'h05088c08_388c0888_050826a1_088c0888_8c088c05_2e80c938_fc050880_c9398c08; +defparam bootram.RAM2.INIT_06=256'h0508812a_0c8c08fc_8c08f805_fc050807_05088c08_0c8c08f8_8c088805_8c050831; +defparam bootram.RAM2.INIT_07=256'h388c0888_08802e8f_8c089005_0cffaf39_8c088c05_0508812a_0c8c088c_8c08fc05; +defparam bootram.RAM2.INIT_08=256'h800c853d_08f40508_050c518c_708c08f4_08f80508_518d398c_08f4050c_0508708c; +defparam bootram.RAM2.INIT_09=256'h38ff1252_70802eb0_07830651_8c387474_52837227_77795656_fc3d0d78_0d8c0c04; +defparam bootram.RAM2.INIT_0A=256'h71ff2e09_14545555_158115ff_06bd3881_712e0981_33525372_38743374_71ff2ea0; +defparam bootram.RAM2.INIT_0B=256'h8414fc14_8f388411_2e098106_70087308_74745451_863d0d04_800b800c_8106e238; +defparam bootram.RAM2.INIT_0C=256'h70797b55_fc3d0d76_863d0d04_7131800c_ffaf3972_70735555_8326e938_54545171; +defparam bootram.RAM2.INIT_0D=256'h70810554_2e983872_125271ff_2ea738ff_06517080_72750783_72278c38_5555558f; +defparam bootram.RAM2.INIT_0E=256'h70840554_04745172_0c863d0d_ea387480_2e098106_125271ff_055634ff_33747081; +defparam bootram.RAM2.INIT_0F=256'h05530c72_08717084_70840554_05530c72_08717084_70840554_05530c72_08717084; +defparam bootram.RAM2.INIT_10=256'h54087170_72708405_72279538_26c93883_1252718f_05530cf0_08717084_70840554; +defparam bootram.RAM2.INIT_11=256'h812e9838_08545472_800bae94_39fd3d0d_7054ff83_8326ed38_fc125271_8405530c; +defparam bootram.RAM2.INIT_12=256'h823fe3a0_b5dc0ce4_519b3f72_ad3f8008_528151e6_b73faeb4_e4993fe3_73b5dc0c; +defparam bootram.RAM2.INIT_13=256'h5a545a77_82c81108_7baeb808_39f73d0d_843f00ff_3f800851_8151e696_3faeb452; +defparam bootram.RAM2.INIT_14=256'hb5387382_38807424_742480e9_59555980_0581712b_841908ff_38818818_802e80d9; +defparam bootram.RAM2.INIT_15=256'h0853722d_53795174_16700853_2eb53878_06537280_80190877_05565681_2b781188; +defparam bootram.RAM2.INIT_16=256'h53bc1308_38aeb808_5877ffad_d6387708_54738025_2c5a5757_fc177981_ff14fc17; +defparam bootram.RAM2.INIT_17=256'hffa938d2_54738025_2c5a5757_fc177981_ff14fc17_0853722d_f8c03f74_a5387951; +defparam bootram.RAM2.INIT_18=256'h08525270_0bfc0570_3d0db5bc_f8943fff_722d7951_bc130853_94397251_398057ff; +defparam bootram.RAM2.INIT_19=256'h04000000_04e3893f_833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138; +defparam bootram.RAM2.INIT_1A=256'h7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040; +defparam bootram.RAM2.INIT_1B=256'h4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120; +defparam bootram.RAM2.INIT_1C=256'h61205a50_756c7472_70657220_72207375_6f616465_6f6f746c_322b2062_55535250; +defparam bootram.RAM2.INIT_1D=256'h696e2073_50322b20_20555352_74696e67_53746172_6e0a0000_6974696f_55206564; +defparam bootram.RAM2.INIT_1E=256'h6f6d206d_6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520; +defparam bootram.RAM2.INIT_1F=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20; +defparam bootram.RAM2.INIT_20=256'h61726520_69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065; +defparam bootram.RAM2.INIT_21=256'h6b2e2046_62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167; +defparam bootram.RAM2.INIT_22=256'h2e000000_2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20; +defparam bootram.RAM2.INIT_23=256'h6e204650_6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563; +defparam bootram.RAM2.INIT_24=256'h20465047_74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069; +defparam bootram.RAM2.INIT_25=256'h20626f6f_6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d; +defparam bootram.RAM2.INIT_26=256'h20696d61_46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000; +defparam bootram.RAM2.INIT_27=256'h2070726f_6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066; +defparam bootram.RAM2.INIT_28=256'h6f647563_64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374; +defparam bootram.RAM2.INIT_29=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; +defparam bootram.RAM2.INIT_2A=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; +defparam bootram.RAM2.INIT_2B=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; +defparam bootram.RAM2.INIT_2C=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; +defparam bootram.RAM2.INIT_2D=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; +defparam bootram.RAM2.INIT_2E=256'h14580a2c_2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20; +defparam bootram.RAM2.INIT_2F=256'h20202020_28282820_20202828_20202020_00202020_0b0b0b0b_01b200d9_05160364; +defparam bootram.RAM2.INIT_30=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; +defparam bootram.RAM2.INIT_31=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; +defparam bootram.RAM2.INIT_32=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; +defparam bootram.RAM2.INIT_33=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; +defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_37=256'h43000000_65000000_792e6578_64756d6d_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_38=256'h00001ac4_00000000_00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff; +defparam bootram.RAM2.INIT_39=256'h00000000_0000173c_000016f0_000b0000_0018000f_ffff0031_05050400_01010100; +defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00001a5c_00001a00_000019a4; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_000016fc_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001_00000000; +defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_15=256'h00000000_ffffffff_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_ffffffff; +defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/capture_ddrlvds.v b/fpga/usrp2/top/u2plus/capture_ddrlvds.v new file mode 100644 index 000000000..b9f53ff8c --- /dev/null +++ b/fpga/usrp2/top/u2plus/capture_ddrlvds.v @@ -0,0 +1,39 @@ + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk_regional; + wire ssclk_io; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(negedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/u2plus/u2plus.ucf new file mode 100755 index 000000000..5fbe55c26 --- /dev/null +++ b/fpga/usrp2/top/u2plus/u2plus.ucf @@ -0,0 +1,424 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +NET "ADC_clkout_p" LOC = "P1" ; +NET "ADC_clkout_n" LOC = "P2" ; +NET "ADCA_12_p" LOC = "Y1" ; +NET "ADCA_12_n" LOC = "Y2" ; +NET "ADCA_10_p" LOC = "W3" ; +NET "ADCA_10_n" LOC = "W4" ; +NET "ADCA_8_p" LOC = "T7" ; +NET "ADCA_8_n" LOC = "U6" ; +NET "ADCA_6_p" LOC = "U5" ; +NET "ADCA_6_n" LOC = "V5" ; +NET "ADCA_4_p" LOC = "T10" ; +NET "ADCA_4_n" LOC = "T9" ; +NET "ADCA_2_p" LOC = "V1" ; +NET "ADCA_2_n" LOC = "V2" ; +NET "ADCA_0_p" LOC = "R8" ; +NET "ADCA_0_n" LOC = "R7" ; +NET "ADCB_2_p" LOC = "U7" ; +NET "ADCB_2_n" LOC = "U8" ; +NET "ADCB_0_p" LOC = "AA2" ; +NET "ADCB_0_n" LOC = "AA3" ; +NET "ADCB_4_p" LOC = "AE1" ; +NET "ADCB_4_n" LOC = "AE2" ; +NET "ADCB_6_p" LOC = "W1" ; +NET "ADCB_6_n" LOC = "W2" ; +NET "ADCB_8_p" LOC = "U3" ; +NET "ADCB_8_n" LOC = "V4" ; +NET "ADCB_10_p" LOC = "J1" ; +NET "ADCB_10_n" LOC = "K1" ; +NET "ADCB_12_p" LOC = "J3" ; +NET "ADCB_12_n" LOC = "J2" ; + +## DAC +NET "DAC_LOCK" LOC = "P4" ; +NET "DACA<0>" LOC = "P8" ; +NET "DACA<1>" LOC = "P9" ; +NET "DACA<2>" LOC = "R5" ; +NET "DACA<3>" LOC = "R6" ; +NET "DACA<4>" LOC = "P7" ; +NET "DACA<5>" LOC = "P6" ; +NET "DACA<6>" LOC = "T3" ; +NET "DACA<7>" LOC = "T4" ; +NET "DACA<8>" LOC = "R3" ; +NET "DACA<9>" LOC = "R4" ; +NET "DACA<10>" LOC = "R2" ; +NET "DACA<11>" LOC = "N1" ; +NET "DACA<12>" LOC = "N2" ; +NET "DACA<13>" LOC = "N5" ; +NET "DACA<14>" LOC = "N4" ; +NET "DACA<15>" LOC = "M2" ; +NET "DACB<0>" LOC = "M5" ; +NET "DACB<1>" LOC = "M6" ; +NET "DACB<2>" LOC = "M4" ; +NET "DACB<3>" LOC = "M3" ; +NET "DACB<4>" LOC = "M8" ; +NET "DACB<5>" LOC = "M7" ; +NET "DACB<6>" LOC = "L4" ; +NET "DACB<7>" LOC = "L3" ; +NET "DACB<8>" LOC = "K3" ; +NET "DACB<9>" LOC = "K2" ; +NET "DACB<10>" LOC = "K5" ; +NET "DACB<11>" LOC = "K4" ; +NET "DACB<12>" LOC = "M10" ; +NET "DACB<13>" LOC = "M9" ; +NET "DACB<14>" LOC = "J5" ; +NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +NET "io_tx<15>" LOC = "K6" ; +NET "io_tx<14>" LOC = "L7" ; +NET "io_tx<13>" LOC = "H2" ; +NET "io_tx<12>" LOC = "H1" ; +NET "io_tx<11>" LOC = "L10" ; +NET "io_tx<10>" LOC = "L9" ; +NET "io_tx<9>" LOC = "G3" ; +NET "io_tx<8>" LOC = "F3" ; +NET "io_tx<7>" LOC = "K7" ; +NET "io_tx<6>" LOC = "J6" ; +NET "io_tx<5>" LOC = "E1" ; +NET "io_tx<4>" LOC = "F2" ; +NET "io_tx<3>" LOC = "J7" ; +NET "io_tx<2>" LOC = "H6" ; +NET "io_tx<1>" LOC = "F5" ; +NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +NET "io_rx<15>" LOC = "AD1" ; +NET "io_rx<14>" LOC = "AD2" ; +NET "io_rx<13>" LOC = "AC2" ; +NET "io_rx<12>" LOC = "AC3" ; +NET "io_rx<11>" LOC = "W7" ; +NET "io_rx<10>" LOC = "W6" ; +NET "io_rx<9>" LOC = "U9" ; +NET "io_rx<8>" LOC = "V8" ; +NET "io_rx<7>" LOC = "AB1" ; +NET "io_rx<6>" LOC = "AC1" ; +NET "io_rx<5>" LOC = "V7" ; +NET "io_rx<4>" LOC = "V6" ; +NET "io_rx<3>" LOC = "Y5" ; +NET "io_rx<2>" LOC = "R10" ; +NET "io_rx<1>" LOC = "R1" ; +NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +NET "FPGA_RESET" LOC = "K24" ; + +## Debug +NET "debug_clk<0>" LOC = "AA10" ; +NET "debug_clk<1>" LOC = "AD11" ; +NET "debug<0>" LOC = "AC19" ; +NET "debug<1>" LOC = "AF20" ; +NET "debug<2>" LOC = "AE20" ; +NET "debug<3>" LOC = "AC16" ; +NET "debug<4>" LOC = "AB16" ; +NET "debug<5>" LOC = "AF19" ; +NET "debug<6>" LOC = "AE19" ; +NET "debug<7>" LOC = "V15" ; +NET "debug<8>" LOC = "U15" ; +NET "debug<9>" LOC = "AE17" ; +NET "debug<10>" LOC = "AD17" ; +NET "debug<11>" LOC = "V14" ; +NET "debug<12>" LOC = "W15" ; +NET "debug<13>" LOC = "AC15" ; +NET "debug<14>" LOC = "AD14" ; +NET "debug<15>" LOC = "AC14" ; +NET "debug<16>" LOC = "AC11" ; +NET "debug<17>" LOC = "AB12" ; +NET "debug<18>" LOC = "AC12" ; +NET "debug<19>" LOC = "V13" ; +NET "debug<20>" LOC = "W13" ; +NET "debug<21>" LOC = "AE8" ; +NET "debug<22>" LOC = "AF8" ; +NET "debug<23>" LOC = "V12" ; +NET "debug<24>" LOC = "W12" ; +NET "debug<25>" LOC = "AB9" ; +NET "debug<26>" LOC = "AC9" ; +NET "debug<27>" LOC = "AC8" ; +NET "debug<28>" LOC = "AB7" ; +NET "debug<29>" LOC = "V11" ; +NET "debug<30>" LOC = "U11" ; +NET "debug<31>" LOC = "Y10" ; + +## UARTS +NET "TXD<3>" LOC = "AD20" ; +NET "TXD<2>" LOC = "AC20" ; +NET "TXD<1>" LOC = "AD19" ; +NET "RXD<3>" LOC = "AF17" ; +NET "RXD<2>" LOC = "AF15" ; +NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +NET "clk_status" LOC = "AD22" ; +NET "CLK_FUNC" LOC = "AC21" ; +NET "clk_sel<0>" LOC = "AE21" ; +NET "clk_sel<1>" LOC = "AD21" ; +NET "clk_en<1>" LOC = "AA17" ; +NET "clk_en<0>" LOC = "Y17" ; + +## I2C +NET "SDA" LOC = "V16" ; +NET "SCL" LOC = "U16" ; + +## Timing +NET "PPS_IN" LOC = "AB6" ; +NET "PPS2_IN" LOC = "AA20" ; + +## SPI +NET "SEN_CLK" LOC = "AA18" ; +NET "MOSI_CLK" LOC = "W17" ; +NET "SCLK_CLK" LOC = "V17" ; +NET "MISO_CLK" LOC = "AC10" ; + +NET "SEN_DAC" LOC = "AE7" ; +NET "SCLK_DAC" LOC = "AF5" ; +NET "MOSI_DAC" LOC = "AE6" ; +NET "MISO_DAC" LOC = "Y3" ; + +NET "SCLK_ADC" LOC = "B1" ; +NET "MOSI_ADC" LOC = "J8" ; +NET "SEN_ADC" LOC = "J9" ; + +NET "MOSI_TX_ADC" LOC = "V10" ; +NET "SEN_TX_ADC" LOC = "W10" ; +NET "SCLK_TX_ADC" LOC = "AC6" ; +NET "MISO_TX_ADC" LOC = "G1" ; + +NET "MOSI_TX_DAC" LOC = "AD6" ; +NET "SEN_TX_DAC" LOC = "AE4" ; +NET "SCLK_TX_DAC" LOC = "AF4" ; + +NET "SCLK_TX_DB" LOC = "AE3" ; +NET "MOSI_TX_DB" LOC = "AF3" ; +NET "SEN_TX_DB" LOC = "W9" ; +NET "MISO_TX_DB" LOC = "AA5" ; + +NET "MOSI_RX_ADC" LOC = "E3" ; +NET "SCLK_RX_ADC" LOC = "F4" ; +NET "SEN_RX_ADC" LOC = "D3" ; +NET "MISO_RX_ADC" LOC = "C1" ; + +NET "SCLK_RX_DAC" LOC = "E4" ; +NET "SEN_RX_DAC" LOC = "K9" ; +NET "MOSI_RX_DAC" LOC = "K8" ; + +NET "SCLK_RX_DB" LOC = "G6" ; +NET "MOSI_RX_DB" LOC = "H7" ; +NET "SEN_RX_DB" LOC = "B2" ; +NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +NET "CLK_TO_MAC" LOC = "P26" ; + +NET "GMII_TXD<7>" LOC = "G21" ; +NET "GMII_TXD<6>" LOC = "C26" ; +NET "GMII_TXD<5>" LOC = "C25" ; +NET "GMII_TXD<4>" LOC = "J21" ; +NET "GMII_TXD<3>" LOC = "H21" ; +NET "GMII_TXD<2>" LOC = "D25" ; +NET "GMII_TXD<1>" LOC = "D24" ; +NET "GMII_TXD<0>" LOC = "E26" ; +NET "GMII_TX_EN" LOC = "D26" ; +NET "GMII_TX_ER" LOC = "J19" ; +NET "GMII_GTX_CLK" LOC = "J20" ; +NET "GMII_TX_CLK" LOC = "P25" ; + +NET "GMII_RX_CLK" LOC = "P21" ; +NET "GMII_RXD<7>" LOC = "G22" ; +NET "GMII_RXD<6>" LOC = "K19" ; +NET "GMII_RXD<5>" LOC = "K18" ; +NET "GMII_RXD<4>" LOC = "E24" ; +NET "GMII_RXD<3>" LOC = "F23" ; +NET "GMII_RXD<2>" LOC = "L18" ; +NET "GMII_RXD<1>" LOC = "L17" ; +NET "GMII_RXD<0>" LOC = "F25" ; +NET "GMII_RX_DV" LOC = "F24" ; +NET "GMII_RX_ER" LOC = "L20" ; +NET "GMII_CRS" LOC = "K20" ; +NET "GMII_COL" LOC = "G23" ; + +NET "PHY_INTn" LOC = "L22" ; +NET "MDIO" LOC = "K21" ; +NET "MDC" LOC = "J23" ; +NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; + +## MIMO Interface +NET "exp_time_out_p" LOC = "Y14" ; +NET "exp_time_out_n" LOC = "AA14" ; +NET "exp_time_in_p" LOC = "N18" ; +NET "exp_time_in_n" LOC = "N17" ; +NET "exp_user_out_p" LOC = "AF14" ; +NET "exp_user_out_n" LOC = "AE14" ; +NET "exp_user_in_p" LOC = "L24" ; +NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +NET "ser_enable" LOC = "R20" ; +NET "ser_prbsen" LOC = "U23" ; +NET "ser_loopen" LOC = "R19" ; +NET "ser_rx_en" LOC = "Y21" ; +NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +NET "ser_t<15>" LOC = "V23" ; +NET "ser_t<14>" LOC = "U22" ; +NET "ser_t<13>" LOC = "V24" ; +NET "ser_t<12>" LOC = "V25" ; +NET "ser_t<11>" LOC = "W23" ; +NET "ser_t<10>" LOC = "V22" ; +NET "ser_t<9>" LOC = "T18" ; +NET "ser_t<8>" LOC = "T17" ; +NET "ser_t<7>" LOC = "Y24" ; +NET "ser_t<6>" LOC = "Y25" ; +NET "ser_t<5>" LOC = "U21" ; +NET "ser_t<4>" LOC = "T20" ; +NET "ser_t<3>" LOC = "Y22" ; +NET "ser_t<2>" LOC = "Y23" ; +NET "ser_t<1>" LOC = "U19" ; +NET "ser_t<0>" LOC = "U18" ; +NET "ser_tkmsb" LOC = "AA24" ; +NET "ser_tklsb" LOC = "AA25" ; +NET "ser_rx_clk" LOC = "P18" ; +NET "ser_r<15>" LOC = "V21" ; +NET "ser_r<14>" LOC = "U20" ; +NET "ser_r<13>" LOC = "AA22" ; +NET "ser_r<12>" LOC = "AA23" ; +NET "ser_r<11>" LOC = "V18" ; +NET "ser_r<10>" LOC = "V19" ; +NET "ser_r<9>" LOC = "AB23" ; +NET "ser_r<8>" LOC = "AC26" ; +NET "ser_r<7>" LOC = "AB26" ; +NET "ser_r<6>" LOC = "AD26" ; +NET "ser_r<5>" LOC = "AC25" ; +NET "ser_r<4>" LOC = "W20" ; +NET "ser_r<3>" LOC = "W21" ; +NET "ser_r<2>" LOC = "AC23" ; +NET "ser_r<1>" LOC = "AC24" ; +NET "ser_r<0>" LOC = "AE26" ; +NET "ser_rkmsb" LOC = "AD25" ; +NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; + +## SPI Flash +NET "flash_miso" LOC = "AF24" ; +NET "flash_clk" LOC = "AE24" ; +NET "flash_mosi" LOC = "AB15" ; +NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +#NET "PROG_B" LOC = "A2" ; +#NET "PUDC_B" LOC = "G8" ; +#NET "DONE" LOC = "AB21" ; +#NET "INIT_B" LOC = "AA15" ; + + +#NET "unnamed_net19" LOC = "AE9" ; # VS1 +#NET "unnamed_net18" LOC = "AF9" ; # VS0 +#NET "unnamed_net17" LOC = "AA12" ; # VS2 +#NET "unnamed_net16" LOC = "Y7" ; # M2 +#NET "unnamed_net15" LOC = "AC4" ; # M1 +#NET "unnamed_net14" LOC = "AD4" ; # M0 +#NET "unnamed_net13" LOC = "D4" ; # TMS +#NET "unnamed_net12" LOC = "E23" ; # TDO +#NET "unnamed_net11" LOC = "G7" ; # TDI +#NET "unnamed_net10" LOC = "A25" ; # TCK +#NET "unnamed_net20" LOC = "V20" ; # SUSPEND + + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; + +#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; + + diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v new file mode 100644 index 000000000..c0140e989 --- /dev/null +++ b/fpga/usrp2/top/u2plus/u2plus.v @@ -0,0 +1,450 @@ +`timescale 1ns / 1ps +//`define DCM_FOR_RAMCLK +////////////////////////////////////////////////////////////////////////////////// + +module u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + input ADC_clkout_p, input ADC_clkout_n, + input ADCA_12_p, input ADCA_12_n, + input ADCA_10_p, input ADCA_10_n, + input ADCA_8_p, input ADCA_8_n, + input ADCA_6_p, input ADCA_6_n, + input ADCA_4_p, input ADCA_4_n, + input ADCA_2_p, input ADCA_2_n, + input ADCA_0_p, input ADCA_0_n, + input ADCB_12_p, input ADCB_12_n, + input ADCB_10_p, input ADCB_10_n, + input ADCB_8_p, input ADCB_8_n, + input ADCB_6_p, input ADCB_6_n, + input ADCB_4_p, input ADCB_4_n, + input ADCB_2_p, input ADCB_2_n, + input ADCB_0_p, input ADCB_0_n, + + // DAC + output reg [15:0] DACA, + output reg [15:0] DACB, + input DAC_LOCK, // unused for now + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + input FPGA_RESET, + output [1:0] debug_clk, + output [31:0] debug, + output [3:1] TXD, input [3:1] RXD, // UARTs + //input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input CLK_FUNC, // FIXME is an input to control the 9510 + input clk_status, + + inout SCL, inout SDA, // I2C + + // PPS + input PPS_IN, input PPS2_IN, + + // SPI + output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, + output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, + output SEN_ADC, output SCLK_ADC, output MOSI_ADC, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, + output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, + output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, + output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, + + // GigE PHY + input CLK_TO_MAC, + + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + input GMII_RX_CLK, + input [7:0] GMII_RXD, + input GMII_RX_DV, + input GMII_RX_ER, + input GMII_COL, + input GMII_CRS, + + input PHY_INTn, // open drain + inout MDIO, + output MDC, + output PHY_RESETn, + output ETH_LED, + +// input POR, + + // Expansion + input exp_time_in_p, input exp_time_in_n, // Diff + output exp_time_out_p, output exp_time_out_n, // Diff + input exp_user_in_p, input exp_user_in_n, // Diff + output exp_user_out_p, output exp_user_out_n, // Diff + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // SRAM + inout [35:0] RAM_D, + output [20:0] RAM_A, + output [3:0] RAM_BWn, + output RAM_ZZ, + output RAM_LDn, + output RAM_OEn, + output RAM_WEn, + output RAM_CENn, + output RAM_CLK, + + // SPI Flash + output flash_cs, + output flash_clk, + output flash_mosi, + input flash_miso + ); + + wire CLK_TO_MAC_int, CLK_TO_MAC_int2; + IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); + BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_in; + IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); + defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_out; + OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); + defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + // ADC A is inverted on the schematic to facilitate a clean layout + // We account for that here by inverting it +`ifdef LVDS + wire [13:0] adc_a, adc_a_inv, adc_b; + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a_inv,adc_b})); + assign adc_a = ~adc_a_inv; +`else + reg [13:0] adc_a, adc_b; + always @(posedge dsp_clk) + begin + adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; + adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; + end +`endif // !`ifdef LVDS + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(clk270_100), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. + BUFG clk270_100_buf_i1 (.I(clk270_100), + .O(clk270_100_buf)); + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk270_100_buf), + .C1(~clk270_100_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + + + // + // Instantiate IO for Bidirectional bus to SRAM + // + wire [35:0] RAM_D_pi; + wire [35:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + generate + for (i=0;i<36;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; + + u2plus_core u2p_c(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (CLK_TO_MAC_int2), + .pps_in (PPS_IN), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .adc_a (adc_a[13:0]), + .adc_ovf_a (1'b0), + .adc_on_a (), + .adc_oe_a (), + .adc_b (adc_b[13:0]), + .adc_ovf_b (1'b0), + .adc_on_b (), + .adc_oe_b (), + .dac_a (dac_a_int[15:0]), + .dac_b (dac_b_int[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (SEN_CLK), + .sen_dac (SEN_DAC), + .sen_adc (SEN_ADC), + .sen_tx_db (SEN_TX_DB), + .sen_tx_adc (SEN_TX_ADC), + .sen_tx_dac (SEN_TX_DAC), + .sen_rx_db (SEN_RX_DB), + .sen_rx_adc (SEN_RX_ADC), + .sen_rx_dac (SEN_RX_DAC), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_po (RAM_D_po), + .RAM_D_pi (RAM_D_pi), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (TXD[3:1]), + .uart_rx_i ({1'b1,RXD[3:1]}), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2), + .button (FPGA_RESET), + .spiflash_cs (flash_cs), + .spiflash_clk (flash_clk), + .spiflash_miso (flash_miso), + .spiflash_mosi (flash_mosi) + ); + + // Drive low so that RAM does not sleep. + assign RAM_ZZ = 0; + // Byte Writes are qualified by the global write enable + // Always do 36bit operations to extram. + assign RAM_BWn = 4'b0000; + +endmodule // u2plus diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v new file mode 100644 index 000000000..22e181caf --- /dev/null +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -0,0 +1,708 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2plus_core + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_time_in, + output exp_time_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_adc, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [35:0] RAM_D_pi, + output [35:0] RAM_D_po, + output RAM_D_poe, + output [20:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output [3:0] uart_tx_o, + input [3:0] uart_rx_i, + output [3:0] uart_baud_o, + input sim_mode, + input [3:0] clock_divider, + input button, + + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi + ); + + localparam SR_MISC = 0; // 7 regs + localparam SR_SIMTIMER = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_UDP_SM = 192; // 64 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 9; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + reg wb_rst; + wire dsp_rst = wb_rst; + + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun0, overrun1, underrun; + wire [3:0] uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time, vita_time_pps; + + wire run_rx0, run_rx1, run_tx; + reg run_rx0_d1, run_rx1_d1; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + // //////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + wire por_rst; + wire [aw-1:0] cpu_adr; + + // Swap boot ram and main ram when in bootloader mode + assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : + cpu_adr ^ 16'hC000; + + system_control sysctrl + (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); + + always @(posedge wb_clk) + if(por_rst) begin + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; + wb_rst <= 1'b1; + end + else begin + case(cpu_bldr_ctrl_state) + + CPU_BLDR_CTRL_WAIT: begin + wb_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; + wb_rst <= 1'b1; + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + wb_rst <= 1'b0; + end + + endcase //cpu_bldr_ctrl_state + end + + // ///////////////////////////////////////////////////////////////////////// + // Processor + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone + // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone + // I-port connects directly to processor + + bootram bootram(.clk(wb_clk), .reset(wb_rst), + .if_adr(13'b0), .if_data(), + .dwb_adr_i(sf_adr[12:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); + +////blinkenlights v0.1 +//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; +//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; + +`include "bootloader.rmi" + + ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), + .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), + .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio({io_tx,io_rx}) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd6; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(bldr_done),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; + + setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + + assign irq= {{8'b0}, + {uart_tx_int[3:0], uart_rx_int[3:0]}, + {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // ICAP for reprogramming the FPGA, Slave #13 (D) + + s3a_icap_wb s3a_icap_wb + (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), + .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI for Flash -- Slave #14 (E) + spi_top flash_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), + .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), + .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), + .ss_pad_o(spiflash_cs), + .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 0 + wire [31:0] sample_rx0; + wire clear_rx0, strobe_rx0; + + always @(posedge dsp_clk) + run_rx0_d1 <= run_rx0; + + dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx0)); + + vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), + .debug() ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire clear_rx1, strobe_rx1; + + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; + + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx1)); + + vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), + .debug() ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + assign RAM_A[20:18] = 3'b0; + + ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(dsp_clk), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A[17:0]), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(rd1_dat), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + wire [31:0] debug_sync; + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core |