diff options
Diffstat (limited to 'fpga/usrp2/top/u2plus')
| -rw-r--r-- | fpga/usrp2/top/u2plus/.gitignore | 1 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/Makefile | 98 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/Makefile.N200 | 98 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/bootloader.rmi | 512 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/capture_ddrlvds.v | 39 | ||||
| -rwxr-xr-x | fpga/usrp2/top/u2plus/u2plus.ucf | 424 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus.v | 453 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus_core.v | 708 |
8 files changed, 0 insertions, 2333 deletions
diff --git a/fpga/usrp2/top/u2plus/.gitignore b/fpga/usrp2/top/u2plus/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/fpga/usrp2/top/u2plus/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile deleted file mode 100644 index 38400ce62..000000000 --- a/fpga/usrp2/top/u2plus/Makefile +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/Makefile.N200 b/fpga/usrp2/top/u2plus/Makefile.N200 deleted file mode 100644 index 9175f9304..000000000 --- a/fpga/usrp2/top/u2plus/Makefile.N200 +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi deleted file mode 100644 index e5be670fb..000000000 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ /dev/null @@ -1,512 +0,0 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d6cd0400_3a0b0b80_80e29c0c_82700b0b_0b0b0b0b; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d7972d_88080b0b_80088408; -defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; -defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; -defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; -defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; -defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; -defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; -defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88; -defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; -defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06; -defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; -defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; -defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; -defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; -defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; -defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; -defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; -defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; -defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_88738306_0b0b80e2_71fc0608; -defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ee2d5050_0b0b80cd_88087575_80088408; -defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_a02d5050_0b0b80cf_88087575_80088408; -defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; -defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; -defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; -defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e2980c_810b0b0b; -defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; -defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; -defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; -defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_cf943f04_82813f80; -defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010; -defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04; -defparam bootram.RAM0.INIT_23=256'h800b80e2_f40c82a0_0b0b80e2_8380800b_822ebd38_80e29c08_802ea438_80e29808; -defparam bootram.RAM0.INIT_24=256'h0b80e2f8_80808280_e2f40cf8_0b0b0b80_808080a4_fc0c04f8_800b80e2_f80c8290; -defparam bootram.RAM0.INIT_25=256'h940b80e2_80c0a880_80e2f40c_8c0b0b0b_80c0a880_e2fc0c04_84800b80_0cf88080; -defparam bootram.RAM0.INIT_26=256'h70085252_80e2a408_5170a738_80e38033_04ff3d0d_80e2fc0c_80d7c80b_f80c0b0b; -defparam bootram.RAM0.INIT_27=256'h8034833d_810b80e3_5270ee38_08700852_2d80e2a4_e2a40c70_38841280_70802e94; -defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e2f008_3d0d0b0b_0d040480; -defparam bootram.RAM0.INIT_29=256'h852eb238_5a798380_0d973d22_0404ee3d_3f823d0d_0b0bf5d4_e2f0510b_040b0b80; -defparam bootram.RAM0.INIT_2A=256'h5a953d22_819d3980_862e8f38_39798380_8e3881a7_8380842e_248b3879_79838085; -defparam bootram.RAM0.INIT_2B=256'h7053963d_f423923d_3d2280e4_39815a95_e4f8238a_953d2280_9539825a_80e4fc23; -defparam bootram.RAM0.INIT_2C=256'h7b1d7f1d_3d415e5c_0b883d99_5b5f4080_0284057b_ae3f8008_abdc3f8b_84055241; -defparam bootram.RAM0.INIT_2D=256'h79337b34_7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26_7b34811c_5b5b7933; -defparam bootram.RAM0.INIT_2E=256'h7c26ef38_811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f_7c26ed38_811c5c88; -defparam bootram.RAM0.INIT_2F=256'h3d0d686a_3d0d04ee_9d903f94_7c26ef38_811c5c86_79337b34_611d5b5b_805c7b1e; -defparam bootram.RAM0.INIT_30=256'ha23f80e1_d7cc5198_538a5280_2e8f3875_0856758a_27973876_5a578379_8412085a; -defparam bootram.RAM0.INIT_31=256'h9f185675_17085dff_5ba05c88_3fa0588a_9c51988f_a45280d8_8e387853_5878a326; -defparam bootram.RAM0.INIT_32=256'h39951733_085e82f2_cc3f8008_80c15c8a_56750804_80da8c05_38758429_95268388; -defparam bootram.RAM0.INIT_33=256'h55961733_5a515677_2a848006_70307096_3380f232_92389417_7580f22e_56888058; -defparam bootram.RAM0.INIT_34=256'h80085f80_5199b83f_38815877_75782e83_18335758_52800b97_538c1708_54901708; -defparam bootram.RAM0.INIT_35=256'h398d1733_c95c81dd_8fdb3f80_18335256_ea05538c_7054953d_398d1733_d35c82aa; -defparam bootram.RAM0.INIT_36=256'h75822488_822ea038_17335675_81c7399c_3f80c85c_525690e7_538c1833_70548e18; -defparam bootram.RAM0.INIT_37=256'h17085692_5695398c_1808710c_8c170890_8106a038_75842e09_a138a839_3875812e; -defparam bootram.RAM0.INIT_38=256'h9e387582_5675822e_399c1733_d05c81ba_33763480_08569317_8a398c17_17227623; -defparam bootram.RAM0.INIT_39=256'h17087022_5691398c_08700840_9a388c17_2e098106_a2397584_812e9d38_24883875; -defparam bootram.RAM0.INIT_3A=256'h7553943d_83389456_56947625_398d1733_d25c80fe_33405680_8c170870_40568839; -defparam bootram.RAM0.INIT_3B=256'h94762583_8d173356_3480d739_8405b505_5c800802_bc3f80d6_1733518b_ea05528c; -defparam bootram.RAM0.INIT_3C=256'h05b50534_5c750284_9d3f80d5_1733518a_8e17528c_993f7553_1733518d_3894568c; -defparam bootram.RAM0.INIT_3D=256'h57577533_963d7905_5a587719_800b833d_3ddc0554_17085594_80cc5c8c_ad39785e; -defparam bootram.RAM0.INIT_3E=256'h19963d79_3d5a5877_54800b83_943ddc05_a05ca455_ed38a439_58887826_77348118; -defparam bootram.RAM0.INIT_3F=256'h0d747053_0d04fe3d_a63f943d_8080519d_26ed3883_18588878_33773481_05575775; -defparam bootram.RAM1.INIT_00=256'h8d39a052_3f9db93f_815191ea_5188953f_38a052a0_72802e92_5394b83f_80d8e852; -defparam bootram.RAM1.INIT_01=256'h5280d9a4_89b53f86_80d98851_0d82b53f_0d04fa3d_d93f843d_3f725191_72518884; -defparam bootram.RAM1.INIT_02=256'h92b43f88_3f800851_bd3f85df_85cb3f86_3fa7f13f_c45193f3_8a5280d9_5193fc3f; -defparam bootram.RAM1.INIT_03=256'h96db3f86_52800851_85c13f73_3f800854_8c3f86b1_92ce3f88_3f800851_983f86bd; -defparam bootram.RAM1.INIT_04=256'h83808451_3f8ab252_805197a1_fb528380_96e53f8b_5190bf3f_84528008_a03f8380; -defparam bootram.RAM1.INIT_05=256'h825196f9_dd528380_97833fbe_83808651_3f8ab252_8551978d_b2528380_97973f8a; -defparam bootram.RAM1.INIT_06=256'h802e80c9_08568008_90b43f80_3dfc0551_aabb3f88_51a8a93f_bd3f8ffa_3f805190; -defparam bootram.RAM1.INIT_07=256'h055180c3_52800890_5380d9e8_06ad3884_ee2e0981_557382fd_8e052255_38768008; -defparam bootram.RAM1.INIT_08=256'h3f883974_735185dd_3f86e23f_525491a4_3f941670_f05192b3_9a3880d9_853f8008; -defparam bootram.RAM1.INIT_09=256'h8d38a00b_5573802e_81065155_70852a70_82808c08_3f8eae3f_b43f8fb9_5275519c; -defparam bootram.RAM1.INIT_0A=256'h808c0c80_80c00b82_2efef838_51547380_2a708106_9d3f7486_80d55186_82808c0c; -defparam bootram.RAM1.INIT_0B=256'h3f9f5280_aa3f89d8_889f3f8d_3f82b73f_f53f93c5_fe3d0d85_3ffee839_cf518682; -defparam bootram.RAM1.INIT_0C=256'hcf3f8852_82ac518c_5185913f_3f845284_ac518cdc_859e3f82_9f528051_5185c23f; -defparam bootram.RAM1.INIT_0D=256'h805184e8_82539f52_518cb53f_f73f82ac_52905184_8cc23f90_3f82ac51_88518584; -defparam bootram.RAM1.INIT_0E=256'h9f529e51_8025df38_ff135372_518c993f_db3f80e4_529c5184_8ca63f9f_3f80e451; -defparam bootram.RAM1.INIT_0F=256'h808c0870_803d0d82_843d0d04_810b800c_81e0840c_bf3f890b_52815184_84e33f9f; -defparam bootram.RAM1.INIT_10=256'h82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182_8b2a8106; -defparam bootram.RAM1.INIT_11=256'h30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93_57585957; -defparam bootram.RAM1.INIT_12=256'h842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e_51538054; -defparam bootram.RAM1.INIT_13=256'h73528118_51ac9a3f_ff065277_a43f7281_527b51ac_81805474_86397353_54548054; -defparam bootram.RAM1.INIT_14=256'h54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51ac8a3f_815280da_51ac923f; -defparam bootram.RAM1.INIT_15=256'hff3ffeb8_51d63f90_3f815281_c551abe1_0d815280_0d04fe3d_e63f873d_527551fe; -defparam bootram.RAM1.INIT_16=256'hfa3d0d78_843d0d04_e0800c53_70900781_81e08008_802ef338_ff065372_3f800881; -defparam bootram.RAM1.INIT_17=256'h33527181_38805471_70802e83_70335252_9e387217_53727627_70565480_7a575781; -defparam bootram.RAM1.INIT_18=256'h04fe3d0d_0c883d0d_81517080_802e8338_74075170_53df3974_80558113_ff2e8338; -defparam bootram.RAM1.INIT_19=256'h88335574_3d0d80e3_3d0d04f9_bcac3f84_80e2ac51_80dae852_88348653_810b80e3; -defparam bootram.RAM1.INIT_1A=256'h80d051ab_54568252_54873d70_24b63886_08558075_3481b8a4_0b80e388_80c63881; -defparam bootram.RAM1.INIT_1B=256'h38865375_0655748c_800881ff_51fee93f_38865275_74802e9c_81ff0655_d53f8008; -defparam bootram.RAM1.INIT_1C=256'h80e2a80c_80dae408_80e38434_0d04810b_800c893d_80e2ac0b_51bbd73f_5280e2ac; -defparam bootram.RAM1.INIT_1D=256'h38845487_807524b3_b8a40855_e3843481_38810b80_557480c3_80e38433_04fb3d0d; -defparam bootram.RAM1.INIT_1E=256'h0551fdfc_52873dfc_2e993884_06557480_800881ff_51aaeb3f_8c5280d0_3dfc0553; -defparam bootram.RAM1.INIT_1F=256'h77568454_04fb3d0d_0c873d0d_e2a80b80_e2a80c80_86387580_ff065574_3f800881; -defparam bootram.RAM1.INIT_20=256'h0b80e384_e2a80c81_38750880_74802e8d_81ff0655_b13f8008_80d051a9_75538c52; -defparam bootram.RAM1.INIT_21=256'h81e08c0c_80e38c0c_08060770_7180e38c_09737506_803d0d73_873d0d04_3474800c; -defparam bootram.RAM1.INIT_22=256'h0c51823d_0c81e098_7080e390_90080607_067180e3_73097375_04803d0d_51823d0d; -defparam bootram.RAM1.INIT_23=256'h8a528051_04ff3d0d_0c843d0d_c93f7280_53805182_0d747053_3f04fe3d_0d0482b1; -defparam bootram.RAM1.INIT_24=256'h157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779_3d0d04fb_82b83f83; -defparam bootram.RAM1.INIT_25=256'h75335556_59565880_0d797b7d_0d04f93d_800c873d_e539800b_5582933f_06537652; -defparam bootram.RAM1.INIT_26=256'h8b387581_5473802e_e53f7433_78525581_81157453_77259d38_38815680_73762ea4; -defparam bootram.RAM1.INIT_27=256'h04fe3d0d_3f833d0d_8051ff8f_3d0d7352_3d0d04ff_75800c89_7324e538_17575376; -defparam bootram.RAM1.INIT_28=256'h528051dd_ff3d0d73_843d0d04_800b800c_5181ab3f_3f8a5272_5253feff_74765370; -defparam bootram.RAM1.INIT_29=256'h73348008_c23f8008_53755181_84398113_56575556_77797b71_04fb3d0d_3f833d0d; -defparam bootram.RAM1.INIT_2A=256'h7431800c_80733472_7224db38_74315274_2e8a3872_387181ff_718a2e90_81ff0652; -defparam bootram.RAM1.INIT_2B=256'h14708429_0d738429_0d04ff3d_1234823d_3380e2b4_51028f05_803d0d72_873d0d04; -defparam bootram.RAM1.INIT_2C=256'hb4133352_805380e2_04fe3d0d_51833d0d_720c5451_f0057022_761080da_82908005; -defparam bootram.RAM1.INIT_2D=256'h0d767856_0d04fc3d_e538843d_53827325_c93f8113_33527251_80e2b813_7251c13f; -defparam bootram.RAM1.INIT_2E=256'h3f738429_527351de_0687388d_812e0981_14335372_3880e2b4_09810695_54748a2e; -defparam bootram.RAM1.INIT_2F=256'h3d0d7484_3d0d04fe_8c150c86_2ef83874_08537280_55538414_82908005_14708429; -defparam bootram.RAM1.INIT_30=256'h800c843d_12085372_2e853890_ff537080_52535181_05881108_29829080_29157084; -defparam bootram.RAM1.INIT_31=256'h38901208_70732e91_52545253_05881108_29829080_29167084_0d807584_0d04fe3d; -defparam bootram.RAM1.INIT_32=256'h0c81b8a4_0b81a888_ff3d0d80_843d0d04_3872800c_545170f1_88140852_7081ff06; -defparam bootram.RAM1.INIT_33=256'h0c70882a_0681a880_227081ff_e2bc0570_51701080_25833884_51518471_08708f06; -defparam bootram.RAM1.INIT_34=256'h55535481_05970533_76780288_04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c; -defparam bootram.RAM1.INIT_35=256'ha88c0c81_10810781_70f13872_06515151_862a7081_a8900870_81863881_5171802e; -defparam bootram.RAM1.INIT_36=256'h2a708106_90087087_f13881a8_51515170_2a708106_90087081_900c81a8_900b81a8; -defparam bootram.RAM1.INIT_37=256'h81a8900c_38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251; -defparam bootram.RAM1.INIT_38=256'hff1252cc_81055634_51707470_81a88c08_5170f138_81065151_70812a70_81a89008; -defparam bootram.RAM1.INIT_39=256'h05335553_02880597_3d0d7678_3d0d04fd_70800c85_81a8900c_3980c00b_39815188; -defparam bootram.RAM1.INIT_3A=256'h2e843881_d0517180_a88c0c81_38721081_515170f1_70810651_0870862a_5481a890; -defparam bootram.RAM1.INIT_3B=256'h872a7081_a8900870_70f13881_06515151_812a7081_a8900870_a8900c81_90517081; -defparam bootram.RAM1.INIT_3C=256'h5171812e_8c0c80d0_733381a8_2e80c538_cf387180_70802e80_51515151_06708132; -defparam bootram.RAM1.INIT_3D=256'h0870872a_3881a890_515170f1_70810651_0870812a_0c81a890_7081a890_83389051; -defparam bootram.RAM1.INIT_3E=256'h80c00b81_81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670; -defparam bootram.RAM1.INIT_3F=256'ha2387052_51525470_70810a06_81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80; -defparam bootram.RAM2.INIT_00=256'h52e23985_f1388112_8d9f7127_31515186_ac087074_085381b8_3881b8ac_7174259b; -defparam bootram.RAM2.INIT_01=256'h808c0c80_0cff0b82_0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff; -defparam bootram.RAM2.INIT_02=256'h82808808_04fb3d0d_38833d0d_708025f1_0cff1151_70840554_51a1c972_e4d45287; -defparam bootram.RAM2.INIT_03=256'h38725173_71802e8f_74760652_e4d45555_53810b80_58515280_8c087106_70098280; -defparam bootram.RAM2.INIT_04=256'h04ff3d0d_38873d0d_877325dc_10575553_13841576_0c8f3981_7482808c_0852712d; -defparam bootram.RAM2.INIT_05=256'h72068280_80880870_2b700982_0c518172_d4057571_842980e4_269f3871_73527187; -defparam bootram.RAM2.INIT_06=256'h0c833d0d_5281e0c8_81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351; -defparam bootram.RAM2.INIT_07=256'hcc0c823d_820b81e0_802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d; -defparam bootram.RAM2.INIT_08=256'hb8a00875_2e933881_54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f; -defparam bootram.RAM2.INIT_09=256'hfc51f7af_8b3880da_5271802e_70810651_3971812a_8080529a_0c535381_71902a71; -defparam bootram.RAM2.INIT_0A=256'h2ef23881_51517080_7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f; -defparam bootram.RAM2.INIT_0B=256'ha0087090_0c5281b8_0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80; -defparam bootram.RAM2.INIT_0C=256'h8638ba51_5372802e_0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170; -defparam bootram.RAM2.INIT_0D=256'h83113356_fb3d0d77_853d0d04_7327e638_81135385_52a1ca3f_14703352_f5c43f72; -defparam bootram.RAM2.INIT_0E=256'h61630290_3d0d7c7e_3d0d04f6_80ed3f87_80db8051_70335356_81113354_82113355; -defparam bootram.RAM2.INIT_0F=256'had51782d_8a387952_3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533; -defparam bootram.RAM2.INIT_10=256'h527651a9_ffbd3f77_3f800851_7651a990_80537752_79557854_77269438_76305777; -defparam bootram.RAM2.INIT_11=256'h3d0d04f7_f4ac3f82_8b053351_803d0d02_8c3d0d04_3351782d_80db8c05_a83f8008; -defparam bootram.RAM2.INIT_12=256'h387681ff_802e81d1_06575775_337081ff_5c5a5878_5208a4b0_70708405_3d0d8c3d; -defparam bootram.RAM2.INIT_13=256'ha0387580_7580f024_2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5; -defparam bootram.RAM2.INIT_14=256'h397580f5_c638818b_80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938; -defparam bootram.RAM2.INIT_15=256'h77841983_3880ec39_80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875; -defparam bootram.RAM2.INIT_16=256'h53903977_a4b05480_59568055_19710852_da397784_51792d80_56805275_12335259; -defparam bootram.RAM2.INIT_17=256'ha4b05480_59568055_19710852_92397784_81538a52_55a4b054_52595680_84197108; -defparam bootram.RAM2.INIT_18=256'h76708105_8e388052_5675802e_59567633_19710859_9e397784_51fdd03f_53905275; -defparam bootram.RAM2.INIT_19=256'h803d0d81_a0940c04_04810b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179; -defparam bootram.RAM2.INIT_1A=256'hff067b8c_05337980_3d0d0297_3d0d04fd_70f13882_06515151_882a7081_a0900870; -defparam bootram.RAM2.INIT_1B=256'h81a0900c_a0800c72_980c7781_ff0681a0_3f7683ff_555354d0_80c08007_80060770; -defparam bootram.RAM2.INIT_1C=256'h3d0d04fc_70800c85_a0800851_ffaa3f81_802e8938_0c735173_0781a090_7180c280; -defparam bootram.RAM2.INIT_1D=256'h3971902a_555351ee_73058115_10157022_278f3872_80537274_7a545555_3d0d7678; -defparam bootram.RAM2.INIT_1E=256'h86537552_04fd3d0d_0c863d0d_ec397180_902a0552_ffff0672_8d387183_5170802e; -defparam bootram.RAM2.INIT_1F=256'h80720c88_a8528551_3d0d80e3_3d0d04ff_a00c5485_700880e3_aaf83f76_80e39851; -defparam bootram.RAM2.INIT_20=256'h52702254_80e3a452_2253800b_0d029605_0d04fd3d_f338833d_52708025_12ff1252; -defparam bootram.RAM2.INIT_21=256'h787a7183_04fa3d0d_0c853d0d_80517080_7225ee38_12525285_38811288_72742e8e; -defparam bootram.RAM2.INIT_22=256'h80e3a455_80e3a80b_ad398008_0884050c_89387680_8008802e_5856c73f_ffff0653; -defparam bootram.RAM2.INIT_23=256'h73237684_988c3f75_7525eb38_14545585_38811588_71802e8f_88155552_55557308; -defparam bootram.RAM2.INIT_24=256'h88055291_7353923d_54a9c73f_3dd60552_933d5392_0d867054_0d04f13d_140c883d; -defparam bootram.RAM2.INIT_25=256'h23800b8c_8405a605_3d238002_8a800b8b_a2052381_80028405_a9b83f90_3ddc0551; -defparam bootram.RAM2.INIT_26=256'h5e80538a_23685d66_8405ae05_3d238002_c0910b8d_aa052380_80028405_3d238180; -defparam bootram.RAM2.INIT_27=256'h05ba0523_3d220284_903d2396_23983d22_8405ae05_3f800802_0551fdb7_52913de4; -defparam bootram.RAM2.INIT_28=256'h9a903f91_e6840551_80c02981_d4055269_ac53913d_05be0523_23800284_800b913d; -defparam bootram.RAM2.INIT_29=256'h80e39852_a53f8653_f20551a8_3d529a3d_2386539b_800b973d_3d0d805b_3d0d04e8; -defparam bootram.RAM2.INIT_2A=256'h5a800b9b_08800858_f7f73f80_80e20523_22028405_0280f205_51a8973f_9a3df805; -defparam bootram.RAM2.INIT_2B=256'ha33d0840_a13d085f_905d6e5e_4659845c_45a33d08_44a13d08_f005436e_3dc41143; -defparam bootram.RAM2.INIT_2C=256'h75085473_3873760c_73752784_51565a55_90807131_1a787c31_58750870_8c3d5684; -defparam bootram.RAM2.INIT_2D=256'h3f750853_a851eedc_883880db_5473802e_16088306_738c3894_73830654_802e9a38; -defparam bootram.RAM2.INIT_2E=256'h26843880_ac3878bf_778025ff_ff195957_05570817_3f757084_765198e6_94160852; -defparam bootram.RAM2.INIT_2F=256'h1f94055a_943d237f_818a800b_6b6e4040_04ea3d0d_3f9a3d0d_2a51f781_c0597882; -defparam bootram.RAM2.INIT_30=256'h5a79963d_80c08007_ce052369_02840580_23818080_800b953d_80ca0523_79028405; -defparam bootram.RAM2.INIT_31=256'h8008095a_5cfae43f_933d7052_80538a52_08466847_2380e3a0_0580d205_23800284; -defparam bootram.RAM2.INIT_32=256'h923880db_ff065a79_3f800881_5c5e8a8e_983d7053_913d7053_80d20523_79028405; -defparam bootram.RAM2.INIT_33=256'h54908053_5d94557b_60586b57_7f5a6d59_3fa93902_cf3fec8d_3f7a51f6_d451f7db; -defparam bootram.RAM2.INIT_34=256'h3d0d7f58_3d0d04f7_fd8d3f98_7c26ef38_811c5c86_79337b34_7c1f5b5b_805c7b1d; -defparam bootram.RAM2.INIT_35=256'h05237756_028405a6_8b3d2380_88185776_05a20523_3d220284_8a3d238d_02ae0522; -defparam bootram.RAM2.INIT_36=256'h90800284_0b8e3d23_ee3d0d81_8b3d0d04_51fe9e3f_5391527d_8b3df805_7e558854; -defparam bootram.RAM2.INIT_37=256'h80085294_be3f8653_b60523e8_81028405_05b50534_34840284_860b8f3d_05b20523; -defparam bootram.RAM2.INIT_38=256'h3df60551_53805294_a4c83f86_3df20551_80085294_983f8453_a4d83fe9_3dec0551; -defparam bootram.RAM2.INIT_39=256'h8653805b_e4055490_9c55943d_80578056_80598058_0843025c_fc3f8008_a5d53fe8; -defparam bootram.RAM2.INIT_3A=256'haa3d088e_04d93d0d_3f943d0d_ef38fbcf_5b867b26_7a34811b_dba01b33_7a1c5a80; -defparam bootram.RAM2.INIT_3B=256'h8d387952_5b799b26_29f2055b_ac3d0884_9d38901d_09810682_7d90862e_11225f5d; -defparam bootram.RAM2.INIT_3C=256'h802e0981_225a7990_a838821b_09810686_5a79812e_b4397a22_f5b93f86_80dc8451; -defparam bootram.RAM2.INIT_3D=256'h85ff389e_2e098106_225a7981_8c38861b_09810686_798c842e_841b225a_06869a38; -defparam bootram.RAM2.INIT_3E=256'h0551a28a_a93dffa8_80e3a052_08438453_87c33f80_1d70525f_87cb3fa8_1d705240; -defparam bootram.RAM2.INIT_3F=256'h821b2202_22a13d23_a2e83f7a_98527951_865380e3_38a73d5a_800885d5_3f80085c; -defparam bootram.RAM3.INIT_00=256'h05238653_84058182_05348202_84058181_851b3302_33a23d34_0523841b_840580fe; -defparam bootram.RAM3.INIT_01=256'h5b865398_02818e05_5aa2a73f_3dea0552_547f53aa_b53f8470_e40551a2_7952a93d; -defparam bootram.RAM3.INIT_02=256'ha2803f02_7a527e51_3d5f8653_a28c3f9e_3df40551_537f52a9_a2983f79_1d527a51; -defparam bootram.RAM3.INIT_03=256'h811c5c86_79337b34_7f1d5b5b_7d537b1d_3ddc0554_5d9c55a9_7c587c57_7c5a7c59; -defparam bootram.RAM3.INIT_04=256'h5b5b6084_708c2a43_901d7022_0684aa38_802e0981_b4397d90_f99d3f84_7c26ef38; -defparam bootram.RAM3.INIT_05=256'hffff065e_861b2280_06848638_852e0981_06515a79_882a708f_84973879_2e098106; -defparam bootram.RAM3.INIT_06=256'h5580e3a0_7d901c62_8338815f_993f8008_821d51a0_80dba052_7d5f8653_7d83fa38; -defparam bootram.RAM3.INIT_07=256'h5183fe3f_1d529c1d_83c73888_387b802e_815c7e87_80088338_5ca0833f_5470535b; -defparam bootram.RAM3.INIT_08=256'h087a08a4_a4388c1b_09810683_387f912e_812e81bb_415d407f_1c22ec11_891b3382; -defparam bootram.RAM3.INIT_09=256'h1de41d82_838339ac_51f2883f_5280dca4_3879537e_7e7a2e8f_5d5d4240_1f841122; -defparam bootram.RAM3.INIT_0A=256'h3d405a88_499a3d99_993d237f_ec387a22_08802e82_80084280_5df5c73f_1d22535d; -defparam bootram.RAM3.INIT_0B=256'h8853a93d_3d236047_821b2297_519feb3f_5379527f_9c3d4088_519ff73f_537e5279; -defparam bootram.RAM3.INIT_0C=256'h1d7f1d5b_3d5e5c7b_7c557d84_cd3f7b56_527e519f_3f885379_79519fd6_ffb40552; -defparam bootram.RAM3.INIT_0D=256'h887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c_5b79337b; -defparam bootram.RAM3.INIT_0E=256'h2e818138_8a387e88_427e832e_7033415b_1b08a41e_81f3398c_085a792d_38618405; -defparam bootram.RAM3.INIT_0F=256'h810681bd_79912e09_1e335b5b_80c01db5_0680e838_832e0981_1a335a79_81db3981; -defparam bootram.RAM3.INIT_10=256'h840c7d81_0c7d81e1_0b81e180_9438810a_2e098106_5c5a797b_80e4fc22_38821b22; -defparam bootram.RAM3.INIT_11=256'hc40c7d81_0c7d81e2_0b81e2c0_9438810a_2e098106_225b797b_3980e4f8_e1880cb3; -defparam bootram.RAM3.INIT_12=256'h3f80de39_e951e48a_e4d00c80_86387d81_2e098106_225b797b_3980e4f4_e2c80c93; -defparam bootram.RAM3.INIT_13=256'h22963d23_0523841a_840580ce_05347d02_840580cd_3d347d02_5d5d7d95_ac1de41d; -defparam bootram.RAM3.INIT_14=256'h527c51f1_537b812a_8a3f8008_70525bf2_6052943d_05237d53_840580d2_861a2202; -defparam bootram.RAM3.INIT_15=256'h3fa93d0d_6151f6b1_7a537f52_7c557e54_05237b56_840580ce_095a7902_fe3f8008; -defparam bootram.RAM3.INIT_16=256'h8c135351_56517108_80e3dc54_38767008_727427a4_d4085553_800b80e3_04fc3d0d; -defparam bootram.RAM3.INIT_17=256'h04fb3d0d_0c863d0d_ff517080_7326e738_81135373_72518b39_81068538_70752e09; -defparam bootram.RAM3.INIT_18=256'he3d40c8e_38811480_73872689_e3d40854_25ba3880_3f800880_5755ffb9_77797153; -defparam bootram.RAM3.INIT_19=256'h54865375_dc120c51_760880e3_1470822b_0c547310_0680e3d8_08811187_3980e3d8; -defparam bootram.RAM3.INIT_1A=256'h813f873d_e005519c_842980e3_53755273_08055486_80081080_14519439_5280e3e0; -defparam bootram.RAM3.INIT_1B=256'h842980e3_54865373_10800805_99388008_73800824_d83f8054_0d7551fe_0d04fd3d; -defparam bootram.RAM3.INIT_1C=256'h2b71902b_12337198_75703381_04fd3d0d_0c853d0d_81547380_519bd73f_e0055276; -defparam bootram.RAM3.INIT_1D=256'h0d883d70_0d04ea3d_5452853d_52535456_7107800c_07831633_70882b72_07821433; -defparam bootram.RAM3.INIT_1E=256'h9d387381_7381ff2e_70335154_57557417_84059d05_b43f8002_52685194_545780c0; -defparam bootram.RAM3.INIT_1F=256'h55be7527_8b398115_85388154_2e098106_54738199_16703351_06943874_aa2e0981; -defparam bootram.RAM3.INIT_20=256'h845380dc_e43f8055_52795193_70545484_3d0d863d_3d0d04f9_73800c98_d1388054; -defparam bootram.RAM3.INIT_21=256'he0940c04_04810b81_0c893d0d_81557480_81068338_08752e09_99c43f80_c8527351; -defparam bootram.RAM3.INIT_22=256'h81065151_708d2a70_81b8b408_5189bb3f_ff065580_3f800881_d13f8abc_fc3d0d8d; -defparam bootram.RAM3.INIT_23=256'h8008802e_51febf3f_3fb0800a_8451e1a4_b53880dd_81833974_80dccc51_54738838; -defparam bootram.RAM3.INIT_24=256'hdde85180_84b53f80_b0800a51_51e6d93f_813f82ac_3f815189_b051e190_9a3880dd; -defparam bootram.RAM3.INIT_25=256'hff529880_805380ff_e33f8380_deb451e0_2ebb3880_3f800880_0a51fee3_cc399880; -defparam bootram.RAM3.INIT_26=256'h82ac51e6_51e0bd3f_3f80df84_9b3ffee5_82ac51e6_51e0cd3f_3f80dee0_0a5192b9; -defparam bootram.RAM3.INIT_27=256'h0d757053_0c04fd3d_7180e4bc_863d0d04_51e0a93f_3980dfc0_83e93f88_8b3f8051; -defparam bootram.RAM3.INIT_28=256'h2d853d0d_38735172_72802e85_e4bc0853_de9a3f80_a052a051_54eab83f_80e08c52; -defparam bootram.RAM3.INIT_29=256'h04fc3d0d_2d843d0d_38805172_72802e85_e4bc0853_ddfe3f80_a0528051_04fe3d0d; -defparam bootram.RAM3.INIT_2A=256'h08868006_38820b80_802e80ec_54815571_81065153_08862a70_3fff0b80_9a518987; -defparam bootram.RAM3.INIT_2B=256'h54718480_8a3987e8_802e8e38_388a5471_8280248a_2e9b3871_54718280_535580e4; -defparam bootram.RAM3.INIT_2C=256'h83067207_088a2c70_2a8c0680_ba3f7188_52855188_c23f8008_54845188_2e8338ff; -defparam bootram.RAM3.INIT_2D=256'hc8110852_8c0680e2_3f71822b_5452debb_c4555351_c80c80e0_337080e4_80e18411; -defparam bootram.RAM3.INIT_2E=256'ha338fec1_2e098106_a6387481_0c74822e_7480e4c0_082e9838_7480e4c0_52ded53f; -defparam bootram.RAM3.INIT_2F=256'h51fdfb3f_fea73f73_80e4c40c_2e8e3873_80e4c408_06963873_822e0981_3f9e3974; -defparam bootram.RAM3.INIT_30=256'h0b80e4c4_e4c00cff_3f800b80_0851879c_daa93f80_04fd3d0d_3f863d0d_995187c7; -defparam bootram.RAM3.INIT_31=256'he03f8451_528451e4_c73fbabd_529c5187_3f81ae80_985187d0_a63f8d52_0c995187; -defparam bootram.RAM3.INIT_32=256'h8d388008_7380082e_5186f43f_87aa3f84_53548451_f49f0670_08908007_87893f80; -defparam bootram.RAM3.INIT_33=256'h0d04fd3d_833f853d_52805187_08848007_86dd3f80_d63f8051_e0dc51e7_53735280; -defparam bootram.RAM3.INIT_34=256'h73109006_71730707_812a8806_2a840672_2a077183_82067187_3370852a_0d029705; -defparam bootram.RAM3.INIT_35=256'hff0682c0_2b077081_72077887_80c00670_0676852b_077081ff_06717307_74832ba0; -defparam bootram.RAM3.INIT_36=256'hff51ff9e_0a075381_0a0681d0_3d0d74d0_3d0d04fe_55555285_53515552_800c5152; -defparam bootram.RAM3.INIT_37=256'h813f7288_80e151ff_51ff873f_ff8c3fb2_3f819951_aa51ff92_ff983f81_3f81ff51; -defparam bootram.RAM3.INIT_38=256'h3f72982a_8151fee2_fee83f81_ed3fb251_ff0651fe_f53f7281_065252fe_2a7081ff; -defparam bootram.RAM3.INIT_39=256'h51febf3f_fec43f80_3f81a151_b051feca_53fecf3f_81ff0652_72902a70_51fedb3f; -defparam bootram.RAM3.INIT_3A=256'h04ffaf3d_3f843d0d_8051fea6_51feab3f_feb03fa0_b53f8051_3fa051fe_8e51feba; -defparam bootram.RAM3.INIT_3B=256'h9451e5bf_945280e1_38775382_82932690_58595777_08841208_0880da3d_0d80d83d; -defparam bootram.RAM3.INIT_3C=256'h80ca3875_7580e426_2e80e938_387580e4_80e62698_80cc3875_7580e62e_3f81d039; -defparam bootram.RAM3.INIT_3D=256'h81953975_2e80f738_387580f2_80f3268b_819b3875_7580f32e_3881ac39_80e12ea5; -defparam bootram.RAM3.INIT_3E=256'h8c943f80_3f800841_80398c90_08084181_d7d33f80_3980c15f_da38818b_80f72e80; -defparam bootram.RAM3.INIT_3F=256'h5f80d639_f93f80c5_e0055189_80d33dfd_8c170852_90170853_5f80ee39_084280c6; -defparam bootram.RAM4.INIT_00=256'h5fb73994_bc3980c2_3880c45f_75802e86_81ff0656_bb3f8008_e005518a_80d33dfd; -defparam bootram.RAM4.INIT_01=256'h528c1708_53901708_3dfe8005_a43980d3_3f80d75f_085188dd_08528c17_17539017; -defparam bootram.RAM4.INIT_02=256'hec055480_80d33dfd_5f829455_3f8339a0_8051fcff_3980d35f_80d25f8d_518bba3f; -defparam bootram.RAM4.INIT_03=256'h8251ec9b_ec388380_58887826_77348118_57577533_d53d7905_58771980_0b833d5a; -defparam bootram.RAM4.INIT_04=256'h028405ab_02a70533_3ff93d0d_ff518398_51d8e03f_0d80e1e0_0d04803d_3f80d33d; -defparam bootram.RAM4.INIT_05=256'h0d7a7c7f_0d04f83d_9e3f893d_528051e5_54755381_88805598_2b075757_05337188; -defparam bootram.RAM4.INIT_06=256'h58330284_76708105_738a3d34_81175754_25b73875_56548074_5874ff16_7f5a5757; -defparam bootram.RAM4.INIT_07=256'hef3f7380_548a51dd_0881ff06_dcc13f80_81ff0651_fc055277_82538a3d_05a10534; -defparam bootram.RAM4.INIT_08=256'hdc567588_56748338_335580de_0d02a305_0d04fa3d_800c8a3d_39815473_2e8538c1; -defparam bootram.RAM4.INIT_09=256'hab053389_0d7c5702_0d04f93d_893f883d_80d051ff_5381f752_883dfc05_3d348154; -defparam bootram.RAM4.INIT_0A=256'h802e9e38_70565473_0881ff06_dbe13f80_33705256_5202a705_893dfc05_3d348153; -defparam bootram.RAM4.INIT_0B=256'h5574800c_2e833881_56547380_81ff0670_a43f8008_527551da_3876537b_80772597; -defparam bootram.RAM4.INIT_0C=256'h56567480_0b883d33_ffa03f80_5280d051_055381f7_54883dfc_fa3d0d81_893d0d04; -defparam bootram.RAM4.INIT_0D=256'h0ca60b81_0b81c080_940c80eb_990b81c0_883d0d04_5675800c_06833881_de2e0981; -defparam bootram.RAM4.INIT_0E=256'h820b81c0_c0980c51_70810781_2bbe8006_3d0d7288_b00c0480_b00b81c0_c0ac0c89; -defparam bootram.RAM4.INIT_0F=256'h803d0d72_823d0d04_a808800c_f13881c0_51515170_2a708106_a4087081_a00c81c0; -defparam bootram.RAM4.INIT_10=256'h70812a70_81c0a408_81c0a00c_9c0c840b_517381c0_81c0980c_06708107_882bbe80; -defparam bootram.RAM4.INIT_11=256'h91387583_55575771_72830655_0d787a7c_ff39fa3d_823d0d04_5170f138_81065151; -defparam bootram.RAM4.INIT_12=256'h94387382_55737527_822a7255_88ca3f72_86388151_5271802e_38728306_0652718a; -defparam bootram.RAM4.INIT_13=256'h708f0680_7470842a_04fe3d0d_39883d0d_811454e9_0c525452_12700872_2b771177; -defparam bootram.RAM4.INIT_14=256'h803d0d82_843d0d04_53d3cf3f_ec113352_8f0680e1_d3dc3f72_54515353_e1ec1133; -defparam bootram.RAM4.INIT_15=256'hff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151_882a7081_e0900870; -defparam bootram.RAM4.INIT_16=256'h800c7182_387682e0_515170f1_70810651_0870882a_5382e090_c0800753_80060780; -defparam bootram.RAM4.INIT_17=256'h90087088_963882e0_5172802e_e0900c72_82800782_e0980c71_81ff0682_e0900c75; -defparam bootram.RAM4.INIT_18=256'he0940c88_0d810b82_0d04fc3d_800c843d_80085170_f13882e0_51515170_2a708106; -defparam bootram.RAM4.INIT_19=256'h81528151_548a8053_88805590_04fc3d0d_3f863d0d_8051ff87_80538052_80558854; -defparam bootram.RAM4.INIT_1A=256'hfed53f86_81528051_88548653_0d888055_0d04fc3d_800c863d_0881ff06_fef13f80; -defparam bootram.RAM4.INIT_1B=256'hff065170_3f800881_803d0deb_823d0d04_8106800c_80088132_3d0dca3f_3d0d0480; -defparam bootram.RAM4.INIT_1C=256'h8055a054_ffb43f88_9b38dd3f_75800826_5684e33f_fb3d0d77_823d0d04_802ef438; -defparam bootram.RAM4.INIT_1D=256'h80cb3d08_80c93d08_ffba3d0d_873d0d04_51fe843f_53815280_069b0a07_75fe9b0a; -defparam bootram.RAM4.INIT_1E=256'h805381ff_81a73882_73800826_54849f3f_b4387517_81ff2681_57805573_ff115657; -defparam bootram.RAM4.INIT_1F=256'h9f3f7482_fed43ffd_3ffefd3f_73518aea_cb3d0852_3f755380_52548c8f_52883d70; -defparam bootram.RAM4.INIT_20=256'h0c88a00b_0b82e098_e0800c81_c00a0782_c00a0680_900c76fe_800b82e0_e0980c88; -defparam bootram.RAM4.INIT_21=256'h0c54fe84_0882e08c_fe801570_3d558f56_ef3f80c8_e0900cfc_8aa00b82_82e0900c; -defparam bootram.RAM4.INIT_22=256'h88800b82_e0800c54_15700882_0c54fe8c_0882e084_fe881570_e0880c54_15700882; -defparam bootram.RAM4.INIT_23=256'he0980c81_38800b82_8025ffbc_16565675_3fff1690_900cfcb0_800b82e0_e0900c8a; -defparam bootram.RAM4.INIT_24=256'h082680cb_80577380_5682db3f_12575a56_797b7d72_04f93d0d_80c83d0d_5574800c; -defparam bootram.RAM4.INIT_25=256'h27833876_55577675_80743175_2ea23882_06547380_387581ff_802e80c3_38815774; -defparam bootram.RAM4.INIT_26=256'h807527e1_38745482_74802e8e_31575956_74197676_eb3f7316_527551fd_54775373; -defparam bootram.RAM4.INIT_27=256'h802e8d38_56545573_0d76787a_0d04fc3d_800c893d_3f815776_dc39fd8c_38828054; -defparam bootram.RAM4.INIT_28=256'hcb3f8008_0ca63981_160c8075_0c800b84_800b8816_74279038_ed3f8008_73135481; -defparam bootram.RAM4.INIT_29=256'h51fcc93f_88160c71_84160c71_760c7406_80083072_5281bd3f_ff165651_30707406; -defparam bootram.RAM4.INIT_2A=256'h14088415_38815388_71802e9f_06705452_800881ff_54fc983f_fd3d0d75_863d0d04; -defparam bootram.RAM4.INIT_2B=256'h0d04fc3d_800c853d_3f805372_0c51fc94_05708816_14088008_81823f88_082e9438; -defparam bootram.RAM4.INIT_2C=256'h04ff3d0d_0c863d0d_800a0680_3f8008fe_8151faa3_0a538152_a05481f9_0d888055; -defparam bootram.RAM4.INIT_2D=256'h81069338_70a02e09_06545151_800881ff_7081ff06_8008882a_a038d73f_80e4cc08; -defparam bootram.RAM4.INIT_2E=256'hc03f8008_833d0d04_3f71800c_8438f5b2_52827127_08ea1152_0c80e4cc_7180e4cc; -defparam bootram.RAM4.INIT_2F=256'h04f63d0d_082b800c_3f810b80_0c04ffa9_80082b80_f33f810b_33800c04_80e2c205; -defparam bootram.RAM4.INIT_30=256'he0800c81_7c882b82_82e0840c_900c8b0b_800b82e0_e0980c88_3f800b82_7d56f998; -defparam bootram.RAM4.INIT_31=256'h2780d338_80547376_e73f7e55_e0900cf8_8aa80b82_82e0900c_0c88a80b_0b82e098; -defparam bootram.RAM4.INIT_32=256'he084085a_88085982_085882e0_3f82e08c_900cf8cc_800b82e0_e0900c8a_88800b82; -defparam bootram.RAM4.INIT_33=256'h71175170_73279138_53805271_27833870_90537073_75315257_5b883d76_82e08008; -defparam bootram.RAM4.INIT_34=256'h803d0d72_8c3d0d04_82e0980c_a939800b_721454ff_1252ec39_05573481_33757081; -defparam bootram.RAM4.INIT_35=256'h3f800870_085182de_8c088805_8c050852_80538c08_0cfd3d0d_8c08028c_51f7893f; -defparam bootram.RAM4.INIT_36=256'h05085182_528c0888_088c0508_0d81538c_8c0cfd3d_048c0802_3d0d8c0c_800c5485; -defparam bootram.RAM4.INIT_37=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_0c048c08_853d0d8c_70800c54_b93f8008; -defparam bootram.RAM4.INIT_38=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; -defparam bootram.RAM4.INIT_39=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; -defparam bootram.RAM4.INIT_3A=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; -defparam bootram.RAM4.INIT_3B=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; -defparam bootram.RAM4.INIT_3C=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; -defparam bootram.RAM4.INIT_3D=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; -defparam bootram.RAM4.INIT_3E=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; -defparam bootram.RAM4.INIT_3F=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; -defparam bootram.RAM5.INIT_00=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; -defparam bootram.RAM5.INIT_01=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; -defparam bootram.RAM5.INIT_02=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; -defparam bootram.RAM5.INIT_03=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; -defparam bootram.RAM5.INIT_04=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; -defparam bootram.RAM5.INIT_05=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; -defparam bootram.RAM5.INIT_06=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; -defparam bootram.RAM5.INIT_07=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; -defparam bootram.RAM5.INIT_08=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; -defparam bootram.RAM5.INIT_09=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; -defparam bootram.RAM5.INIT_0A=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; -defparam bootram.RAM5.INIT_0B=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; -defparam bootram.RAM5.INIT_0C=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; -defparam bootram.RAM5.INIT_0D=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; -defparam bootram.RAM5.INIT_0E=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; -defparam bootram.RAM5.INIT_0F=256'h71028c05_3d0d7679_ff8339fc_ed387054_52718326_530cfc12_71708405_84055408; -defparam bootram.RAM5.INIT_10=256'h38737370_71ff2e93_38ff1252_70802ea2_74830651_72278a38_55535583_9f053357; -defparam bootram.RAM5.INIT_11=256'h7071902b_882b7507_0d047474_800c863d_06ef3874_ff2e0981_ff125271_81055534; -defparam bootram.RAM5.INIT_12=256'h530c7271_71708405_05530c72_72717084_8405530c_38727170_8f7227a5_07515451; -defparam bootram.RAM5.INIT_13=256'h718326f2_0cfc1252_70840553_90387271_38837227_718f26dd_0cf01252_70840553; -defparam bootram.RAM5.INIT_14=256'h5170802e_74078306_80d93871_5272802e_70545555_0d787a7c_9039fa3d_387053ff; -defparam bootram.RAM5.INIT_15=256'h81873870_3872802e_098106a9_5174712e_33743356_2eb13871_135372ff_80d438ff; -defparam bootram.RAM5.INIT_16=256'h33743356_06d13871_ff2e0981_55555272_8115ff15_fc388112_70802e80_81ff0651; -defparam bootram.RAM5.INIT_17=256'h27883871_57558373_0d047174_800c883d_51525270_06717131_067581ff_517081ff; -defparam bootram.RAM5.INIT_18=256'hff120670_09f7fbfd_38740870_72802eb1_39fc1353_5552ff97_88387476_0874082e; -defparam bootram.RAM5.INIT_19=256'hd0387476_0876082e_27d03874_57558373_84158417_51709a38_80065151_f8848281; -defparam bootram.RAM5.INIT_1A=256'h387380e4_72812e9e_9c085454_800b80e2_04fd3d0d_0c883d0d_39800b80_5552fedf; -defparam bootram.RAM5.INIT_1B=256'he4d00cff_a33f7280_800851f6_ffb9bb3f_dc528151_973f80e2_fb3fffb1_d00cffb1; -defparam bootram.RAM5.INIT_1C=256'h0d80e2e4_ff39ff3d_f6863f00_3f800851_51ffb99e_e2dc5281_b0fa3f80_b1de3fff; -defparam bootram.RAM5.INIT_1D=256'h833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138_08525270_0bfc0570; -defparam bootram.RAM5.INIT_1E=256'h6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_3f040000_04ffb289; -defparam bootram.RAM5.INIT_1F=256'h74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e_636b6574; -defparam bootram.RAM5.INIT_20=256'h21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d_6c697479; -defparam bootram.RAM5.INIT_21=256'h3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069; -defparam bootram.RAM5.INIT_22=256'h7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070_70656374; -defparam bootram.RAM5.INIT_23=256'h70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000_74202564; -defparam bootram.RAM5.INIT_24=256'h6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000_203d2025; -defparam bootram.RAM5.INIT_25=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741_720a0000; -defparam bootram.RAM5.INIT_26=256'h756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d_640a0000; -defparam bootram.RAM5.INIT_27=256'h65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000_723a2025; -defparam bootram.RAM5.INIT_28=256'h000007cc_000007cc_000007cc_000007cc_00000650_00000000_65743a20_7061636b; -defparam bootram.RAM5.INIT_29=256'h000007cc_000007a2_000007cc_000007cc_000006a5_000006bd_000007cc_000007cc; -defparam bootram.RAM5.INIT_2A=256'h00000778_000007cc_0000065d_00000715_000007cc_000006d3_000007cc_000007cc; -defparam bootram.RAM5.INIT_2B=256'h45000000_01b200d9_05160364_14580a2c_3fff0000_0050c285_c0a80a02_00000751; -defparam bootram.RAM5.INIT_2C=256'h00000000_43444546_38394142_34353637_30313233_2e256400_642e2564_25642e25; -defparam bootram.RAM5.INIT_2D=256'h656e7420_69676e6d_6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff; -defparam bootram.RAM5.INIT_2E=256'h6f6e3a20_636f6d6d_6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c; -defparam bootram.RAM5.INIT_2F=256'h666f7220_696e6720_6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c; -defparam bootram.RAM5.INIT_30=256'h3d202564_697a6520_72642073_20776569_6172703a_646c655f_0a68616e_00000000; -defparam bootram.RAM5.INIT_31=256'h3a202564_67746873_206c656e_74656e74_6e736973_696e636f_55445020_0a000000; -defparam bootram.RAM5.INIT_32=256'h696e2073_50322b20_20555352_74696e67_53746172_0b0b0b0b_00000000_2025640a; -defparam bootram.RAM5.INIT_33=256'h6172652e_69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520; -defparam bootram.RAM5.INIT_34=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000; -defparam bootram.RAM5.INIT_35=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; -defparam bootram.RAM5.INIT_36=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; -defparam bootram.RAM5.INIT_37=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; -defparam bootram.RAM5.INIT_38=256'h6820746f_726f7567_67207468_6c6c696e_2e0a4661_6f756e64_67652066_20696d61; -defparam bootram.RAM5.INIT_39=256'h6f647563_64207072_56616c69_72652e00_726d7761_6e206669_6c742d69_20627569; -defparam bootram.RAM5.INIT_3A=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; -defparam bootram.RAM5.INIT_3B=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; -defparam bootram.RAM5.INIT_3C=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; -defparam bootram.RAM5.INIT_3D=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; -defparam bootram.RAM5.INIT_3E=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; -defparam bootram.RAM5.INIT_3F=256'h2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20; -defparam bootram.RAM6.INIT_00=256'h00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265_6669726d; -defparam bootram.RAM6.INIT_01=256'h45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000_4e4f4e45; -defparam bootram.RAM6.INIT_02=256'h5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865_43000000; -defparam bootram.RAM6.INIT_03=256'h20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f_4155544f; -defparam bootram.RAM6.INIT_04=256'h6e207570_6f722069_21457272_00030203_00000001_00030003_00000000_780a0000; -defparam bootram.RAM6.INIT_05=256'h64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163_64617465; -defparam bootram.RAM6.INIT_06=256'h00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65_796c6f61; -defparam bootram.RAM6.INIT_07=256'h64756d6d_43444546_38394142_34353637_30313233_00000000_6f72740a_0a0a6162; -defparam bootram.RAM6.INIT_08=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_65000000_792e6578; -defparam bootram.RAM6.INIT_09=256'hffff0031_05050400_01010100_3fff0000_0050c285_c0a80a02_0000316c_00000000; -defparam bootram.RAM6.INIT_0A=256'h000030fc_10101200_00003038_00003030_00003028_00003020_000b0000_0018000f; -defparam bootram.RAM6.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff; -defparam bootram.RAM6.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/capture_ddrlvds.v b/fpga/usrp2/top/u2plus/capture_ddrlvds.v deleted file mode 100644 index b9f53ff8c..000000000 --- a/fpga/usrp2/top/u2plus/capture_ddrlvds.v +++ /dev/null @@ -1,39 +0,0 @@ - - -module capture_ddrlvds - #(parameter WIDTH=7) - (input clk, - input ssclk_p, - input ssclk_n, - input [WIDTH-1:0] in_p, - input [WIDTH-1:0] in_n, - output reg [(2*WIDTH)-1:0] out); - - wire [WIDTH-1:0] ddr_dat; - wire ssclk_regional; - wire ssclk_io; - wire ssclk; - wire [(2*WIDTH)-1:0] out_pre1; - reg [(2*WIDTH)-1:0] out_pre2; - - IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); - - genvar i; - generate - for(i = 0; i < WIDTH; i = i + 1) - begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds - (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); - IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 - (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), - .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); - end - endgenerate - - always @(negedge clk) - out_pre2 <= out_pre1; - - always @(posedge clk) - out <= out_pre2; - -endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/u2plus/u2plus.ucf deleted file mode 100755 index 5fbe55c26..000000000 --- a/fpga/usrp2/top/u2plus/u2plus.ucf +++ /dev/null @@ -1,424 +0,0 @@ -## Main 100 MHz Clock -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; - -## ADC -NET "ADC_clkout_p" LOC = "P1" ; -NET "ADC_clkout_n" LOC = "P2" ; -NET "ADCA_12_p" LOC = "Y1" ; -NET "ADCA_12_n" LOC = "Y2" ; -NET "ADCA_10_p" LOC = "W3" ; -NET "ADCA_10_n" LOC = "W4" ; -NET "ADCA_8_p" LOC = "T7" ; -NET "ADCA_8_n" LOC = "U6" ; -NET "ADCA_6_p" LOC = "U5" ; -NET "ADCA_6_n" LOC = "V5" ; -NET "ADCA_4_p" LOC = "T10" ; -NET "ADCA_4_n" LOC = "T9" ; -NET "ADCA_2_p" LOC = "V1" ; -NET "ADCA_2_n" LOC = "V2" ; -NET "ADCA_0_p" LOC = "R8" ; -NET "ADCA_0_n" LOC = "R7" ; -NET "ADCB_2_p" LOC = "U7" ; -NET "ADCB_2_n" LOC = "U8" ; -NET "ADCB_0_p" LOC = "AA2" ; -NET "ADCB_0_n" LOC = "AA3" ; -NET "ADCB_4_p" LOC = "AE1" ; -NET "ADCB_4_n" LOC = "AE2" ; -NET "ADCB_6_p" LOC = "W1" ; -NET "ADCB_6_n" LOC = "W2" ; -NET "ADCB_8_p" LOC = "U3" ; -NET "ADCB_8_n" LOC = "V4" ; -NET "ADCB_10_p" LOC = "J1" ; -NET "ADCB_10_n" LOC = "K1" ; -NET "ADCB_12_p" LOC = "J3" ; -NET "ADCB_12_n" LOC = "J2" ; - -## DAC -NET "DAC_LOCK" LOC = "P4" ; -NET "DACA<0>" LOC = "P8" ; -NET "DACA<1>" LOC = "P9" ; -NET "DACA<2>" LOC = "R5" ; -NET "DACA<3>" LOC = "R6" ; -NET "DACA<4>" LOC = "P7" ; -NET "DACA<5>" LOC = "P6" ; -NET "DACA<6>" LOC = "T3" ; -NET "DACA<7>" LOC = "T4" ; -NET "DACA<8>" LOC = "R3" ; -NET "DACA<9>" LOC = "R4" ; -NET "DACA<10>" LOC = "R2" ; -NET "DACA<11>" LOC = "N1" ; -NET "DACA<12>" LOC = "N2" ; -NET "DACA<13>" LOC = "N5" ; -NET "DACA<14>" LOC = "N4" ; -NET "DACA<15>" LOC = "M2" ; -NET "DACB<0>" LOC = "M5" ; -NET "DACB<1>" LOC = "M6" ; -NET "DACB<2>" LOC = "M4" ; -NET "DACB<3>" LOC = "M3" ; -NET "DACB<4>" LOC = "M8" ; -NET "DACB<5>" LOC = "M7" ; -NET "DACB<6>" LOC = "L4" ; -NET "DACB<7>" LOC = "L3" ; -NET "DACB<8>" LOC = "K3" ; -NET "DACB<9>" LOC = "K2" ; -NET "DACB<10>" LOC = "K5" ; -NET "DACB<11>" LOC = "K4" ; -NET "DACB<12>" LOC = "M10" ; -NET "DACB<13>" LOC = "M9" ; -NET "DACB<14>" LOC = "J5" ; -NET "DACB<15>" LOC = "J4" ; - -## TX DB GPIO -NET "io_tx<15>" LOC = "K6" ; -NET "io_tx<14>" LOC = "L7" ; -NET "io_tx<13>" LOC = "H2" ; -NET "io_tx<12>" LOC = "H1" ; -NET "io_tx<11>" LOC = "L10" ; -NET "io_tx<10>" LOC = "L9" ; -NET "io_tx<9>" LOC = "G3" ; -NET "io_tx<8>" LOC = "F3" ; -NET "io_tx<7>" LOC = "K7" ; -NET "io_tx<6>" LOC = "J6" ; -NET "io_tx<5>" LOC = "E1" ; -NET "io_tx<4>" LOC = "F2" ; -NET "io_tx<3>" LOC = "J7" ; -NET "io_tx<2>" LOC = "H6" ; -NET "io_tx<1>" LOC = "F5" ; -NET "io_tx<0>" LOC = "G4" ; - -## RX DB GPIO -NET "io_rx<15>" LOC = "AD1" ; -NET "io_rx<14>" LOC = "AD2" ; -NET "io_rx<13>" LOC = "AC2" ; -NET "io_rx<12>" LOC = "AC3" ; -NET "io_rx<11>" LOC = "W7" ; -NET "io_rx<10>" LOC = "W6" ; -NET "io_rx<9>" LOC = "U9" ; -NET "io_rx<8>" LOC = "V8" ; -NET "io_rx<7>" LOC = "AB1" ; -NET "io_rx<6>" LOC = "AC1" ; -NET "io_rx<5>" LOC = "V7" ; -NET "io_rx<4>" LOC = "V6" ; -NET "io_rx<3>" LOC = "Y5" ; -NET "io_rx<2>" LOC = "R10" ; -NET "io_rx<1>" LOC = "R1" ; -NET "io_rx<0>" LOC = "M1" ; - -## MISC -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -NET "FPGA_RESET" LOC = "K24" ; - -## Debug -NET "debug_clk<0>" LOC = "AA10" ; -NET "debug_clk<1>" LOC = "AD11" ; -NET "debug<0>" LOC = "AC19" ; -NET "debug<1>" LOC = "AF20" ; -NET "debug<2>" LOC = "AE20" ; -NET "debug<3>" LOC = "AC16" ; -NET "debug<4>" LOC = "AB16" ; -NET "debug<5>" LOC = "AF19" ; -NET "debug<6>" LOC = "AE19" ; -NET "debug<7>" LOC = "V15" ; -NET "debug<8>" LOC = "U15" ; -NET "debug<9>" LOC = "AE17" ; -NET "debug<10>" LOC = "AD17" ; -NET "debug<11>" LOC = "V14" ; -NET "debug<12>" LOC = "W15" ; -NET "debug<13>" LOC = "AC15" ; -NET "debug<14>" LOC = "AD14" ; -NET "debug<15>" LOC = "AC14" ; -NET "debug<16>" LOC = "AC11" ; -NET "debug<17>" LOC = "AB12" ; -NET "debug<18>" LOC = "AC12" ; -NET "debug<19>" LOC = "V13" ; -NET "debug<20>" LOC = "W13" ; -NET "debug<21>" LOC = "AE8" ; -NET "debug<22>" LOC = "AF8" ; -NET "debug<23>" LOC = "V12" ; -NET "debug<24>" LOC = "W12" ; -NET "debug<25>" LOC = "AB9" ; -NET "debug<26>" LOC = "AC9" ; -NET "debug<27>" LOC = "AC8" ; -NET "debug<28>" LOC = "AB7" ; -NET "debug<29>" LOC = "V11" ; -NET "debug<30>" LOC = "U11" ; -NET "debug<31>" LOC = "Y10" ; - -## UARTS -NET "TXD<3>" LOC = "AD20" ; -NET "TXD<2>" LOC = "AC20" ; -NET "TXD<1>" LOC = "AD19" ; -NET "RXD<3>" LOC = "AF17" ; -NET "RXD<2>" LOC = "AF15" ; -NET "RXD<1>" LOC = "AD12" ; - -## AD9510 -NET "clk_status" LOC = "AD22" ; -NET "CLK_FUNC" LOC = "AC21" ; -NET "clk_sel<0>" LOC = "AE21" ; -NET "clk_sel<1>" LOC = "AD21" ; -NET "clk_en<1>" LOC = "AA17" ; -NET "clk_en<0>" LOC = "Y17" ; - -## I2C -NET "SDA" LOC = "V16" ; -NET "SCL" LOC = "U16" ; - -## Timing -NET "PPS_IN" LOC = "AB6" ; -NET "PPS2_IN" LOC = "AA20" ; - -## SPI -NET "SEN_CLK" LOC = "AA18" ; -NET "MOSI_CLK" LOC = "W17" ; -NET "SCLK_CLK" LOC = "V17" ; -NET "MISO_CLK" LOC = "AC10" ; - -NET "SEN_DAC" LOC = "AE7" ; -NET "SCLK_DAC" LOC = "AF5" ; -NET "MOSI_DAC" LOC = "AE6" ; -NET "MISO_DAC" LOC = "Y3" ; - -NET "SCLK_ADC" LOC = "B1" ; -NET "MOSI_ADC" LOC = "J8" ; -NET "SEN_ADC" LOC = "J9" ; - -NET "MOSI_TX_ADC" LOC = "V10" ; -NET "SEN_TX_ADC" LOC = "W10" ; -NET "SCLK_TX_ADC" LOC = "AC6" ; -NET "MISO_TX_ADC" LOC = "G1" ; - -NET "MOSI_TX_DAC" LOC = "AD6" ; -NET "SEN_TX_DAC" LOC = "AE4" ; -NET "SCLK_TX_DAC" LOC = "AF4" ; - -NET "SCLK_TX_DB" LOC = "AE3" ; -NET "MOSI_TX_DB" LOC = "AF3" ; -NET "SEN_TX_DB" LOC = "W9" ; -NET "MISO_TX_DB" LOC = "AA5" ; - -NET "MOSI_RX_ADC" LOC = "E3" ; -NET "SCLK_RX_ADC" LOC = "F4" ; -NET "SEN_RX_ADC" LOC = "D3" ; -NET "MISO_RX_ADC" LOC = "C1" ; - -NET "SCLK_RX_DAC" LOC = "E4" ; -NET "SEN_RX_DAC" LOC = "K9" ; -NET "MOSI_RX_DAC" LOC = "K8" ; - -NET "SCLK_RX_DB" LOC = "G6" ; -NET "MOSI_RX_DB" LOC = "H7" ; -NET "SEN_RX_DB" LOC = "B2" ; -NET "MISO_RX_DB" LOC = "H4" ; - -## ETH PHY -NET "CLK_TO_MAC" LOC = "P26" ; - -NET "GMII_TXD<7>" LOC = "G21" ; -NET "GMII_TXD<6>" LOC = "C26" ; -NET "GMII_TXD<5>" LOC = "C25" ; -NET "GMII_TXD<4>" LOC = "J21" ; -NET "GMII_TXD<3>" LOC = "H21" ; -NET "GMII_TXD<2>" LOC = "D25" ; -NET "GMII_TXD<1>" LOC = "D24" ; -NET "GMII_TXD<0>" LOC = "E26" ; -NET "GMII_TX_EN" LOC = "D26" ; -NET "GMII_TX_ER" LOC = "J19" ; -NET "GMII_GTX_CLK" LOC = "J20" ; -NET "GMII_TX_CLK" LOC = "P25" ; - -NET "GMII_RX_CLK" LOC = "P21" ; -NET "GMII_RXD<7>" LOC = "G22" ; -NET "GMII_RXD<6>" LOC = "K19" ; -NET "GMII_RXD<5>" LOC = "K18" ; -NET "GMII_RXD<4>" LOC = "E24" ; -NET "GMII_RXD<3>" LOC = "F23" ; -NET "GMII_RXD<2>" LOC = "L18" ; -NET "GMII_RXD<1>" LOC = "L17" ; -NET "GMII_RXD<0>" LOC = "F25" ; -NET "GMII_RX_DV" LOC = "F24" ; -NET "GMII_RX_ER" LOC = "L20" ; -NET "GMII_CRS" LOC = "K20" ; -NET "GMII_COL" LOC = "G23" ; - -NET "PHY_INTn" LOC = "L22" ; -NET "MDIO" LOC = "K21" ; -NET "MDC" LOC = "J23" ; -NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; - -## MIMO Interface -NET "exp_time_out_p" LOC = "Y14" ; -NET "exp_time_out_n" LOC = "AA14" ; -NET "exp_time_in_p" LOC = "N18" ; -NET "exp_time_in_n" LOC = "N17" ; -NET "exp_user_out_p" LOC = "AF14" ; -NET "exp_user_out_n" LOC = "AE14" ; -NET "exp_user_in_p" LOC = "L24" ; -NET "exp_user_in_n" LOC = "M23" ; - -## SERDES -NET "ser_enable" LOC = "R20" ; -NET "ser_prbsen" LOC = "U23" ; -NET "ser_loopen" LOC = "R19" ; -NET "ser_rx_en" LOC = "Y21" ; -NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -NET "ser_t<15>" LOC = "V23" ; -NET "ser_t<14>" LOC = "U22" ; -NET "ser_t<13>" LOC = "V24" ; -NET "ser_t<12>" LOC = "V25" ; -NET "ser_t<11>" LOC = "W23" ; -NET "ser_t<10>" LOC = "V22" ; -NET "ser_t<9>" LOC = "T18" ; -NET "ser_t<8>" LOC = "T17" ; -NET "ser_t<7>" LOC = "Y24" ; -NET "ser_t<6>" LOC = "Y25" ; -NET "ser_t<5>" LOC = "U21" ; -NET "ser_t<4>" LOC = "T20" ; -NET "ser_t<3>" LOC = "Y22" ; -NET "ser_t<2>" LOC = "Y23" ; -NET "ser_t<1>" LOC = "U19" ; -NET "ser_t<0>" LOC = "U18" ; -NET "ser_tkmsb" LOC = "AA24" ; -NET "ser_tklsb" LOC = "AA25" ; -NET "ser_rx_clk" LOC = "P18" ; -NET "ser_r<15>" LOC = "V21" ; -NET "ser_r<14>" LOC = "U20" ; -NET "ser_r<13>" LOC = "AA22" ; -NET "ser_r<12>" LOC = "AA23" ; -NET "ser_r<11>" LOC = "V18" ; -NET "ser_r<10>" LOC = "V19" ; -NET "ser_r<9>" LOC = "AB23" ; -NET "ser_r<8>" LOC = "AC26" ; -NET "ser_r<7>" LOC = "AB26" ; -NET "ser_r<6>" LOC = "AD26" ; -NET "ser_r<5>" LOC = "AC25" ; -NET "ser_r<4>" LOC = "W20" ; -NET "ser_r<3>" LOC = "W21" ; -NET "ser_r<2>" LOC = "AC23" ; -NET "ser_r<1>" LOC = "AC24" ; -NET "ser_r<0>" LOC = "AE26" ; -NET "ser_rkmsb" LOC = "AD25" ; -NET "ser_rklsb" LOC = "Y20" ; - -## SRAM -NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; - -## SPI Flash -NET "flash_miso" LOC = "AF24" ; -NET "flash_clk" LOC = "AE24" ; -NET "flash_mosi" LOC = "AB15" ; -NET "flash_cs" LOC = "AA7" ; - -## MISC FPGA, unused for now -#NET "PROG_B" LOC = "A2" ; -#NET "PUDC_B" LOC = "G8" ; -#NET "DONE" LOC = "AB21" ; -#NET "INIT_B" LOC = "AA15" ; - - -#NET "unnamed_net19" LOC = "AE9" ; # VS1 -#NET "unnamed_net18" LOC = "AF9" ; # VS0 -#NET "unnamed_net17" LOC = "AA12" ; # VS2 -#NET "unnamed_net16" LOC = "Y7" ; # M2 -#NET "unnamed_net15" LOC = "AC4" ; # M1 -#NET "unnamed_net14" LOC = "AD4" ; # M0 -#NET "unnamed_net13" LOC = "D4" ; # TMS -#NET "unnamed_net12" LOC = "E23" ; # TDO -#NET "unnamed_net11" LOC = "G7" ; # TDI -#NET "unnamed_net10" LOC = "A25" ; # TCK -#NET "unnamed_net20" LOC = "V20" ; # SUSPEND - - -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; - -NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; - -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; - -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; - -TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; - -#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; - - diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v deleted file mode 100644 index 7c2270df6..000000000 --- a/fpga/usrp2/top/u2plus/u2plus.v +++ /dev/null @@ -1,453 +0,0 @@ -`timescale 1ns / 1ps -//`define DCM_FOR_RAMCLK -////////////////////////////////////////////////////////////////////////////////// - -module u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - input ADC_clkout_p, input ADC_clkout_n, - input ADCA_12_p, input ADCA_12_n, - input ADCA_10_p, input ADCA_10_n, - input ADCA_8_p, input ADCA_8_n, - input ADCA_6_p, input ADCA_6_n, - input ADCA_4_p, input ADCA_4_n, - input ADCA_2_p, input ADCA_2_n, - input ADCA_0_p, input ADCA_0_n, - input ADCB_12_p, input ADCB_12_n, - input ADCB_10_p, input ADCB_10_n, - input ADCB_8_p, input ADCB_8_n, - input ADCB_6_p, input ADCB_6_n, - input ADCB_4_p, input ADCB_4_n, - input ADCB_2_p, input ADCB_2_n, - input ADCB_0_p, input ADCB_0_n, - - // DAC - output reg [15:0] DACA, - output reg [15:0] DACB, - input DAC_LOCK, // unused for now - - // DB IO Pins - inout [15:0] io_tx, - inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - input FPGA_RESET, - output [1:0] debug_clk, - output [31:0] debug, - output [3:1] TXD, input [3:1] RXD, // UARTs - //input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input CLK_FUNC, // FIXME is an input to control the 9510 - input clk_status, - - inout SCL, inout SDA, // I2C - - // PPS - input PPS_IN, input PPS2_IN, - - // SPI - output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, - output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, - output SEN_ADC, output SCLK_ADC, output MOSI_ADC, - output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, - output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, - output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, - output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, - output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, - output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, - - // GigE PHY - input CLK_TO_MAC, - - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - input GMII_RX_CLK, - input [7:0] GMII_RXD, - input GMII_RX_DV, - input GMII_RX_ER, - input GMII_COL, - input GMII_CRS, - - input PHY_INTn, // open drain - inout MDIO, - output MDC, - output PHY_RESETn, - output ETH_LED, - -// input POR, - - // Expansion - input exp_time_in_p, input exp_time_in_n, // Diff - output exp_time_out_p, output exp_time_out_n, // Diff - input exp_user_in_p, input exp_user_in_n, // Diff - output exp_user_out_p, output exp_user_out_n, // Diff - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // SRAM - inout [35:0] RAM_D, - output [20:0] RAM_A, - output [3:0] RAM_BWn, - output RAM_ZZ, - output RAM_LDn, - output RAM_OEn, - output RAM_WEn, - output RAM_CENn, - output RAM_CLK, - - // SPI Flash - output flash_cs, - output flash_clk, - output flash_mosi, - input flash_miso - ); - - wire CLK_TO_MAC_int, CLK_TO_MAC_int2; - IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); - BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); - - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire exp_user_in; - IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); - defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_user_out; - OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); - defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge clk_fpga) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - - // ADC A is inverted on the schematic to facilitate a clean layout - // We account for that here by inverting it -`ifdef LVDS - wire [13:0] adc_a, adc_a_inv, adc_b; - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a_inv,adc_b})); - assign adc_a = ~adc_a_inv; -`else - reg [13:0] adc_a, adc_b; - always @(posedge dsp_clk) - begin - adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, - ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; - adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, - ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; - end -`endif // !`ifdef LVDS - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(clk270_100), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. - BUFG clk270_100_buf_i1 (.I(clk270_100), - .O(clk270_100_buf)); - OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), - .C0(clk270_100_buf), - .C1(~clk270_100_buf), - .CE(1'b1), - .D0(1'b1), - .D1(1'b0), - .R(1'b0), - .S(1'b0)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [5:0] leds_int; - assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; - - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - - - // - // Instantiate IO for Bidirectional bus to SRAM - // - wire [35:0] RAM_D_pi; - wire [35:0] RAM_D_po; - wire RAM_D_poe; - - genvar i; - - generate - for (i=0;i<36;i=i+1) - begin : gen_RAM_D_IO - - IOBUF #( - .DRIVE(12), - .IOSTANDARD("LVCMOS25"), - .SLEW("FAST") - ) - RAM_D_i ( - .O(RAM_D_pi[i]), - .I(RAM_D_po[i]), - .IO(RAM_D[i]), - .T(RAM_D_poe) - ); - end // block: gen_RAM_D_IO - endgenerate - - - - wire [15:0] dac_a_int, dac_b_int; - // DAC A and B are swapped in schematic to facilitate clean layout - // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) DACA <= ~dac_b_int; - always @(negedge dsp_clk) DACB <= dac_a_int; - - wire pps; - assign pps = PPS_IN ^ PPS2_IN; - - u2plus_core u2p_c(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (CLK_TO_MAC_int2), - .pps_in (pps), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_time_in (exp_time_in), - .exp_time_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .adc_a (adc_a[13:0]), - .adc_ovf_a (1'b0), - .adc_on_a (), - .adc_oe_a (), - .adc_b (adc_b[13:0]), - .adc_ovf_b (1'b0), - .adc_on_b (), - .adc_oe_b (), - .dac_a (dac_a_int[15:0]), - .dac_b (dac_b_int[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (SEN_CLK), - .sen_dac (SEN_DAC), - .sen_adc (SEN_ADC), - .sen_tx_db (SEN_TX_DB), - .sen_tx_adc (SEN_TX_ADC), - .sen_tx_dac (SEN_TX_DAC), - .sen_rx_db (SEN_RX_DB), - .sen_rx_adc (SEN_RX_ADC), - .sen_rx_dac (SEN_RX_DAC), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D_po (RAM_D_po), - .RAM_D_pi (RAM_D_pi), - .RAM_D_poe (RAM_D_poe), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (TXD[3:1]), - .uart_rx_i ({1'b1,RXD[3:1]}), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2), - .button (FPGA_RESET), - .spiflash_cs (flash_cs), - .spiflash_clk (flash_clk), - .spiflash_miso (flash_miso), - .spiflash_mosi (flash_mosi) - ); - - // Drive low so that RAM does not sleep. - assign RAM_ZZ = 0; - // Byte Writes are qualified by the global write enable - // Always do 36bit operations to extram. - assign RAM_BWn = 4'b0000; - -endmodule // u2plus diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v deleted file mode 100644 index ee5d7efcd..000000000 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ /dev/null @@ -1,708 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2plus_core - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_time_in, - output exp_time_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_adc, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - input [35:0] RAM_D_pi, - output [35:0] RAM_D_po, - output RAM_D_poe, - output [20:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output [3:0] uart_tx_o, - input [3:0] uart_rx_i, - output [3:0] uart_baud_o, - input sim_mode, - input [3:0] clock_divider, - input button, - - output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi - ); - - localparam SR_MISC = 0; // 7 regs - localparam SR_SIMTIMER = 8; // 2 - localparam SR_TIME64 = 10; // 6 - localparam SR_BUF_POOL = 16; // 4 - - localparam SR_RX_FRONT = 24; // 5 - localparam SR_RX_CTRL0 = 32; // 9 - localparam SR_RX_DSP0 = 48; // 7 - localparam SR_RX_CTRL1 = 80; // 9 - localparam SR_RX_DSP1 = 96; // 7 - - localparam SR_TX_FRONT = 128; // ? - localparam SR_TX_CTRL = 144; // 6 - localparam SR_TX_DSP = 160; // 5 - - localparam SR_UDP_SM = 192; // 64 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 9; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - - reg wb_rst; - wire dsp_rst = wb_rst; - - wire [31:0] status; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun0, overrun1, underrun; - wire [3:0] uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time, vita_time_pps; - - wire run_rx0, run_rx1, run_tx; - reg run_rx0_d1, run_rx1_d1; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - - wb_1master #(.decode_w(8), - .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) - .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) - .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI - .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C - .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO - .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback - .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC - .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) - .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC - .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused - .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART - .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR - .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused - .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP - .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash - .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - - // //////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - - reg cpu_bldr_ctrl_state; - localparam CPU_BLDR_CTRL_WAIT = 0; - localparam CPU_BLDR_CTRL_DONE = 1; - - wire bldr_done; - wire por_rst; - wire [aw-1:0] cpu_adr; - - // Swap boot ram and main ram when in bootloader mode - assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : - cpu_adr ^ 16'hC000; - - system_control sysctrl - (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); - - always @(posedge wb_clk) - if(por_rst) begin - cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; - wb_rst <= 1'b1; - end - else begin - case(cpu_bldr_ctrl_state) - - CPU_BLDR_CTRL_WAIT: begin - wb_rst <= 1'b0; - if (bldr_done == 1'b1) begin //set by the bootloader - cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; - wb_rst <= 1'b1; - end - end - - CPU_BLDR_CTRL_DONE: begin //stay here forever - wb_rst <= 1'b0; - end - - endcase //cpu_bldr_ctrl_state - end - - // ///////////////////////////////////////////////////////////////////////// - // Processor - - assign bus_error = m0_err | m0_rty; - - wire [63:0] zpu_status; - zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst), - // Data Wishbone bus to system bus fabric - .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), - .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), - // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone - // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone - // I-port connects directly to processor - - bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(14'b0), .if_data(), - .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), - .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); - -////blinkenlights v0.1 -//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; -//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; - -`include "bootloader.rmi" - - ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .if_adr(14'b0), .if_data(), - .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - wire [35:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - - wire [31:0] router_debug; - - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - - .status(status), .sys_int_o(buffer_int), .debug(router_debug), - - .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), - .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), - .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), - - .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) - ); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio({io_tx,io_rx}) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd6; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), - .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), - .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - settings_bus_crossclock settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(bldr_done),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; - - setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - - setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) - sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic - wire underrun_wb, overrun_wb, pps_wb; - - oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); - oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); - oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); - - assign irq= {{8'b0}, - {uart_tx_int[3:0], uart_rx_int[3:0]}, - {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, - {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - // No longer used, replaced with simple_timer below - assign s9_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Simple Timer interrupts - - simple_timer #(.BASE(SR_SIMTIMER)) simple_timer - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .onetime_int(onetime_int), .periodic_int(periodic_int)); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - // No longer used, see time_64bit. Still need to handle mimo time, though - assign sc_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // ICAP for reprogramming the FPGA, Slave #13 (D) - - s3a_icap_wb s3a_icap_wb - (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), - .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI for Flash -- Slave #14 (E) - spi_top flash_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), - .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), - .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), - .ss_pad_o(spiflash_cs), - .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 0 - wire [31:0] sample_rx0; - wire clear_rx0, strobe_rx0; - - always @(posedge dsp_clk) - run_rx0_d1 <= run_rx0; - - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), - .debug() ); - - setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx0)); - - vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), - .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), - .debug() ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 1 - wire [31:0] sample_rx1; - wire clear_rx1, strobe_rx1; - - always @(posedge dsp_clk) - run_rx1_d1 <= run_rx1; - - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), - .debug() ); - - setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx1)); - - vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun1), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), - .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), - .debug() ); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire tx_src_rdy, tx_dst_rdy; - wire [31:0] debug_vt; - wire clear_tx; - - setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - assign RAM_A[20:18] = 3'b0; - - ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) - ext_fifo_i1 - (.int_clk(dsp_clk), - .ext_clk(dsp_clk), - .rst(dsp_rst | clear_tx), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A[17:0]), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain(rd1_dat), - .src_rdy_i(rd1_ready_o), - .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), - .src_rdy_o(tx_src_rdy), - .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo), - .debug2(debug_extfifo2) ); - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(dac_a),.dac_b(dac_b), - .underrun(underrun), .run(run_tx), - .debug(debug_vt)); - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - wire [31:0] debug_sync; - - time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), - .debug(debug_sync)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; - assign debug_gpio_0 = 32'd0; - assign debug_gpio_1 = 32'd0; - -endmodule // u2_core |