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-rw-r--r--fpga/usrp2/top/u2_rev3_iad/Makefile1
1 files changed, 0 insertions, 1 deletions
diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile
index 5ae8846dd..15df9e43e 100644
--- a/fpga/usrp2/top/u2_rev3_iad/Makefile
+++ b/fpga/usrp2/top/u2_rev3_iad/Makefile
@@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \