4 files changed, 0 insertions, 123 deletions
diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/u1e_passthru/.gitignore
deleted file mode 100644
index 1b2211df0..000000000
--- a/fpga/usrp2/top/u1e_passthru/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build*
diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile
deleted file mode 100644
index f2d835608..000000000
--- a/fpga/usrp2/top/u1e_passthru/Makefile
+++ /dev/null
@@ -1,98 +0,0 @@
-#
-# Copyright 2008 Ettus Research LLC
-#
-
-##################################################
-# Project Setup
-##################################################
-TOP_MODULE = passthru
-BUILD_DIR = $(abspath build$(ISE))
-
-##################################################
-# Include other makefiles
-##################################################
-
-include ../Makefile.common
-include ../../fifo/Makefile.srcs
-include ../../control_lib/Makefile.srcs
-include ../../sdr_lib/Makefile.srcs
-include ../../serdes/Makefile.srcs
-include ../../simple_gemac/Makefile.srcs
-include ../../timing/Makefile.srcs
-include ../../opencores/Makefile.srcs
-include ../../vrt/Makefile.srcs
-include ../../udp/Makefile.srcs
-include ../../coregen/Makefile.srcs
-include ../../gpmc/Makefile.srcs
-
-##################################################
-# Project Properties
-##################################################
-export PROJECT_PROPERTIES := \
-family "Spartan-3A DSP" \
-device xc3sd1800a \
-package cs484 \
-speed -4 \
-top_level_module_type "HDL" \
-synthesis_tool "XST (VHDL/Verilog)" \
-simulator "ISE Simulator (VHDL/Verilog)" \
-"Preferred Language" "Verilog" \
-"Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE 
-
-##################################################
-# Sources
-##################################################
-TOP_SRCS = \
-passthru.v \
-passthru.ucf
-
-SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
-$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
-$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \
-$(GPMC_SRCS)
-
-##################################################
-# Process Properties
-##################################################
-SYNTHESIZE_PROPERTIES = \
-"Number of Clock Buffers" 8 \
-"Pack I/O Registers into IOBs" Yes \
-"Optimization Effort" High \
-"Optimize Instantiated Primitives" TRUE \
-"Register Balancing" Yes \
-"Use Clock Enable" Auto \
-"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
-
-TRANSLATE_PROPERTIES = \
-"Macro Search Path" "$(shell pwd)/../../coregen/"
-
-MAP_PROPERTIES = \
-"Allow Logic Optimization Across Hierarchy" TRUE \
-"Map to Input Functions" 4 \
-"Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
-"Perform Timing-Driven Packing and Placement" TRUE \
-"Map Effort Level" High \
-"Extra Effort" Normal \
-"Combinatorial Logic Optimization" TRUE \
-"Register Duplication" TRUE
-
-PLACE_ROUTE_PROPERTIES = \
-"Place & Route Effort Level (Overall)" High 
-
-STATIC_TIMING_PROPERTIES = \
-"Number of Paths in Error/Verbose Report" 10 \
-"Report Type" "Error Report"
-
-GEN_PROG_FILE_PROPERTIES = \
-"Configuration Rate" 6 \
-"Create Binary Configuration File" TRUE \
-"Done (Output Events)" 5 \
-"Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6 \
-"Unused IOB Pins" "Pull Up"
-
-SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/u1e_passthru/passthru.ucf
deleted file mode 100644
index 64e6f0440..000000000
--- a/fpga/usrp2/top/u1e_passthru/passthru.ucf
+++ /dev/null
@@ -1,6 +0,0 @@
-NET "overo_gpio145"  LOC = "C7"  ;
-NET "cgen_mosi"  LOC = "E22"  ;
-NET "cgen_sclk"  LOC = "J19"  ;
-NET "cgen_sen_b"  LOC = "H20"  ;
-NET "fpga_cfg_din"  LOC = "W17"  ;
-NET "fpga_cfg_cclk"  LOC = "V17"  ;
diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v
deleted file mode 100644
index 12e4db017..000000000
--- a/fpga/usrp2/top/u1e_passthru/passthru.v
+++ /dev/null
@@ -1,18 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module passthru
-  (input overo_gpio145,
-   output cgen_sclk,
-   output cgen_sen_b,
-   output cgen_mosi,
-   input fpga_cfg_din,
-   input fpga_cfg_cclk
-   );
-   
-   assign cgen_sclk = fpga_cfg_cclk;
-   assign cgen_sen_b = overo_gpio145;
-   assign cgen_mosi = fpga_cfg_din;
-   
-   
-endmodule // passthru