diff options
Diffstat (limited to 'fpga/usrp2/top/safe_u2plus')
| -rw-r--r-- | fpga/usrp2/top/safe_u2plus/.gitignore | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/safe_u2plus/Makefile | 245 | ||||
| -rw-r--r-- | fpga/usrp2/top/safe_u2plus/safe_u2plus.v | 23 | ||||
| -rwxr-xr-x | fpga/usrp2/top/safe_u2plus/u2plus.ucf | 401 |
4 files changed, 671 insertions, 0 deletions
diff --git a/fpga/usrp2/top/safe_u2plus/.gitignore b/fpga/usrp2/top/safe_u2plus/.gitignore new file mode 100644 index 000000000..a96f0be92 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/.gitignore @@ -0,0 +1,2 @@ +build* +*impact* diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile new file mode 100644 index 000000000..b72241050 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/Makefile @@ -0,0 +1,245 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u2plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2plus/capture_ddrlvds.v \ +top/safe_u2plus/u2plus.ucf \ +top/safe_u2plus/safe_u2plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v new file mode 100644 index 000000000..dca9688c5 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v @@ -0,0 +1,23 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [5:1] leds, // LED4 is shared w/INIT_B + output ETH_LED + ); + + wire clk_fpga; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + +endmodule // safe_u2plus diff --git a/fpga/usrp2/top/safe_u2plus/u2plus.ucf b/fpga/usrp2/top/safe_u2plus/u2plus.ucf new file mode 100755 index 000000000..0a9460d86 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/u2plus.ucf @@ -0,0 +1,401 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +#NET "ADC_clkout_p" LOC = "P1" ; +#NET "ADC_clkout_n" LOC = "P2" ; +#NET "ADCA_12_p" LOC = "Y1" ; +#NET "ADCA_12_n" LOC = "Y2" ; +#NET "ADCA_10_p" LOC = "W3" ; +#NET "ADCA_10_n" LOC = "W4" ; +#NET "ADCA_8_p" LOC = "T7" ; +#NET "ADCA_8_n" LOC = "U6" ; +#NET "ADCA_6_p" LOC = "U5" ; +#NET "ADCA_6_n" LOC = "V5" ; +#NET "ADCA_4_p" LOC = "T10" ; +#NET "ADCA_4_n" LOC = "T9" ; +#NET "ADCA_2_p" LOC = "V1" ; +#NET "ADCA_2_n" LOC = "V2" ; +#NET "ADCA_0_p" LOC = "R8" ; +#NET "ADCA_0_n" LOC = "R7" ; +#NET "ADCB_2_p" LOC = "U7" ; +#NET "ADCB_2_n" LOC = "U8" ; +#NET "ADCB_0_p" LOC = "AA2" ; +#NET "ADCB_0_n" LOC = "AA3" ; +#NET "ADCB_4_p" LOC = "AE1" ; +#NET "ADCB_4_n" LOC = "AE2" ; +#NET "ADCB_6_p" LOC = "W1" ; +#NET "ADCB_6_n" LOC = "W2" ; +#NET "ADCB_8_p" LOC = "U3" ; +#NET "ADCB_8_n" LOC = "V4" ; +#NET "ADCB_10_p" LOC = "J1" ; +#NET "ADCB_10_n" LOC = "K1" ; +#NET "ADCB_12_p" LOC = "J3" ; +#NET "ADCB_12_n" LOC = "J2" ; + +## DAC +#NET "DAC_LOCK" LOC = "P4" ; +#NET "DACA<0>" LOC = "P8" ; +#NET "DACA<1>" LOC = "P9" ; +#NET "DACA<2>" LOC = "R5" ; +#NET "DACA<3>" LOC = "R6" ; +#NET "DACA<4>" LOC = "P7" ; +#NET "DACA<5>" LOC = "P6" ; +#NET "DACA<6>" LOC = "T3" ; +#NET "DACA<7>" LOC = "T4" ; +#NET "DACA<8>" LOC = "R3" ; +#NET "DACA<9>" LOC = "R4" ; +#NET "DACA<10>" LOC = "R2" ; +#NET "DACA<11>" LOC = "N1" ; +#NET "DACA<12>" LOC = "N2" ; +#NET "DACA<13>" LOC = "N5" ; +#NET "DACA<14>" LOC = "N4" ; +#NET "DACA<15>" LOC = "M2" ; +#NET "DACB<0>" LOC = "M5" ; +#NET "DACB<1>" LOC = "M6" ; +#NET "DACB<2>" LOC = "M4" ; +#NET "DACB<3>" LOC = "M3" ; +#NET "DACB<4>" LOC = "M8" ; +#NET "DACB<5>" LOC = "M7" ; +#NET "DACB<6>" LOC = "L4" ; +#NET "DACB<7>" LOC = "L3" ; +#NET "DACB<8>" LOC = "K3" ; +#NET "DACB<9>" LOC = "K2" ; +#NET "DACB<10>" LOC = "K5" ; +#NET "DACB<11>" LOC = "K4" ; +#NET "DACB<12>" LOC = "M10" ; +#NET "DACB<13>" LOC = "M9" ; +#NET "DACB<14>" LOC = "J5" ; +#NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +#NET "io_tx<15>" LOC = "K6" ; +#NET "io_tx<14>" LOC = "L7" ; +#NET "io_tx<13>" LOC = "H2" ; +#NET "io_tx<12>" LOC = "H1" ; +#NET "io_tx<11>" LOC = "L10" ; +#NET "io_tx<10>" LOC = "L9" ; +#NET "io_tx<9>" LOC = "G3" ; +#NET "io_tx<8>" LOC = "F3" ; +#NET "io_tx<7>" LOC = "K7" ; +#NET "io_tx<6>" LOC = "J6" ; +#NET "io_tx<5>" LOC = "E1" ; +#NET "io_tx<4>" LOC = "F2" ; +#NET "io_tx<3>" LOC = "J7" ; +#NET "io_tx<2>" LOC = "H6" ; +#NET "io_tx<1>" LOC = "F5" ; +#NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +#NET "io_rx<15>" LOC = "AD1" ; +#NET "io_rx<14>" LOC = "AD2" ; +#NET "io_rx<13>" LOC = "AC2" ; +#NET "io_rx<12>" LOC = "AC3" ; +#NET "io_rx<11>" LOC = "W7" ; +#NET "io_rx<10>" LOC = "W6" ; +#NET "io_rx<9>" LOC = "U9" ; +#NET "io_rx<8>" LOC = "V8" ; +#NET "io_rx<7>" LOC = "AB1" ; +#NET "io_rx<6>" LOC = "AC1" ; +#NET "io_rx<5>" LOC = "V7" ; +#NET "io_rx<4>" LOC = "V6" ; +#NET "io_rx<3>" LOC = "Y5" ; +#NET "io_rx<2>" LOC = "R10" ; +#NET "io_rx<1>" LOC = "R1" ; +#NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +#NET "FPGA_RESET" LOC = "K24" ; + +## Debug +#NET "debug_clk<0>" LOC = "AA10" ; +#NET "debug_clk<1>" LOC = "AD11" ; +#NET "debug<0>" LOC = "AC19" ; +#NET "debug<1>" LOC = "AF20" ; +#NET "debug<2>" LOC = "AE20" ; +#NET "debug<3>" LOC = "AC16" ; +#NET "debug<4>" LOC = "AB16" ; +#NET "debug<5>" LOC = "AF19" ; +#NET "debug<6>" LOC = "AE19" ; +#NET "debug<7>" LOC = "V15" ; +#NET "debug<8>" LOC = "U15" ; +#NET "debug<9>" LOC = "AE17" ; +#NET "debug<10>" LOC = "AD17" ; +#NET "debug<11>" LOC = "V14" ; +#NET "debug<12>" LOC = "W15" ; +#NET "debug<13>" LOC = "AC15" ; +#NET "debug<14>" LOC = "AD14" ; +#NET "debug<15>" LOC = "AC14" ; +#NET "debug<16>" LOC = "AC11" ; +#NET "debug<17>" LOC = "AB12" ; +#NET "debug<18>" LOC = "AC12" ; +#NET "debug<19>" LOC = "V13" ; +#NET "debug<20>" LOC = "W13" ; +#NET "debug<21>" LOC = "AE8" ; +#NET "debug<22>" LOC = "AF8" ; +#NET "debug<23>" LOC = "V12" ; +#NET "debug<24>" LOC = "W12" ; +#NET "debug<25>" LOC = "AB9" ; +#NET "debug<26>" LOC = "AC9" ; +#NET "debug<27>" LOC = "AC8" ; +#NET "debug<28>" LOC = "AB7" ; +#NET "debug<29>" LOC = "V11" ; +#NET "debug<30>" LOC = "U11" ; +#NET "debug<31>" LOC = "Y10" ; + +## UARTS +#NET "TXD<3>" LOC = "AD20" ; +#NET "TXD<2>" LOC = "AC20" ; +#NET "TXD<1>" LOC = "AD19" ; +#NET "RXD<3>" LOC = "AF17" ; +#NET "RXD<2>" LOC = "AF15" ; +#NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +#NET "CLK_STATUS" LOC = "AD22" ; +#NET "CLK_FUNC" LOC = "AC21" ; +#NET "clk_sel<0>" LOC = "AE21" ; +#NET "clk_sel<1>" LOC = "AD21" ; +#NET "clk_en<1>" LOC = "AA17" ; +#NET "clk_en<0>" LOC = "Y17" ; + +## I2C +#NET "SDA" LOC = "V16" ; +#NET "SCL" LOC = "U16" ; + +## Timing +#NET "PPS_IN" LOC = "AB6" ; +#NET "PPS2_IN" LOC = "AA20" ; + +## SPI +#NET "SEN_CLK" LOC = "AA18" ; +#NET "MOSI_CLK" LOC = "W17" ; +#NET "SCLK_CLK" LOC = "V17" ; +#NET "MISO_CLK" LOC = "AC10" ; + +#NET "SEN_DAC" LOC = "AE7" ; +#NET "SCLK_DAC" LOC = "AF5" ; +#NET "MOSI_DAC" LOC = "AE6" ; +#NET "MISO_DAC" LOC = "Y3" ; + +#NET "SCLK_ADC" LOC = "B1" ; +#NET "MOSI_ADC" LOC = "J8" ; +#NET "SEN_ADC" LOC = "J9" ; + +#NET "MOSI_TX_ADC" LOC = "V10" ; +#NET "SEN_TX_ADC" LOC = "W10" ; +#NET "SCLK_TX_ADC" LOC = "AC6" ; +#NET "MISO_TX_ADC" LOC = "G1" ; + +#NET "MOSI_TX_DAC" LOC = "AD6" ; +#NET "SEN_TX_DAC" LOC = "AE4" ; +#NET "SCLK_TX_DAC" LOC = "AF4" ; + +#NET "SCLK_TX_DB" LOC = "AE3" ; +#NET "MOSI_TX_DB" LOC = "AF3" ; +#NET "SEN_TX_DB" LOC = "W9" ; +#NET "MISO_TX_DB" LOC = "AA5" ; + +#NET "MOSI_RX_ADC" LOC = "E3" ; +#NET "SCLK_RX_ADC" LOC = "F4" ; +#NET "SEN_RX_ADC" LOC = "D3" ; +#NET "MISO_RX_ADC" LOC = "C1" ; + +#NET "SCLK_RX_DAC" LOC = "E4" ; +#NET "SEN_RX_DAC" LOC = "K9" ; +#NET "MOSI_RX_DAC" LOC = "K8" ; + +#NET "SCLK_RX_DB" LOC = "G6" ; +#NET "MOSI_RX_DB" LOC = "H7" ; +#NET "SEN_RX_DB" LOC = "B2" ; +#NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +#NET "CLK_TO_MAC" LOC = "P26" ; + +#NET "GMII_TXD<7>" LOC = "G21" ; +#NET "GMII_TXD<6>" LOC = "C26" ; +#NET "GMII_TXD<5>" LOC = "C25" ; +#NET "GMII_TXD<4>" LOC = "J21" ; +#NET "GMII_TXD<3>" LOC = "H21" ; +#NET "GMII_TXD<2>" LOC = "D25" ; +#NET "GMII_TXD<1>" LOC = "D24" ; +#NET "GMII_TXD<0>" LOC = "E26" ; +#NET "GMII_TX_EN" LOC = "D26" ; +#NET "GMII_TX_ER" LOC = "J19" ; +#NET "GMII_GTX_CLK" LOC = "J20" ; +#NET "GMII_TX_CLK" LOC = "P25" ; + +#NET "GMII_RX_CLK" LOC = "P21" ; +#NET "GMII_RXD<7>" LOC = "G22" ; +#NET "GMII_RXD<6>" LOC = "K19" ; +#NET "GMII_RXD<5>" LOC = "K18" ; +#NET "GMII_RXD<4>" LOC = "E24" ; +#NET "GMII_RXD<3>" LOC = "F23" ; +#NET "GMII_RXD<2>" LOC = "L18" ; +#NET "GMII_RXD<1>" LOC = "L17" ; +#NET "GMII_RXD<0>" LOC = "F25" ; +#NET "GMII_RX_DV" LOC = "F24" ; +#NET "GMII_RX_ER" LOC = "L20" ; +#NET "GMII_CRS" LOC = "K20" ; +#NET "GMII_COL" LOC = "G23" ; + +#NET "PHY_INTn" LOC = "L22" ; +#NET "MDIO" LOC = "K21" ; +#NET "MDC" LOC = "J23" ; +#NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" ; + +## MIMO Interface +#NET "exp_time_out_p" LOC = "Y14" ; +#NET "exp_time_out_n" LOC = "AA14" ; +#NET "exp_time_in_p" LOC = "N18" ; +#NET "exp_time_in_n" LOC = "N17" ; +#NET "exp_user_out_p" LOC = "AF14" ; +#NET "exp_user_out_n" LOC = "AE14" ; +#NET "exp_user_in_p" LOC = "L24" ; +#NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +#NET "ser_enable" LOC = "R20" ; +#NET "ser_prbsen" LOC = "U23" ; +#NET "ser_loopen" LOC = "R19" ; +#NET "ser_rx_en" LOC = "Y21" ; +#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +#NET "ser_t<15>" LOC = "V23" ; +#NET "ser_t<14>" LOC = "U22" ; +#NET "ser_t<13>" LOC = "V24" ; +#NET "ser_t<12>" LOC = "V25" ; +#NET "ser_t<11>" LOC = "W23" ; +#NET "ser_t<10>" LOC = "V22" ; +#NET "ser_t<9>" LOC = "T18" ; +#NET "ser_t<8>" LOC = "T17" ; +#NET "ser_t<7>" LOC = "Y24" ; +#NET "ser_t<6>" LOC = "Y25" ; +#NET "ser_t<5>" LOC = "U21" ; +#NET "ser_t<4>" LOC = "T20" ; +#NET "ser_t<3>" LOC = "Y22" ; +#NET "ser_t<2>" LOC = "Y23" ; +#NET "ser_t<1>" LOC = "U19" ; +#NET "ser_t<0>" LOC = "U18" ; +#NET "ser_tkmsb" LOC = "AA24" ; +#NET "ser_tklsb" LOC = "AA25" ; +#NET "ser_rx_clk" LOC = "P18" ; +#NET "ser_r<15>" LOC = "V21" ; +#NET "ser_r<14>" LOC = "U20" ; +#NET "ser_r<13>" LOC = "AA22" ; +#NET "ser_r<12>" LOC = "AA23" ; +#NET "ser_r<11>" LOC = "V18" ; +#NET "ser_r<10>" LOC = "V19" ; +#NET "ser_r<9>" LOC = "AB23" ; +#NET "ser_r<8>" LOC = "AC26" ; +#NET "ser_r<7>" LOC = "AB26" ; +#NET "ser_r<6>" LOC = "AD26" ; +#NET "ser_r<5>" LOC = "AC25" ; +#NET "ser_r<4>" LOC = "W20" ; +#NET "ser_r<3>" LOC = "W21" ; +#NET "ser_r<2>" LOC = "AC23" ; +#NET "ser_r<1>" LOC = "AC24" ; +#NET "ser_r<0>" LOC = "AE26" ; +#NET "ser_rkmsb" LOC = "AD25" ; +#NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +#NET "RAM_D<35>" LOC = "K16" ; +#NET "RAM_D<34>" LOC = "D20" ; +#NET "RAM_D<33>" LOC = "C20" ; +#NET "RAM_D<32>" LOC = "E21" ; +#NET "RAM_D<31>" LOC = "D21" ; +#NET "RAM_D<30>" LOC = "C21" ; +#NET "RAM_D<29>" LOC = "B21" ; +#NET "RAM_D<28>" LOC = "H17" ; +#NET "RAM_D<27>" LOC = "G17" ; +#NET "RAM_D<26>" LOC = "B23" ; +#NET "RAM_D<25>" LOC = "A22" ; +#NET "RAM_D<24>" LOC = "D23" ; +#NET "RAM_D<23>" LOC = "C23" ; +#NET "RAM_D<22>" LOC = "D22" ; +#NET "RAM_D<21>" LOC = "C22" ; +#NET "RAM_D<20>" LOC = "F19" ; +#NET "RAM_D<19>" LOC = "G20" ; +#NET "RAM_D<18>" LOC = "F20" ; +#NET "RAM_D<17>" LOC = "F7" ; +#NET "RAM_D<16>" LOC = "E7" ; +#NET "RAM_D<15>" LOC = "G9" ; +#NET "RAM_D<14>" LOC = "H9" ; +#NET "RAM_D<13>" LOC = "G10" ; +#NET "RAM_D<12>" LOC = "H10" ; +#NET "RAM_D<11>" LOC = "A4" ; +#NET "RAM_D<10>" LOC = "B4" ; +#NET "RAM_D<9>" LOC = "C5" ; +#NET "RAM_D<8>" LOC = "D6" ; +#NET "RAM_D<7>" LOC = "J11" ; +#NET "RAM_D<6>" LOC = "K11" ; +#NET "RAM_D<5>" LOC = "B7" ; +#NET "RAM_D<4>" LOC = "C7" ; +#NET "RAM_D<3>" LOC = "B6" ; +#NET "RAM_D<2>" LOC = "C6" ; +#NET "RAM_D<1>" LOC = "C8" ; +#NET "RAM_D<0>" LOC = "D8" ; +#NET "RAM_A<0>" LOC = "C11" ; +#NET "RAM_A<1>" LOC = "E12" ; +#NET "RAM_A<2>" LOC = "F12" ; +#NET "RAM_A<3>" LOC = "D13" ; +#NET "RAM_A<4>" LOC = "C12" ; +#NET "RAM_A<5>" LOC = "A12" ; +#NET "RAM_A<6>" LOC = "B12" ; +#NET "RAM_A<7>" LOC = "E14" ; +#NET "RAM_A<8>" LOC = "F14" ; +#NET "RAM_A<9>" LOC = "B15" ; +#NET "RAM_A<10>" LOC = "A15" ; +#NET "RAM_A<11>" LOC = "D16" ; +#NET "RAM_A<12>" LOC = "C15" ; +#NET "RAM_A<13>" LOC = "D17" ; +#NET "RAM_A<14>" LOC = "C16" ; +#NET "RAM_A<15>" LOC = "F15" ; +#NET "RAM_A<16>" LOC = "C17" ; +#NET "RAM_A<17>" LOC = "B17" ; +#NET "RAM_A<18>" LOC = "B18" ; +#NET "RAM_A<19>" LOC = "A18" ; +#NET "RAM_A<20>" LOC = "D18" ; +#NET "RAM_BWn<3>" LOC = "D9" ; +#NET "RAM_BWn<2>" LOC = "A9" ; +#NET "RAM_BWn<1>" LOC = "B9" ; +#NET "RAM_BWn<0>" LOC = "G12" ; +#NET "RAM_ZZ" LOC = "J12" ; +#NET "RAM_LDn" LOC = "H12" ; +#NET "RAM_OEn" LOC = "C10" ; +#NET "RAM_WEn" LOC = "D10" ; +#NET "RAM_CENn" LOC = "B10" ; +#NET "RAM_CLK" LOC = "A10" ; + +## SPI Flash +#NET "flash_miso" LOC = "AF24" ; +#NET "flash_clk" LOC = "AE24" ; +#NET "flash_mosi" LOC = "AB15" ; +#NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +##NET "PROG_B" LOC = "A2" ; +##NET "PUDC_B" LOC = "G8" ; +##NET "DONE" LOC = "AB21" ; +##NET "INIT_B" LOC = "AA15" ; + + +##NET "unnamed_net19" LOC = "AE9" ; # VS1 +##NET "unnamed_net18" LOC = "AF9" ; # VS0 +##NET "unnamed_net17" LOC = "AA12" ; # VS2 +##NET "unnamed_net16" LOC = "Y7" ; # M2 +##NET "unnamed_net15" LOC = "AC4" ; # M1 +##NET "unnamed_net14" LOC = "AD4" ; # M0 +##NET "unnamed_net13" LOC = "D4" ; # TMS +##NET "unnamed_net12" LOC = "E23" ; # TDO +##NET "unnamed_net11" LOC = "G7" ; # TDI +##NET "unnamed_net10" LOC = "A25" ; # TCK +##NET "unnamed_net20" LOC = "V20" ; # SUSPEND |