diff options
Diffstat (limited to 'fpga/usrp2/top/USRP2')
| -rw-r--r-- | fpga/usrp2/top/USRP2/u2_core.v | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index 2e3d41731..ee1116eac 100644 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -193,7 +193,6 @@ module u2_core wire uart_tx_int, uart_rx_int; wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; @@ -202,7 +201,7 @@ module u2_core wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - wire serdes_link_up; + wire serdes_link_up, good_sync; wire epoch; wire [31:0] irq; wire [63:0] vita_time, vita_time_pps; @@ -423,17 +422,17 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[4:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio({io_tx,io_rx}) ); + .rx(run_rx0_d1 | rx_rx1_d1), .tx(run_tx), .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd7, 16'd0}; //major, minor + localparam compat_num = {16'd7, 16'd1}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -441,7 +440,7 @@ module u2_core .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word08(status),.word09(32'b0),.word10(vita_time[63:32]), .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) ); @@ -502,7 +501,7 @@ module u2_core // In Rev3 there are only 6 leds, and the highest one is on the ETH connector wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up & good_sync, 1'b0}; setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); @@ -524,7 +523,7 @@ module u2_core assign irq= {{8'b0}, {8'b0}, - {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {2'b0, good_sync, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), @@ -539,12 +538,12 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Simple Timer interrupts - + /* simple_timer #(.BASE(SR_SIMTIMER)) simple_timer (.clk(wb_clk), .reset(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .onetime_int(onetime_int), .periodic_int(periodic_int)); - + */ // ///////////////////////////////////////////////////////////////////////// // UART, Slave #10 @@ -558,11 +557,13 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // ATR Controller, Slave #11 + /* atr_controller atr_controller (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + */ // ////////////////////////////////////////////////////////////////////////// // Time Sync, Slave #12 @@ -572,16 +573,16 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // SD Card Reader / Writer, Slave #13 - + /* sd_spi_wb sd_spi_wb (.clk(wb_clk),.rst(wb_rst), .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), .wb_ack_o(sd_ack) ); - + assign sd_dat_i[31:8] = 0; - + */ // ///////////////////////////////////////////////////////////////////////// // ADC Frontend wire [23:0] adc_i, adc_q; @@ -729,8 +730,7 @@ module u2_core time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), - .debug(debug_sync)); + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync)); // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins |