11 files changed, 2678 insertions, 0 deletions

diff --git a/fpga/usrp2/top/N2x0/.gitignore b/fpga/usrp2/top/N2x0/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/fpga/usrp2/top/N2x0/Makefile b/fpga/usrp2/top/N2x0/Makefile
new file mode 100644
index 000000000..b6a3d9624
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/Makefile
@@ -0,0 +1,23 @@
+#
+# Copyright 2011 Ettus Research LLC
+#
+
+all: N200R3 N210R3 N200R4 N210R4
+	find -name "*.twr" | xargs grep constraint | grep met
+
+clean:
+	rm -rf build*
+
+N200R3:
+	make -f Makefile.$@ bin
+
+N210R3:
+	make -f Makefile.$@ bin
+
+N200R4:
+	make -f Makefile.$@ bin
+
+N210R4:
+	make -f Makefile.$@ bin
+
+.PHONY: all clean
diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R3 b/fpga/usrp2/top/N2x0/Makefile.N200R3
new file mode 100644
index 000000000..07b955d13
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/Makefile.N200R3
@@ -0,0 +1,104 @@
+#
+# Copyright 2008-2012 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2plus
+BUILD_DIR = $(abspath build$(ISE)-N200R3)
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u2plus_core.v \
+u2plus.v \
+u2plus.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R4 b/fpga/usrp2/top/N2x0/Makefile.N200R4
new file mode 100644
index 000000000..8b1090308
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/Makefile.N200R4
@@ -0,0 +1,105 @@
+#
+# Copyright 2008-2012 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2plus
+BUILD_DIR = $(abspath build$(ISE)-N200R4)
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+capture_ddrlvds.v \
+u2plus_core.v \
+u2plus.v \
+u2plus.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto \
+"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)"
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R3 b/fpga/usrp2/top/N2x0/Makefile.N210R3
new file mode 100644
index 000000000..411aa20f1
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/Makefile.N210R3
@@ -0,0 +1,104 @@
+#
+# Copyright 2008-2012 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2plus
+BUILD_DIR = $(abspath build$(ISE)-N210R3)
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u2plus_core.v \
+u2plus.v \
+u2plus.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R4 b/fpga/usrp2/top/N2x0/Makefile.N210R4
new file mode 100644
index 000000000..44ce17b3f
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/Makefile.N210R4
@@ -0,0 +1,105 @@
+#
+# Copyright 2008-2012 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2plus
+BUILD_DIR = $(abspath build$(ISE)-N210R4)
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+capture_ddrlvds.v \
+u2plus_core.v \
+u2plus.v \
+u2plus.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto \
+"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)"
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/N2x0/bootloader.rmi b/fpga/usrp2/top/N2x0/bootloader.rmi
new file mode 100644
index 000000000..60706081c
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/bootloader.rmi
@@ -0,0 +1,512 @@
+defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d7e40400_3a0b0b80_80e49c0c_82700b0b_0b0b0b0b;
+defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d8ae2d_88080b0b_80088408;
+defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608;
+defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608;
+defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105;
+defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473;
+defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109;
+defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673;
+defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88;
+defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b;
+defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06;
+defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff;
+defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351;
+defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105;
+defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105;
+defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105;
+defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981;
+defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206;
+defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608;
+defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_88738306_0b0b80e4_71fc0608;
+defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_852d5050_0b0b80cf_88087575_80088408;
+defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_b72d5050_0b0b80d0_88087575_80088408;
+defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081;
+defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081;
+defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504;
+defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e4980c_810b0b0b;
+defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552;
+defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572;
+defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff;
+defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d0ab3f04_82813f80;
+defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010;
+defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04;
+defparam bootram.RAM0.INIT_23=256'h800b80e4_f40c82a0_0b0b80e4_8380800b_822ebd38_80e49c08_802ea438_80e49808;
+defparam bootram.RAM0.INIT_24=256'h0b80e4f8_80808280_e4f40cf8_0b0b0b80_808080a4_fc0c04f8_800b80e4_f80c8290;
+defparam bootram.RAM0.INIT_25=256'h940b80e4_80c0a880_80e4f40c_8c0b0b0b_80c0a880_e4fc0c04_84800b80_0cf88080;
+defparam bootram.RAM0.INIT_26=256'h70085252_80e4a408_5170a738_80e58033_04ff3d0d_80e4fc0c_80d8e00b_f80c0b0b;
+defparam bootram.RAM0.INIT_27=256'h8034833d_810b80e5_5270ee38_08700852_2d80e4a4_e4a40c70_38841280_70802e94;
+defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e4f008_3d0d0b0b_0d040480;
+defparam bootram.RAM0.INIT_29=256'h3d225a79_80c13895_0d685b7a_0404ee3d_3f823d0d_0b0bf5d4_e4f0510b_040b0b80;
+defparam bootram.RAM0.INIT_2A=256'h8d3881d2_8380862e_81dc3979_842e8e38_38798380_8085248b_ae387983_8380852e;
+defparam bootram.RAM0.INIT_2B=256'h0b983d22_81b83980_81e4d00c_81c0397a_81e2cc0c_c939810b_e18c0c81_39810b81;
+defparam bootram.RAM0.INIT_2C=256'h80862e8b_99397983_2e9f3881_79838084_85248b38_38798380_80852ea7_5b5b7983;
+defparam bootram.RAM0.INIT_2D=256'h055241a9_53963d84_5b923d70_5b833983_5b873981_81883982_872e8c38_38798380;
+defparam bootram.RAM0.INIT_2E=256'h5b79337b_1d7f1d5b_415e5c7b_883d993d_5f40800b_84057c5b_3f800802_953f8a8b;
+defparam bootram.RAM0.INIT_2F=256'h1c5c887c_337b3481_055b5b79_1d963d7d_1f5e5c7b_38800b90_887c26ef_34811c5c;
+defparam bootram.RAM0.INIT_30=256'h5c7b1e61_26ef3880_1c5c867c_337b3481_1d5b5b79_5c7b1d60_0b881f5e_26ed3880;
+defparam bootram.RAM0.INIT_31=256'h1208595a_0d686a84_0d04ee3d_8b3f943d_26ef389a_1c5c867c_337b3481_1d5b5b79;
+defparam bootram.RAM0.INIT_32=256'h833f80e1_d8e45195_538c5280_2e8c3875_94387580_56758c2e_9c387708_58837927;
+defparam bootram.RAM0.INIT_33=256'h9f175675_18085dff_5ba05c88_3fa0578c_b45194f0_a45280d9_8e387853_5778a326;
+defparam bootram.RAM0.INIT_34=256'h39951833_085e81eb_993f8008_80c15c89_56750804_80dba405_38758429_92268281;
+defparam bootram.RAM0.INIT_35=256'h19335757_52800b97_538c1808_54901808_55961833_38845776_80f22e83_56825775;
+defparam bootram.RAM0.INIT_36=256'hea05538c_7054953d_398d1833_d35c81b3_80085f80_5196ab3f_38815776_75772e83;
+defparam bootram.RAM0.INIT_37=256'h80c85c75_568de63f_8c193352_548e1953_8d183370_c95c9439_8cd93f80_19335256;
+defparam bootram.RAM0.INIT_38=256'h8c190858_80dbf005_38758429_852680c2_ff055675_39941833_053480ff_028405b5;
+defparam bootram.RAM0.INIT_39=256'h76842980_77239b39_39921822_08770ca2_a9399018_3976225f_76085fae_56750804;
+defparam bootram.RAM0.INIT_3A=256'h5e80cc5c_5cad3978_0c5680d2_90190871_80e58405_39768429_0840568e_e5840570;
+defparam bootram.RAM0.INIT_3B=256'h18588878_33773481_05575775_19963d79_3d5a5877_54800b83_943ddc05_8c180855;
+defparam bootram.RAM0.INIT_3C=256'h75337734_79055757_7719963d_833d5a58_0554800b_55943ddc_39a05ca4_26ed38a4;
+defparam bootram.RAM0.INIT_3D=256'h525392a0_5380da80_3d0d7470_3d0d04fe_9ba73f94_83808051_7826ed38_81185888;
+defparam bootram.RAM0.INIT_3E=256'hcd3f7251_52725187_3f8d39a0_d23f9bba_3f81518f_a05187de_9238a052_3f72802e;
+defparam bootram.RAM0.INIT_3F=256'h3f8c5280_bc5191e4_8a5280da_5188c13f_3f80daa0_3d0d8297_3d0d04fa_8fc13f84;
+defparam bootram.RAM1.INIT_00=256'h963f87db_80085190_3f85b83f_a43f868b_a9c33f85_80e5a00c_db3f820b_dadc5191;
+defparam bootram.RAM1.INIT_01=256'hd23f85ee_80085194_9a3f7352_80085485_3f85ff3f_b03f87cf_80085190_3f868b3f;
+defparam bootram.RAM1.INIT_02=256'h80845195_8ab25283_5195983f_52838080_dc3f8cb6_8ea13f94_52800851_3f838085;
+defparam bootram.RAM1.INIT_03=256'h5194f03f_52838087_fa3f8ab2_80855194_8ab25283_5195843f_52838086_8e3f8ab2;
+defparam bootram.RAM1.INIT_04=256'h3fabfb3f_b351a9e9_8e8d3f8f_963f8051_809251a5_94e53f83_83808251_80c08952;
+defparam bootram.RAM1.INIT_05=256'hfdee2e09_55557382_088e0522_c9387680_08802e80_80085680_518e843f_883dfc05;
+defparam bootram.RAM1.INIT_06=256'h833f9416_db885190_089a3880_c4cb3f80_90055180_80528008_845380db_8106ad38;
+defparam bootram.RAM1.INIT_07=256'h3f8bfb3f_893fa4e9_9a9d3f8d_74527551_8e3f8839_3f735185_f43f8693_7052548e;
+defparam bootram.RAM1.INIT_08=256'h85a93f9f_9f528051_3f88803f_843f8bb0_82b73f87_3f91cb3f_3d0d85dc_ff9e39fe;
+defparam bootram.RAM1.INIT_09=256'h5184eb3f_3f885288_ac518ae2_84f83f82_84528451_518aef3f_853f82ac_52805185;
+defparam bootram.RAM1.INIT_0A=256'h80e4518a_5184cf3f_539f5280_8ac83f82_3f82ac51_905184de_d53f9052_82ac518a;
+defparam bootram.RAM1.INIT_0B=256'hca3f9f52_529e5184_25df389f_13537280_8aac3fff_3f80e451_9c5184c2_b93f9f52;
+defparam bootram.RAM1.INIT_0C=256'h2a810680_8c08708b_3d0d8280_3d0d0480_0b800c84_e0840c81_3f890b81_815184a6;
+defparam bootram.RAM1.INIT_0D=256'h58595775_055a5757_70802582_05337030_028c05a7_0d7a7d7f_0d04f93d_0c51823d;
+defparam bootram.RAM1.INIT_0E=256'h53805481_709f2a51_8a557330_55738338_2e883888_05557583_72802588_822e9338;
+defparam bootram.RAM1.INIT_0F=256'h54805486_2b075154_05707284_777131fe_812cff05_2e973876_72547280_77259e38;
+defparam bootram.RAM1.INIT_10=256'hae8f3f81_52811851_ae973f73_06527751_3f7281ff_7b51aea1_80547452_39735381;
+defparam bootram.RAM1.INIT_11=256'h7551fee6_bd537852_5580ca54_05335681_3d0d029f_3d0d04fb_ae873f89_5280da51;
+defparam bootram.RAM1.INIT_12=256'hff065372_3f800881_d63ffebb_81528151_51adde3f_815280c5_04fe3d0d_3f873d0d;
+defparam bootram.RAM1.INIT_13=256'h70565480_7a575781_fa3d0d78_843d0d04_e0800c53_70900781_81e08008_802ef338;
+defparam bootram.RAM1.INIT_14=256'h80558113_ff2e8338_33527181_38805471_70802e83_70335252_9e387217_53727627;
+defparam bootram.RAM1.INIT_15=256'ha8348653_810b80e5_04fe3d0d_0c883d0d_81517080_802e8338_74075170_53df3974;
+defparam bootram.RAM1.INIT_16=256'h80e5a834_bc38810b_a8335574_3d0d80e5_3d0d04f9_beab3f84_80e4ac51_80dc8c52;
+defparam bootram.RAM1.INIT_17=256'h7551fef4_9c388652_5574802e_0881ff06_addf3f80_5280d051_70545682_8654873d;
+defparam bootram.RAM1.INIT_18=256'h3d0d0481_0b800c89_3f80e4ac_ac51bde1_755280e4_8c388653_ff065574_3f800881;
+defparam bootram.RAM1.INIT_19=256'he5a43484_38810b80_335574b9_0d80e5a4_0c04fb3d_0880e4a8_3480dc88_0b80e5a4;
+defparam bootram.RAM1.INIT_1A=256'h3dfc0551_38845287_74802e99_81ff0655_803f8008_80d051ad_05538c52_54873dfc;
+defparam bootram.RAM1.INIT_1B=256'h3d0d7756_3d0d04fb_0b800c87_0c80e4a8_7580e4a8_55748638_0881ff06_fe923f80;
+defparam bootram.RAM1.INIT_1C=256'h0c810b80_0880e4a8_2e8d3875_06557480_800881ff_51abc63f_8c5280d0_84547553;
+defparam bootram.RAM1.INIT_1D=256'hac0c81e0_077080e5_e5ac0806_75067180_0d730973_0d04803d_800c873d_e5a43474;
+defparam bootram.RAM1.INIT_1E=256'he0980c51_e5b00c81_06077080_80e5b008_73750671_3d0d7309_3d0d0480_8c0c5182;
+defparam bootram.RAM1.INIT_1F=256'h3d0d8a52_3d0d04ff_72800c84_5181c73f_70535380_fe3d0d74_81af3f04_823d0d04;
+defparam bootram.RAM1.INIT_20=256'h38811574_72802e90_ff065454_74337081_77795656_04fb3d0d_3f833d0d_805181b6;
+defparam bootram.RAM1.INIT_21=256'h3f833d0d_528051cd_ff3d0d73_873d0d04_800b800c_913fe539_76525581_81ff0653;
+defparam bootram.RAM1.INIT_22=256'hff3d0d73_843d0d04_800b800c_5180e73f_3f8a5272_5253ffbd_74765370_04fe3d0d;
+defparam bootram.RAM1.INIT_23=256'h3d0d73a0_3d0d04ff_b4123482_053380e4_7251028f_04803d0d_3f833d0d_528051dd;
+defparam bootram.RAM1.INIT_24=256'hb4133352_805380e4_04fe3d0d_51833d0d_22720c53_dc940570_05751080_29829080;
+defparam bootram.RAM1.INIT_25=256'h0d767856_0d04fc3d_e538843d_53827325_ce3f8113_33527251_80e4b813_7251c63f;
+defparam bootram.RAM1.INIT_26=256'h3f73a029_527351de_0687388d_812e0981_14335372_3880e4b4_09810695_54748a2e;
+defparam bootram.RAM1.INIT_27=256'h82908005_0d74a029_0d04fe3d_150c863d_f838748c_5372802e_54841408_82908005;
+defparam bootram.RAM1.INIT_28=256'h81a8880c_3d0d800b_3d0d04ff_72800c84_90120853_802e8538_52ff5370_88110852;
+defparam bootram.RAM1.INIT_29=256'h3d0d04fd_a8880c83_81800b81_a8840c51_70882a81_81a8800c_7081ff06_80e4c022;
+defparam bootram.RAM1.INIT_2A=256'h70810651_0870862a_3881a890_802e8186_54815171_05335553_02880597_3d0d7678;
+defparam bootram.RAM1.INIT_2B=256'h81065151_70812a70_81a89008_81a8900c_0c81900b_0781a88c_38721081_515170f1;
+defparam bootram.RAM1.INIT_2C=256'h2eb13880_ba387180_5170802e_32515151_81067081_70872a70_81a89008_5170f138;
+defparam bootram.RAM1.INIT_2D=256'hf13881a8_51515170_2a708106_90087081_900c81a8_517081a8_2e8338a0_e8517181;
+defparam bootram.RAM1.INIT_2E=256'h0c853d0d_900c7080_c00b81a8_51883980_52cc3981_5634ff12_74708105_8c085170;
+defparam bootram.RAM1.INIT_2F=256'h70f13872_06515151_862a7081_a8900870_55535481_05970533_76780288_04fd3d0d;
+defparam bootram.RAM1.INIT_30=256'h70810651_0870812a_0c81a890_7081a890_38819051_71802e84_0c81d051_1081a88c;
+defparam bootram.RAM1.INIT_31=256'h71802e80_2e80cf38_51517080_81325151_70810670_0870872a_3881a890_515170f1;
+defparam bootram.RAM1.INIT_32=256'h812a7081_a8900870_a8900c81_90517081_812e8338_80d05171_81a88c0c_c5387333;
+defparam bootram.RAM1.INIT_33=256'h388114ff_70802e8e_51515151_06708132_872a7081_a8900870_70f13881_06515151;
+defparam bootram.RAM1.INIT_34=256'h0d755480_0d04fd3d_800c853d_0c805170_0b81a890_8a3980c0_b7398151_135354ff;
+defparam bootram.RAM1.INIT_35=256'h1353e239_27f13881_868d9f71_73315151_b8ac0870_ac085281_9b3881b8_53727425;
+defparam bootram.RAM1.INIT_36=256'h82808c0c_840cff0b_ef0b8280_8280800c_0c81e20b_0b828088_ff3d0dff_853d0d04;
+defparam bootram.RAM1.INIT_37=256'h0d828088_0d04fb3d_f138833d_51708025_540cff11_72708405_87519eea_80efd852;
+defparam bootram.RAM1.INIT_38=256'h8f387251_5271802e_55747606_80efd855_8053810b_06585152_808c0871_08700982;
+defparam bootram.RAM1.INIT_39=256'h0d04ff3d_dc38873d_53877325_76105755_81138415_8c0c8f39_2d748280_73085271;
+defparam bootram.RAM1.INIT_3A=256'h70720682_82808808_722b7009_710c5181_efd80575_71842980_87269f38_0d735271;
+defparam bootram.RAM1.INIT_3B=256'hc80c833d_0c5281e0_0881e0c4_05227470_3d0d0292_0d0404ff_5152833d_80880c53;
+defparam bootram.RAM1.INIT_3C=256'he0cc0c82_38820b81_70802ef3_84065151_b8a00870_e0cc0c81_0d810b81_0d04803d;
+defparam bootram.RAM1.INIT_3D=256'h81b8a008_802e9338_06545272_a0087081_3d0d81b8_c00c04fe_3f7181e0_3d0d04de;
+defparam bootram.RAM1.INIT_3E=256'hdca051f8_2e8b3880_51527180_2a708106_9a397181_81808052_710c5353_7571902a;
+defparam bootram.RAM1.INIT_3F=256'h802ef238_06515170_087080c0_0d81b8a0_0d04803d_800c843d_3f725271_d33fff9e;
+defparam bootram.RAM2.INIT_00=256'hb8a00870_cc0c5281_880781e0_2270902b_0d028e05_0d04ff3d_800c823d_8180800b;
+defparam bootram.RAM2.INIT_01=256'h2e8638ba_80537280_3d0d7554_3d0d04fd_e0cc0c83_38840b81_70802ef3_90065151;
+defparam bootram.RAM2.INIT_02=256'h77831133_04fb3d0d_38853d0d_857327e6_3f811353_5252a5c0_72147033_51f7a53f;
+defparam bootram.RAM2.INIT_03=256'h7e616302_f63d0d7c_873d0d04_5180ed3f_5680dca4_54703353_55811133_56821133;
+defparam bootram.RAM2.INIT_04=256'h52ad5178_2e8a3879_8f387580_57768025_5f5d5b59_9f2a515b_33703070_9005bb05;
+defparam bootram.RAM2.INIT_05=256'h77527651_51ffbd3f_863f8008_527651ad_54805377_38795578_77772694_2d763057;
+defparam bootram.RAM2.INIT_06=256'h823d0d04_51f68d3f_028b0533_04803d0d_2d8c3d0d_05335178_0880dcb0_ad9e3f80;
+defparam bootram.RAM2.INIT_07=256'hd1387681_75802e81_ff065757_78337081_d15c5a58_055208a1_3d707084_f73d0d8c;
+defparam bootram.RAM2.INIT_08=256'h24a03875_387580f0_f02e80fb_57597580_81197033_0680db38_a52e0981_ff065675;
+defparam bootram.RAM2.INIT_09=256'h8b397580_80c63881_7580e42e_38819539_802e819e_248a3875_387580e3_80e32eb9;
+defparam bootram.RAM2.INIT_0A=256'h39778419_ba3880ec_7580f82e_3880f539_f32e80db_8b387580_7580f524_f52eac38;
+defparam bootram.RAM2.INIT_0B=256'h80539039_55a1d154_52595680_84197108_80da3977_7551792d_59568052_83123352;
+defparam bootram.RAM2.INIT_0C=256'h55a1d154_52595680_84197108_52923977_5481538a_8055a1d1_08525956_77841971;
+defparam bootram.RAM2.INIT_0D=256'h52767081_2e8e3880_33567580_59595676_84197108_3f9e3977_7551fdd0_80539052;
+defparam bootram.RAM2.INIT_0E=256'h04803d0d_81e0d00c_0d048a0b_800c8b3d_a339800b_811959fe_792dec39_05583351;
+defparam bootram.RAM2.INIT_0F=256'h88059b05_0d797b02_0d04fc3d_ef38823d_51515170_32708106_708c2a81_81b8b408;
+defparam bootram.RAM2.INIT_10=256'h81065151_72822a70_810a0752_2e863871_54557080_06555556_7b077281_3372982b;
+defparam bootram.RAM2.INIT_11=256'he0d80c73_d40c7081_3f7181e0_5151ffa9_3179712b_0752a075_3871820a_70802e86;
+defparam bootram.RAM2.INIT_12=256'h55558053_76787a54_04fc3d0d_0c863d0d_08517080_3f81b880_8938ff95_5173802e;
+defparam bootram.RAM2.INIT_13=256'h7183ffff_802e8d38_902a5170_51ee3971_81155553_70227305_38721015_7274278f;
+defparam bootram.RAM2.INIT_14=256'h3f767008_b851aed9_755280e5_3d0d8653_3d0d04fd_71800c86_0552ec39_0672902a;
+defparam bootram.RAM2.INIT_15=256'h8025f338_12525270_0c8812ff_89518072_80e5c852_04ff3d0d_54853d0d_80e5c00c;
+defparam bootram.RAM2.INIT_16=256'h12881252_2e8e3881_22547274_c4525270_800b80e5_96052253_fd3d0d02_833d0d04;
+defparam bootram.RAM2.INIT_17=256'hc73f8008_06535856_7183ffff_3d0d787a_3d0d04fa_70800c85_ee388051_52897225;
+defparam bootram.RAM2.INIT_18=256'h55527180_73088815_c4555555_c80b80e5_800880e5_050cad39_76800884_802e8938;
+defparam bootram.RAM2.INIT_19=256'hf13d0d86_883d0d04_7684140c_3f757323_eb389bee_55897525_15881454_2e8f3881;
+defparam bootram.RAM2.INIT_1A=256'h3f908002_0551ad99_52913ddc_923d8805_a83f7353_055254ad_53923dd6_7054933d;
+defparam bootram.RAM2.INIT_1B=256'h8405aa05_81808002_0b8c3d23_a6052380_80028405_0b8b3d23_23818a80_8405a205;
+defparam bootram.RAM2.INIT_1C=256'hfdb73f80_3de40551_538a5291_5d665e80_ae052368_80028405_0b8d3d23_2380c091;
+defparam bootram.RAM2.INIT_1D=256'h028405be_913d2380_0523800b_028405ba_23963d22_3d22903d_ae052398_08028405;
+defparam bootram.RAM2.INIT_1E=256'h805b800b_04e83d0d_3f913d0d_05519df1_2981e684_526980c0_913dd405_0523ac53;
+defparam bootram.RAM2.INIT_1F=256'hf83f0280_f80551ab_b8529a3d_865380e5_51ac863f_9a3df205_539b3d52_973d2386;
+defparam bootram.RAM2.INIT_20=256'h436e44a1_1143f005_0b9b3dc4_08585a80_3f800880_0523f7e2_840580e2_f2052202;
+defparam bootram.RAM2.INIT_21=256'h56845875_06408c3d_088305fc_085fa33d_6e5ea13d_845c905d_3d084659_3d0845a3;
+defparam bootram.RAM2.INIT_22=256'h9a387383_5473802e_760c7508_27843873_5a557375_71315156_7c319080_08701a78;
+defparam bootram.RAM2.INIT_23=256'h08527651_08539416_efe63f75_80dccc51_802e8838_83065473_38941608_0654738c;
+defparam bootram.RAM2.INIT_24=256'h78822a51_3880c059_78bf2684_25ffac38_59577780_0817ff19_70840557_9cc33f75;
+defparam bootram.RAM2.INIT_25=256'h840580ca_055a7902_237f1f94_800b943d_4040818a_3d0d6b6e_3d0d04ea_f6e83f9a;
+defparam bootram.RAM2.INIT_26=256'h02840580_963d2380_80075a79_236980c0_0580ce05_80800284_953d2381_0523800b;
+defparam bootram.RAM2.INIT_27=256'h840580d2_095a7902_e03f8008_70525cfa_8a52933d_68478053_e5c00846_d2052380;
+defparam bootram.RAM2.INIT_28=256'hf7c23f7a_80dcf851_5a799238_0881ff06_8ac83f80_70535c5e_7053983d_0523913d;
+defparam bootram.RAM2.INIT_29=256'h7b1d7c1f_8053805c_557b5490_6b575d94_6d596058_39027f5a_edd53fa9_51f6b63f;
+defparam bootram.RAM2.INIT_2A=256'h05228a3d_7f5802ae_04f73d0d_3f983d0d_ef38fd89_5c867c26_7b34811c_5b5b7933;
+defparam bootram.RAM2.INIT_2B=256'h88548b3d_77567e55_05a60523_23800284_57768b3d_05238818_028405a2_238d3d22;
+defparam bootram.RAM2.INIT_2C=256'h0523860b_028405b2_3d239080_0d810b8e_0d04ee3d_9e3f8b3d_527d51fe_f8055391;
+defparam bootram.RAM2.INIT_2D=256'h0551a8b5_52943dec_86538008_23ea9c3f_8405b605_05348102_028405b5_8f3d3484;
+defparam bootram.RAM2.INIT_2E=256'h3feacf3f_0551a9b2_52943df6_3f865380_0551a8a5_52943df2_84538008_3feaeb3f;
+defparam bootram.RAM2.INIT_2F=256'h5a80dcc4_805b7a1c_54908653_943de405_80569c55_80588057_025c8059_80080843;
+defparam bootram.RAM2.INIT_30=256'h5f5d7d90_088e1122_3d0daa3d_3d0d04d9_fbcb3f94_7b26ef38_811b5b86_1b337a34;
+defparam bootram.RAM2.INIT_31=256'ha851f5a0_795280dd_9b268d38_055b5b79_088429f2_901dac3d_06829d38_862e0981;
+defparam bootram.RAM2.INIT_32=256'hd438841b_09810686_7990802e_821b225a_0686e238_812e0981_7a225a79_3f86ee39;
+defparam bootram.RAM2.INIT_33=256'h52408885_389e1d70_810686b9_79812e09_861b225a_0686c638_842e0981_225a798c;
+defparam bootram.RAM2.INIT_34=256'h085c8008_a5e73f80_ffa80551_c052a93d_845380e5_3f800843_525f87fd_3fa81d70;
+defparam bootram.RAM2.INIT_35=256'h80fe0523_22028405_3d23821b_3f7a22a1_7951a6c5_80e5b852_3d5a8653_868f38a7;
+defparam bootram.RAM2.INIT_36=256'ha93de405_86537952_81820523_82028405_81810534_33028405_3d34851b_841b33a2;
+defparam bootram.RAM2.INIT_37=256'h7a51a5f5_53981d52_8e055b86_843f0281_05525aa6_53aa3dea_8470547f_51a6923f;
+defparam bootram.RAM2.INIT_38=256'h7c597c58_3f027c5a_7e51a5dd_86537a52_3f9e3d5f_0551a5e9_52a93df4_3f79537f;
+defparam bootram.RAM2.INIT_39=256'hef38f999_5c867c26_7b34811c_5b5b7933_7b1d7f1d_05547d53_55a93ddc_7c575d9c;
+defparam bootram.RAM2.INIT_3A=256'h810684d1_60842e09_2a435b5b_7022708c_e438901d_09810684_7d90802e_3f84ee39;
+defparam bootram.RAM2.INIT_3B=256'hb4387e5e_065f7e84_2280ffff_c038861b_09810684_5a79852e_708f0651_3879882a;
+defparam bootram.RAM2.INIT_3C=256'h535b5ca3_e5c05470_1c625580_815e7e90_80088338_51a3f63f_c452821d_865380dc;
+defparam bootram.RAM2.INIT_3D=256'h33821c22_b83f891b_9c1d5184_38881d52_802e8481_7d87387b_8338815c_e03f8008;
+defparam bootram.RAM2.INIT_3E=256'h11225d5d_08a41f84_8c1b087a_0683de38_912e0981_81bb387f_407f812e_ec11405d;
+defparam bootram.RAM2.INIT_3F=256'h535d5df5_1d821d22_39ac1de4_ef3f83bd_ddc851f1_537d5280_2e8f3879_42407d7a;
+defparam bootram.RAM3.INIT_00=256'h527951a3_5a88537d_3d993d5f_237f499a_7a22993d_2e83a638_42800880_c33f8008;
+defparam bootram.RAM3.INIT_01=256'h05527951_a93dffb4_60478853_22973d23_c83f821b_527f51a3_40885379_d43f9c3d;
+defparam bootram.RAM3.INIT_02=256'h337b3481_1f5b5b79_5c7b1d7c_7e843d5e_7b567c55_51a3aa3f_5379527d_a3b33f88;
+defparam bootram.RAM3.INIT_03=256'h8405085a_26ef3861_1b5b887b_051c3481_79330284_5b7f1b5a_26ef3880_1c5c887c;
+defparam bootram.RAM3.INIT_04=256'h39811a33_bb388295_7d882e81_832e8a38_405b427d_a41e7033_398c1b08_792d82ad;
+defparam bootram.RAM3.INIT_05=256'hf4387c22_09810681_5c79912e_12335c5e_80c01e89_a238ac1d_09810681_5a79832e;
+defparam bootram.RAM3.INIT_06=256'h3d5c5e88_4b983d9b_9b3d2379_085a7c22_fe388c1c_08802e80_80084180_51f4813f;
+defparam bootram.RAM3.INIT_07=256'h3d23794d_821d229d_901c085a_51a2823f_537d527f_963d4088_51a28e3f_537a527d;
+defparam bootram.RAM3.INIT_08=256'h5e5c7b1d_557e843d_3f7e567e_7d51a1e1_88537a52_51a1ea3f_cc05527a_8853a93d;
+defparam bootram.RAM3.INIT_09=256'h811b5b88_84051c34_5a793302_805b7f1b_7c26ef38_811c5c88_79337b34_7c1f5b5b;
+defparam bootram.RAM3.INIT_0A=256'h3d347e02_5d5d7e95_ac1de41d_3f80de39_e951e598_5a792d80_60840508_7b26ef38;
+defparam bootram.RAM3.INIT_0B=256'h05237e53_840580d2_861a2202_22963d23_0523841a_840580ce_05347e02_840580cd;
+defparam bootram.RAM3.INIT_0C=256'h840580ce_095a7902_c03f8008_527c51f1_537b812a_cc3f8008_70525bf1_6052943d;
+defparam bootram.RAM3.INIT_0D=256'h94085553_800b80e6_04fc3d0d_3fa93d0d_6151f5f7_7a537f52_7c557d54_05237b56;
+defparam bootram.RAM3.INIT_0E=256'h72518b39_81068538_70752e09_8c135351_56517108_80e69c54_38767008_727427a4;
+defparam bootram.RAM3.INIT_0F=256'h3f800880_5755ffb9_77797153_04fb3d0d_0c863d0d_ff517080_7326e738_81135373;
+defparam bootram.RAM3.INIT_10=256'h0680e698_08811187_3980e698_e6940c8e_38811480_73872689_e6940854_25ba3880;
+defparam bootram.RAM3.INIT_11=256'h80081080_14519439_5280e6a0_54865375_9c120c51_760880e6_1470822b_0c547310;
+defparam bootram.RAM3.INIT_12=256'hd83f8054_0d7551fe_0d04fd3d_a43f873d_a005519f_842980e6_53755273_08055486;
+defparam bootram.RAM3.INIT_13=256'h81547380_519efa3f_a0055276_842980e6_54865373_10800805_99388008_73800824;
+defparam bootram.RAM3.INIT_14=256'h07831633_70882b72_07821433_2b71902b_12337198_75703381_04fd3d0d_0c853d0d;
+defparam bootram.RAM3.INIT_15=256'h387383ff_595776a8_e6fc2256_0d7d7f80_0d04f93d_5452853d_52535456_7107800c;
+defparam bootram.RAM3.INIT_16=256'h51547674_80e78005_14709029_38739029_832680d3_52565473_22707231_ff068b3d;
+defparam bootram.RAM3.INIT_17=256'h88538a3d_90291554_26ad3874_57547483_70723157_068d3d22_7383ffff_2380c039;
+defparam bootram.RAM3.INIT_18=256'h9d3f8116_547451e3_17703353_27913875_80567578_519dea3f_80e78005_52739029;
+defparam bootram.RAM3.INIT_19=256'h800b8288_54807323_80e78054_fc23800b_052280e6_3d0d029a_3d0d04fc_56ec3989;
+defparam bootram.RAM3.INIT_1A=256'h837427d9_90145454_3f811482_0551ef9b_e6fc2274_b5ae5280_828c140c_140c800b;
+defparam bootram.RAM3.INIT_1B=256'h38758288_567581be_70810651_7c2c8132_805a5c84_800b80e7_04f43d0d_38863d0d;
+defparam bootram.RAM3.INIT_1C=256'h800881ff_2e80c538_3f8008ff_7b51e2e2_1a88055b_80d63878_7981ff26_1a085b5d;
+defparam bootram.RAM3.INIT_1D=256'h38815d77_76802e83_59515858_25075351_80257180_32703072_7030728d_06708a32;
+defparam bootram.RAM3.INIT_1E=256'h27ffb138_5a81ff7a_1a0c811a_800b828c_82881a0c_19088105_5d348288_7b708105;
+defparam bootram.RAM3.INIT_1F=256'h78225675_7627bf38_1b0c568b_8111828c_828c1908_387c9138_802e80d2_82881908;
+defparam bootram.RAM3.INIT_20=256'h81185888_75337734_781a5757_5b58771a_800b833d_55881954_82881908_802eab38;
+defparam bootram.RAM3.INIT_21=256'h82901a5a_1a0c811c_800b828c_82881a0c_a83f800b_7c0551f2_80e6fc22_7826ef38;
+defparam bootram.RAM3.INIT_22=256'h0284059d_94ba3f80_c0526851_70545780_3d0d883d_3d0d04ea_fea9388e_5c837c27;
+defparam bootram.RAM3.INIT_23=256'h51547381_74167033_81069438_81aa2e09_2e9d3873_547381ff_17703351_05575574;
+defparam bootram.RAM3.INIT_24=256'hf93d0d86_983d0d04_5473800c_27d13880_1555be75_548b3981_06853881_992e0981;
+defparam bootram.RAM3.INIT_25=256'h09810683_8008752e_5199ca3f_ddec5273_55845380_93ea3f80_84527951_3d705454;
+defparam bootram.RAM3.INIT_26=256'h81ff0655_c23f8008_8dd73f8a_04fc3d0d_81e0940c_0d04810b_800c893d_38815574;
+defparam bootram.RAM3.INIT_27=256'h74b53880_51818339_3880ddf0_51547388_70810651_08708d2a_3f81b8b4_805189c1;
+defparam bootram.RAM3.INIT_28=256'h89873f82_c33f8151_ded451de_2e9a3880_3f800880_0a51febf_d73fb080_dea851de;
+defparam bootram.RAM3.INIT_29=256'h802ebb38_e33f8008_800a51fe_80cc3998_80df8c51_5184b53f_3fb0800a_ac51e2f6;
+defparam bootram.RAM3.INIT_2A=256'h3f82ac51_8451de80_bf3f80e0_800a5192_ffff5298_80805380_de963f83_80dfd851;
+defparam bootram.RAM3.INIT_2B=256'he451dddc_883980e0_5183e93f_e2a83f80_3f82ac51_a851ddf0_e53f80e0_e2b83ffe;
+defparam bootram.RAM3.INIT_2C=256'h51dc8b3f_3fa052a0_5254e6c8_5380e1b0_3d0d7570_c00c04fd_047180ef_3f863d0d;
+defparam bootram.RAM3.INIT_2D=256'h80efc008_51dbef3f_0da05280_0d04fe3d_722d853d_85387351_5372802e_80efc008;
+defparam bootram.RAM3.INIT_2E=256'h70810651_8008862a_8d3fff0b_0d9a5189_0d04fc3d_722d843d_85388051_5372802e;
+defparam bootram.RAM3.INIT_2F=256'h71828024_802e9b38_e4547182_06535580_80088680_ec38820b_71802e80_53548155;
+defparam bootram.RAM3.INIT_30=256'h08528551_88c83f80_ff548451_802e8338_e8547184_388a3987_71802e8e_8a388a54;
+defparam bootram.RAM3.INIT_31=256'he1e85553_efcc0c80_11337080_0780e2a8_70830672_80088a2c_882a8c06_88c03f71;
+defparam bootram.RAM3.INIT_32=256'h387480ef_c4082e98_3f7480ef_5252dc88_e4c81108_2b8c0680_ef3f7182_515452db;
+defparam bootram.RAM3.INIT_33=256'h7380efc8_81069638_74822e09_c13f9e39_06a338fe_812e0981_2ea63874_c40c7482;
+defparam bootram.RAM3.INIT_34=256'h0dd8b03f_0d04fd3d_cd3f863d_3f995187_7351fdfb_0cfea73f_7380efc8_082e8e38;
+defparam bootram.RAM3.INIT_35=256'hd63f81ae_52985187_87ac3f8d_c80c9951_ff0b80ef_80efc40c_a23f800b_80085187;
+defparam bootram.RAM3.INIT_36=256'h70535484_07f49f06_80089080_51878f3f_e0f03f84_ce528451_87cd3fbb_80529c51;
+defparam bootram.RAM3.INIT_37=256'h5186e33f_e3e63f80_80e28051_08537352_2e8d3880_3f738008_845186fa_5187b03f;
+defparam bootram.RAM3.INIT_38=256'h872a0771_2a820671_05337085_3d0d0297_3d0d04fd_87893f85_07528051_80088480;
+defparam bootram.RAM3.INIT_39=256'hff067685_07077081_a0067173_0674832b_07731090_06717307_72812a88_832a8406;
+defparam bootram.RAM3.INIT_3A=256'h853d0d04_52555552_52535155_c0800c51_81ff0682_872b0770_70720778_2b80c006;
+defparam bootram.RAM3.INIT_3B=256'h923f8199_81aa51ff_51ff983f_9e3f81ff_81ff51ff_d00a0753_d00a0681_fe3d0d74;
+defparam bootram.RAM3.INIT_3C=256'h81ff0651_fef53f72_ff065252_882a7081_ff813f72_3f80e151_b251ff87_51ff8c3f;
+defparam bootram.RAM3.INIT_3D=256'h5253fecf_7081ff06_3f72902a_2a51fedb_e23f7298_818151fe_51fee83f_feed3fb2;
+defparam bootram.RAM3.INIT_3E=256'h51feb03f_feb53f80_ba3fa051_3f8e51fe_8051febf_51fec43f_ca3f81a1_3fb051fe;
+defparam bootram.RAM3.INIT_3F=256'h5183ce3f_805280d0_3dfc0553_0d825487_0d04fb3d_a63f843d_3f8051fe_a051feab;
+defparam bootram.RAM4.INIT_00=256'h82932690_58595777_08841208_0880d73d_0d80d53d_04ffb23d_0c873d0d_863d2280;
+defparam bootram.RAM4.INIT_01=256'h2980e384_b2387584_75962681_ff9f1656_3f81bc39_b851e1b4_945280e2_38775382;
+defparam bootram.RAM4.INIT_02=256'h0b81e4d0_e2cc0c80_0c810b81_0b81e18c_08085e81_d5e43f80_0480c15c_05567508;
+defparam bootram.RAM4.INIT_03=256'hffff065e_3f800883_f839fef6_80c65c80_3f80085f_085e8c9d_8c993f80_0c818a39;
+defparam bootram.RAM4.INIT_04=256'heff8518a_80d33980_3f80c55c_f85189f5_085280ef_08538c17_e8399017_80d65c80;
+defparam bootram.RAM4.INIT_05=256'h08528c17_17539017_5cb73994_bc3980c2_3880c45c_75802e86_81ff0656_ba3f8008;
+defparam bootram.RAM4.INIT_06=256'h80d25c8d_518bb93f_528c1708_53901708_3dfe8005_a43980d0_3f80d75c_085188dc;
+defparam bootram.RAM4.INIT_07=256'h58771980_0b833d5a_ec055480_80d03dfd_5c829455_3f8339a0_8051fcf8_3980d35c;
+defparam bootram.RAM4.INIT_08=256'h0d04803d_3f80d03d_8251e8bd_ec388380_58887826_77348118_57577533_d23d7905;
+defparam bootram.RAM4.INIT_09=256'h2b075757_05337188_028405ab_02a70533_3ff93d0d_ff518397_51d68d3f_0d80e3e0;
+defparam bootram.RAM4.INIT_0A=256'h74ff1656_5a575758_7a7c7f7f_04f83d0d_3f893d0d_8051e1aa_75538152_82559854;
+defparam bootram.RAM4.INIT_0B=256'h538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473_b7387581_54807425;
+defparam bootram.RAM4.INIT_0C=256'h81547380_8538c139_3f73802e_8a51da86_81ff0654_d83f8008_ff0651d8_05527781;
+defparam bootram.RAM4.INIT_0D=256'h3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533_04fa3d0d_0c8a3d0d;
+defparam bootram.RAM4.INIT_0E=256'h3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d_d051ff89_81f75280;
+defparam bootram.RAM4.INIT_0F=256'h76537b52_77259738_2e9e3880_56547380_81ff0670_f83f8008_705256d7_02a70533;
+defparam bootram.RAM4.INIT_10=256'h3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056_3f800881_7551d6bb;
+defparam bootram.RAM4.INIT_11=256'h83388156_2e098106_567480de_883d3356_a03f800b_80d051ff_5381f752_883dfc05;
+defparam bootram.RAM4.INIT_12=256'h0b81c0b0_ac0c89b0_a60b81c0_81c0800c_0c80eb0b_0b81c094_3d0d0499_75800c88;
+defparam bootram.RAM4.INIT_13=256'h0870812a_0c81c0a4_0b81c0a0_980c5182_810781c0_be800670_0d72882b_0c04803d;
+defparam bootram.RAM4.INIT_14=256'h70810781_2bbe8006_3d0d7288_3d0d0480_08800c82_3881c0a8_515170f1_70810651;
+defparam bootram.RAM4.INIT_15=256'h70f13882_06515151_812a7081_c0a40870_c0a00c81_0c840b81_7381c09c_c0980c51;
+defparam bootram.RAM4.INIT_16=256'h72830652_52718a38_38758306_57577191_83065555_787a7c72_39fa3d0d_3d0d04ff;
+defparam bootram.RAM4.INIT_17=256'h7008720c_77117712_3873822b_73752794_2a725555_ca3f7282_38815188_71802e86;
+defparam bootram.RAM4.INIT_18=256'h515353d1_ec113354_8f0680e3_70842a70_fe3d0d74_883d0d04_1454e939_52545281;
+defparam bootram.RAM4.INIT_19=256'h2a708106_90087088_3d0d82e0_3d0d0480_d1ba3f84_11335253_0680e3ec_c73f728f;
+defparam bootram.RAM4.INIT_1A=256'h80075353_060780c0_067a8c80_337880ff_0d029305_0d04fe3d_f138823d_51515170;
+defparam bootram.RAM4.INIT_1B=256'hff0682e0_900c7581_0c7182e0_7682e080_5170f138_81065151_70882a70_82e09008;
+defparam bootram.RAM4.INIT_1C=256'h515170f1_70810651_0870882a_3882e090_72802e96_900c7251_800782e0_980c7182;
+defparam bootram.RAM4.INIT_1D=256'h53805280_55885480_940c8880_810b82e0_04fc3d0d_0c843d0d_08517080_3882e080;
+defparam bootram.RAM4.INIT_1E=256'h81ff0680_f13f8008_528151fe_8a805381_80559054_fc3d0d88_863d0d04_51ff873f;
+defparam bootram.RAM4.INIT_1F=256'h0dca3f80_0d04803d_d53f863d_528051fe_54865381_88805588_04fc3d0d_0c863d0d;
+defparam bootram.RAM4.INIT_20=256'h3d0d04fb_2ef43882_06517080_800881ff_3d0deb3f_3d0d0480_06800c82_08813281;
+defparam bootram.RAM4.INIT_21=256'h9b0a0753_fe9b0a06_55a05475_b43f8880_38dd3fff_8008269b_84e33f75_3d0d7756;
+defparam bootram.RAM4.INIT_22=256'h80557381_11565757_cb3d08ff_c93d0880_ba3d0d80_3d0d04ff_fe843f87_81528051;
+defparam bootram.RAM4.INIT_23=256'h548c8f3f_883d7052_5381ff52_a7388280_80082681_849f3f73_38751754_ff2681b4;
+defparam bootram.RAM4.INIT_24=256'h0b82e090_980c8880_3f7482e0_d43ffd9f_fefd3ffe_518aea3f_3d085273_755380cb;
+defparam bootram.RAM4.INIT_25=256'ha00b82e0_e0900c8a_88a00b82_82e0980c_800c810b_0a0782e0_0a0680c0_0c76fec0;
+defparam bootram.RAM4.INIT_26=256'h880c54fe_700882e0_54fe8415_82e08c0c_80157008_558f56fe_3f80c83d_900cfcef;
+defparam bootram.RAM4.INIT_27=256'h0b82e090_900c8a80_800b82e0_800c5488_700882e0_54fe8c15_82e0840c_88157008;
+defparam bootram.RAM4.INIT_28=256'hc83d0d04_74800c80_980c8155_800b82e0_25ffbc38_56567580_ff169016_0cfcb03f;
+defparam bootram.RAM4.INIT_29=256'h2e80c338_81577480_2680cb38_57738008_82db3f80_575a5656_7b7d7212_f93d0d79;
+defparam bootram.RAM4.INIT_2A=256'h7551fdeb_77537352_83387654_57767527_74317555_a2388280_5473802e_7581ff06;
+defparam bootram.RAM4.INIT_2B=256'h39fd8c3f_828054dc_7527e138_74548280_802e8e38_57595674_19767631_3f731674;
+defparam bootram.RAM4.INIT_2C=256'h3f800874_135481ed_2e8d3873_54557380_76787a56_04fc3d0d_0c893d0d_81577680;
+defparam bootram.RAM4.INIT_2D=256'h16565152_707406ff_3f800830_a63981cb_0c80750c_800b8416_0b88160c_27903880;
+defparam bootram.RAM4.INIT_2E=256'h3d0d7554_3d0d04fd_fcc93f86_160c7151_160c7188_0c740684_08307276_81bd3f80;
+defparam bootram.RAM4.INIT_2F=256'h823f8814_2e943881_08841508_81538814_802e9f38_70545271_0881ff06_fc983f80;
+defparam bootram.RAM4.INIT_30=256'h5481f90a_888055a0_04fc3d0d_0c853d0d_80537280_51fc943f_7088160c_08800805;
+defparam bootram.RAM4.INIT_31=256'h38d73f80_efd008a0_ff3d0d80_863d0d04_0a06800c_8008fe80_51faa33f_53815281;
+defparam bootram.RAM4.INIT_32=256'h80efd008_80efd00c_06933871_a02e0981_54515170_0881ff06_81ff0680_08882a70;
+defparam bootram.RAM4.INIT_33=256'h800c04f3_e4c20533_3f800880_3d0d04c0_71800c83_38f5b33f_82712784_ea115252;
+defparam bootram.RAM4.INIT_34=256'h800b82e0_56f9983f_f63d0d7d_2b800c04_810b8008_04ffa93f_082b800c_3f810b80;
+defparam bootram.RAM4.INIT_35=256'h88a80b82_82e0980c_800c810b_882b82e0_e0840c7c_0c8b0b82_0b82e090_980c8880;
+defparam bootram.RAM4.INIT_36=256'h900c8a80_800b82e0_80d33888_54737627_3f7e5580_900cf8e7_a80b82e0_e0900c8a;
+defparam bootram.RAM4.INIT_37=256'h883d7675_e080085b_84085a82_085982e0_5882e088_82e08c08_0cf8cc3f_0b82e090;
+defparam bootram.RAM4.INIT_38=256'h57348112_75708105_17517033_27913871_80527173_83387053_53707327_31525790;
+defparam bootram.RAM4.INIT_39=256'h08028c0c_f7893f8c_3d0d7251_3d0d0480_e0980c8c_39800b82_1454ffa9_52ec3972;
+defparam bootram.RAM4.INIT_3A=256'h0d8c0c04_0c54853d_80087080_5182de3f_08880508_0508528c_538c088c_fd3d0d80;
+defparam bootram.RAM4.INIT_3B=256'h800c5485_3f800870_085182b9_8c088805_8c050852_81538c08_0cfd3d0d_8c08028c;
+defparam bootram.RAM4.INIT_3C=256'h388c0888_088025ab_8c088805_08fc050c_0d800b8c_8c0cf93d_048c0802_3d0d8c0c;
+defparam bootram.RAM4.INIT_3D=256'h0c8c08f4_8c08f405_8838810b_08fc0508_f4050c8c_800b8c08_0888050c_0508308c;
+defparam bootram.RAM4.INIT_3E=256'h0b8c08f0_8c050c80_08308c08_8c088c05_8025ab38_088c0508_fc050c8c_05088c08;
+defparam bootram.RAM4.INIT_3F=256'h8c088c05_050c8053_088c08fc_8c08f005_08f0050c_38810b8c_fc050888_050c8c08;
+defparam bootram.RAM5.INIT_00=256'h388c08f8_08802e8c_8c08fc05_f8050c54_08708c08_81a73f80_88050851_08528c08;
+defparam bootram.RAM5.INIT_01=256'hfb3d0d80_08028c0c_8c0c048c_54893d0d_0870800c_8c08f805_08f8050c_0508308c;
+defparam bootram.RAM5.INIT_02=256'h8c08fc05_050c810b_308c0888_08880508_2593388c_88050880_050c8c08_0b8c08fc;
+defparam bootram.RAM5.INIT_03=256'h528c0888_088c0508_0c81538c_8c088c05_8c050830_8c388c08_05088025_0c8c088c;
+defparam bootram.RAM5.INIT_04=256'h308c08f8_08f80508_2e8c388c_fc050880_0c548c08_8c08f805_3f800870_050851ad;
+defparam bootram.RAM5.INIT_05=256'h08fc050c_0d810b8c_8c0cfd3d_048c0802_3d0d8c0c_800c5487_f8050870_050c8c08;
+defparam bootram.RAM5.INIT_06=256'h38800b8c_08802ea3_8c08fc05_0827ac38_8c088805_088c0508_f8050c8c_800b8c08;
+defparam bootram.RAM5.INIT_07=256'h0cc9398c_8c08fc05_fc050810_050c8c08_108c088c_088c0508_2499388c_088c0508;
+defparam bootram.RAM5.INIT_08=256'h088c0508_8805088c_a1388c08_88050826_05088c08_388c088c_802e80c9_08fc0508;
+defparam bootram.RAM5.INIT_09=256'h2a8c08fc_fc050881_050c8c08_078c08f8_08fc0508_f805088c_050c8c08_318c0888;
+defparam bootram.RAM5.INIT_0A=256'h88050870_8f388c08_0508802e_398c0890_050cffaf_2a8c088c_8c050881_050c8c08;
+defparam bootram.RAM5.INIT_0B=256'h3d0d8c0c_08800c85_8c08f405_f4050c51_08708c08_8c08f805_0c518d39_8c08f405;
+defparam bootram.RAM5.INIT_0C=256'h5271ff2e_b038ff12_5170802e_74078306_278c3874_56528372_78777956_04fc3d0d;
+defparam bootram.RAM5.INIT_0D=256'h098106e2_5571ff2e_ff145455_81158115_8106bd38_72712e09_74335253_a0387433;
+defparam bootram.RAM5.INIT_0E=256'h14545451_118414fc_068f3884_082e0981_51700873_04747454_0c863d0d_38800b80;
+defparam bootram.RAM5.INIT_0F=256'h55555555_7670797b_04fc3d0d_0c863d0d_72713180_55ffaf39_38707355_718326e9;
+defparam bootram.RAM5.INIT_10=256'h54337470_72708105_ff2e9838_ff125271_802ea738_83065170_38727507_8f72278c;
+defparam bootram.RAM5.INIT_11=256'h54087170_72708405_0d047451_800c863d_06ea3874_ff2e0981_ff125271_81055634;
+defparam bootram.RAM5.INIT_12=256'h72708405_8405530c_54087170_72708405_8405530c_54087170_72708405_8405530c;
+defparam bootram.RAM5.INIT_13=256'h70840553_05540871_38727084_83722795_8f26c938_f0125271_8405530c_54087170;
+defparam bootram.RAM5.INIT_14=256'h53558372_05335755_028c059f_0d767971_8339fc3d_387054ff_718326ed_0cfc1252;
+defparam bootram.RAM5.INIT_15=256'h125271ff_055534ff_73737081_ff2e9338_ff125271_802ea238_83065170_278a3874;
+defparam bootram.RAM5.INIT_16=256'h7227a538_5154518f_71902b07_2b750770_04747488_0c863d0d_ef387480_2e098106;
+defparam bootram.RAM5.INIT_17=256'hf0125271_8405530c_0c727170_70840553_530c7271_71708405_05530c72_72717084;
+defparam bootram.RAM5.INIT_18=256'h39fa3d0d_7053ff90_8326f238_fc125271_8405530c_38727170_83722790_8f26dd38;
+defparam bootram.RAM5.INIT_19=256'h5372ff2e_d438ff13_70802e80_07830651_d9387174_72802e80_54555552_787a7c70;
+defparam bootram.RAM5.INIT_1A=256'h802e80fc_ff065170_87387081_72802e81_8106a938_74712e09_74335651_b1387133;
+defparam bootram.RAM5.INIT_1B=256'h7581ff06_7081ff06_74335651_d1387133_2e098106_555272ff_15ff1555_38811281;
+defparam bootram.RAM5.INIT_1C=256'h38747655_74082e88_88387108_55837327_04717457_0c883d0d_52527080_71713151;
+defparam bootram.RAM5.INIT_1D=256'h06515151_84828180_120670f8_f7fbfdff_74087009_802eb138_fc135372_52ff9739;
+defparam bootram.RAM5.INIT_1E=256'h800b800c_52fedf39_38747655_76082ed0_d0387408_55837327_15841757_709a3884;
+defparam bootram.RAM5.INIT_1F=256'h3fffb080_0cffb0e4_7380efd4_812e9e38_08545472_0b80e49c_fd3d0d80_883d0d04;
+defparam bootram.RAM5.INIT_20=256'he33f80e4_c73fffaf_d40cffb0_3f7280ef_0851f6a3_b7dd3f80_528151ff_3f80e4dc;
+defparam bootram.RAM5.INIT_21=256'h525270ff_fc057008_80e4e40b_39ff3d0d_863f00ff_800851f6_ffb7c03f_dc528151;
+defparam bootram.RAM5.INIT_22=256'h04000000_ffb0f23f_3d0d0404_06f13883_ff2e0981_08525270_2dfc1270_2e913870;
+defparam bootram.RAM5.INIT_23=256'h2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069_21457272_00000040;
+defparam bootram.RAM5.INIT_24=256'h206e756d_6c697479_74696269_6f6d7061_65642063_70656374_3a204578_646c6572;
+defparam bootram.RAM5.INIT_25=256'h6e20636f_6f722069_21457272_25640a00_676f7420_62757420_25642c20_62657220;
+defparam bootram.RAM5.INIT_26=256'h65642070_70656374_3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f;
+defparam bootram.RAM5.INIT_27=256'h0a000000_74202564_7420676f_2c206275_68202564_656e6774_6164206c_61796c6f;
+defparam bootram.RAM5.INIT_28=256'h640a0000_203d2025_70656564_643a2073_616e6765_6b206368_206c696e_0a657468;
+defparam bootram.RAM5.INIT_29=256'h46504741_720a0000_6f616465_6f6f746c_44502062_31302055_50204e32_0a555352;
+defparam bootram.RAM5.INIT_2A=256'h4669726d_640a0000_723a2025_756d6265_7479206e_62696c69_70617469_20636f6d;
+defparam bootram.RAM5.INIT_2B=256'h640a0000_723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_77617265;
+defparam bootram.RAM5.INIT_2C=256'h65743a20_7061636b_65727920_65636f76_69702072_476f7420_00000000_61646472;
+defparam bootram.RAM5.INIT_2D=256'h00000785_00000785_00000785_00000785_00000785_00000785_00000690_00000000;
+defparam bootram.RAM5.INIT_2E=256'h00000785_00000785_00000785_0000075b_00000785_00000785_000006d5_000006ec;
+defparam bootram.RAM5.INIT_2F=256'h00000735_0000072e_00000729_00000724_0000069d_00000709_00000785_00000785;
+defparam bootram.RAM5.INIT_30=256'h01b200d9_05160364_14580a2c_3fff0000_0050c285_c0a80a02_00000749_0000073c;
+defparam bootram.RAM5.INIT_31=256'h43444546_38394142_34353637_30313233_2e256400_642e2564_25642e25_45000000;
+defparam bootram.RAM5.INIT_32=256'h69676e6d_6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff_00000000;
+defparam bootram.RAM5.INIT_33=256'h636f6d6d_6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c_656e7420;
+defparam bootram.RAM5.INIT_34=256'h696e6720_6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c_6f6e3a20;
+defparam bootram.RAM5.INIT_35=256'h697a6520_72642073_20776569_6172703a_646c655f_0a68616e_00000000_666f7220;
+defparam bootram.RAM5.INIT_36=256'h67746873_206c656e_74656e74_6e736973_696e636f_55445020_0a000000_3d202564;
+defparam bootram.RAM5.INIT_37=256'h50322b20_20555352_74696e67_53746172_0b0b0b0b_00000000_2025640a_3a202564;
+defparam bootram.RAM5.INIT_38=256'h69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520_696e2073;
+defparam bootram.RAM5.INIT_39=256'h726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000_6172652e;
+defparam bootram.RAM5.INIT_3A=256'h6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f;
+defparam bootram.RAM5.INIT_3B=256'h7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e;
+defparam bootram.RAM5.INIT_3C=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f;
+defparam bootram.RAM5.INIT_3D=256'h726f7567_67207468_6c6c696e_2e0a4661_6f756e64_67652066_20696d61_46504741;
+defparam bootram.RAM5.INIT_3E=256'h64207072_56616c69_72652e00_726d7761_6e206669_6c742d69_20627569_6820746f;
+defparam bootram.RAM5.INIT_3F=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563;
+defparam bootram.RAM6.INIT_00=256'h6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00;
+defparam bootram.RAM6.INIT_01=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765;
+defparam bootram.RAM6.INIT_02=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67;
+defparam bootram.RAM6.INIT_03=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000;
+defparam bootram.RAM6.INIT_04=256'h75696c74_746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20_20666f75;
+defparam bootram.RAM6.INIT_05=256'h2025640a_7420746f_64207365_53706565_2e000000_77617265_6669726d_2d696e20;
+defparam bootram.RAM6.INIT_06=256'h53594d4d_58000000_57455f52_58000000_57455f54_00000000_4e4f4e45_00000000;
+defparam bootram.RAM6.INIT_07=256'h6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865_43000000_45545249;
+defparam bootram.RAM6.INIT_08=256'h20676f74_7825782c_74652030_2077726f_4144563a_4e45475f_4155544f_5048595f;
+defparam bootram.RAM6.INIT_09=256'h6f722069_21457272_00030203_00000001_00030003_00000000_780a0000_20307825;
+defparam bootram.RAM6.INIT_0A=256'h65637465_20457870_6c65723a_68616e64_6b657420_20706163_64617465_6e207570;
+defparam bootram.RAM6.INIT_0B=256'h2025640a_20676f74_20627574_2025642c_6e677468_64206c65_796c6f61_64207061;
+defparam bootram.RAM6.INIT_0C=256'h000020eb_00002064_00002086_0000209b_000020eb_000020eb_00002045_00000000;
+defparam bootram.RAM6.INIT_0D=256'h000020eb_000020eb_000020eb_000020eb_000020eb_000020eb_000020eb_000020eb;
+defparam bootram.RAM6.INIT_0E=256'h000020b7_00002076_000020eb_000020eb_000020e1_000020ca_000020eb_000020eb;
+defparam bootram.RAM6.INIT_0F=256'h64756d6d_43444546_38394142_34353637_30313233_00000000_6f72740a_0a0a6162;
+defparam bootram.RAM6.INIT_10=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_65000000_792e6578;
+defparam bootram.RAM6.INIT_11=256'hffff0031_05050400_01010100_3fff0000_0050c285_c0a80a02_0000326c_00000000;
+defparam bootram.RAM6.INIT_12=256'h000031fc_10101200_000030dc_000030d4_000030cc_000030c4_000b0000_0018000f;
+defparam bootram.RAM6.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff;
+defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
diff --git a/fpga/usrp2/top/N2x0/capture_ddrlvds.v b/fpga/usrp2/top/N2x0/capture_ddrlvds.v
new file mode 100644
index 000000000..e261dcbe8
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/capture_ddrlvds.v
@@ -0,0 +1,55 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+
+module capture_ddrlvds
+  #(parameter WIDTH=7)
+   (input clk,
+    input ssclk_p,
+    input ssclk_n,
+    input [WIDTH-1:0] in_p,
+    input [WIDTH-1:0] in_n,
+    output reg [(2*WIDTH)-1:0] out);
+
+   wire [WIDTH-1:0] 	   ddr_dat;
+   wire 		   ssclk;
+   wire [(2*WIDTH)-1:0]    out_pre1;
+   reg [(2*WIDTH)-1:0] 	   out_pre2;
+   
+   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
+   clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
+   
+   genvar 	       i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1)
+	begin : gen_lvds_pins
+	   IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds 
+	      (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
+	   IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2
+	     (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk),
+	      .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
+	end
+   endgenerate
+
+   always @(posedge clk)
+     out_pre2 <= out_pre1;
+
+   always @(posedge clk)
+     out      <= out_pre2;
+   
+endmodule // capture_ddrlvds
diff --git a/fpga/usrp2/top/N2x0/u2plus.ucf b/fpga/usrp2/top/N2x0/u2plus.ucf
new file mode 100755
index 000000000..5fbe55c26
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/u2plus.ucf
@@ -0,0 +1,424 @@
+## Main 100 MHz Clock
+NET "CLK_FPGA_P"  LOC = "AA13"  ;
+NET "CLK_FPGA_N"  LOC = "Y13"  ;
+
+## ADC
+NET "ADC_clkout_p"  LOC = "P1"  ;
+NET "ADC_clkout_n"  LOC = "P2"  ;
+NET "ADCA_12_p"  LOC = "Y1"  ;
+NET "ADCA_12_n"  LOC = "Y2"  ;
+NET "ADCA_10_p"  LOC = "W3"  ;
+NET "ADCA_10_n"  LOC = "W4"  ;
+NET "ADCA_8_p"  LOC = "T7"  ;
+NET "ADCA_8_n"  LOC = "U6"  ;
+NET "ADCA_6_p"  LOC = "U5"  ;
+NET "ADCA_6_n"  LOC = "V5"  ;
+NET "ADCA_4_p"  LOC = "T10"  ;
+NET "ADCA_4_n"  LOC = "T9"  ;
+NET "ADCA_2_p"  LOC = "V1"  ;
+NET "ADCA_2_n"  LOC = "V2"  ;
+NET "ADCA_0_p"  LOC = "R8"  ;
+NET "ADCA_0_n"  LOC = "R7"  ;
+NET "ADCB_2_p"  LOC = "U7"  ;
+NET "ADCB_2_n"  LOC = "U8"  ;
+NET "ADCB_0_p"  LOC = "AA2"  ;
+NET "ADCB_0_n"  LOC = "AA3"  ;
+NET "ADCB_4_p"  LOC = "AE1"  ;
+NET "ADCB_4_n"  LOC = "AE2"  ;
+NET "ADCB_6_p"  LOC = "W1"  ;
+NET "ADCB_6_n"  LOC = "W2"  ;
+NET "ADCB_8_p"  LOC = "U3"  ;
+NET "ADCB_8_n"  LOC = "V4"  ;
+NET "ADCB_10_p"  LOC = "J1"  ;
+NET "ADCB_10_n"  LOC = "K1"  ;
+NET "ADCB_12_p"  LOC = "J3"  ;
+NET "ADCB_12_n"  LOC = "J2"  ;
+
+## DAC
+NET "DAC_LOCK"  LOC = "P4"  ;
+NET "DACA<0>"  LOC = "P8"  ;
+NET "DACA<1>"  LOC = "P9"  ;
+NET "DACA<2>"  LOC = "R5"  ;
+NET "DACA<3>"  LOC = "R6"  ;
+NET "DACA<4>"  LOC = "P7"  ;
+NET "DACA<5>"  LOC = "P6"  ;
+NET "DACA<6>"  LOC = "T3"  ;
+NET "DACA<7>"  LOC = "T4"  ;
+NET "DACA<8>"  LOC = "R3"  ;
+NET "DACA<9>"  LOC = "R4"  ;
+NET "DACA<10>"  LOC = "R2"  ;
+NET "DACA<11>"  LOC = "N1"  ;
+NET "DACA<12>"  LOC = "N2"  ;
+NET "DACA<13>"  LOC = "N5"  ;
+NET "DACA<14>"  LOC = "N4"  ;
+NET "DACA<15>"  LOC = "M2"  ;
+NET "DACB<0>"  LOC = "M5"  ;
+NET "DACB<1>"  LOC = "M6"  ;
+NET "DACB<2>"  LOC = "M4"  ;
+NET "DACB<3>"  LOC = "M3"  ;
+NET "DACB<4>"  LOC = "M8"  ;
+NET "DACB<5>"  LOC = "M7"  ;
+NET "DACB<6>"  LOC = "L4"  ;
+NET "DACB<7>"  LOC = "L3"  ;
+NET "DACB<8>"  LOC = "K3"  ;
+NET "DACB<9>"  LOC = "K2"  ;
+NET "DACB<10>"  LOC = "K5"  ;
+NET "DACB<11>"  LOC = "K4"  ;
+NET "DACB<12>"  LOC = "M10"  ;
+NET "DACB<13>"  LOC = "M9"  ;
+NET "DACB<14>"  LOC = "J5"  ;
+NET "DACB<15>"  LOC = "J4"  ;
+
+## TX DB GPIO
+NET "io_tx<15>"  LOC = "K6"  ;
+NET "io_tx<14>"  LOC = "L7"  ;
+NET "io_tx<13>"  LOC = "H2"  ;
+NET "io_tx<12>"  LOC = "H1"  ;
+NET "io_tx<11>"  LOC = "L10"  ;
+NET "io_tx<10>"  LOC = "L9"  ;
+NET "io_tx<9>"  LOC = "G3"  ;
+NET "io_tx<8>"  LOC = "F3"  ;
+NET "io_tx<7>"  LOC = "K7"  ;
+NET "io_tx<6>"  LOC = "J6"  ;
+NET "io_tx<5>"  LOC = "E1"  ;
+NET "io_tx<4>"  LOC = "F2"  ;
+NET "io_tx<3>"  LOC = "J7"  ;
+NET "io_tx<2>"  LOC = "H6"  ;
+NET "io_tx<1>"  LOC = "F5"  ;
+NET "io_tx<0>"  LOC = "G4"  ;
+
+## RX DB GPIO
+NET "io_rx<15>"  LOC = "AD1"  ;
+NET "io_rx<14>"  LOC = "AD2"  ;
+NET "io_rx<13>"  LOC = "AC2"  ;
+NET "io_rx<12>"  LOC = "AC3"  ;
+NET "io_rx<11>"  LOC = "W7"  ;
+NET "io_rx<10>"  LOC = "W6"  ;
+NET "io_rx<9>"  LOC = "U9"  ;
+NET "io_rx<8>"  LOC = "V8"  ;
+NET "io_rx<7>"  LOC = "AB1"  ;
+NET "io_rx<6>"  LOC = "AC1"  ;
+NET "io_rx<5>"  LOC = "V7"  ;
+NET "io_rx<4>"  LOC = "V6"  ;
+NET "io_rx<3>"  LOC = "Y5"  ;
+NET "io_rx<2>"  LOC = "R10"  ;
+NET "io_rx<1>"  LOC = "R1"  ;
+NET "io_rx<0>"  LOC = "M1"  ;
+
+## MISC
+NET "leds<5>"  LOC = "AF25"  ;
+NET "leds<4>"  LOC = "AE25"  ;
+NET "leds<3>"  LOC = "AF23"  ;
+NET "leds<2>"  LOC = "AE23"  ;
+NET "leds<1>"  LOC = "AB18"  ;
+NET "FPGA_RESET"  LOC = "K24"  ;
+
+## Debug
+NET "debug_clk<0>"  LOC = "AA10"  ;
+NET "debug_clk<1>"  LOC = "AD11"  ;
+NET "debug<0>"  LOC = "AC19"  ;
+NET "debug<1>"  LOC = "AF20"  ;
+NET "debug<2>"  LOC = "AE20"  ;
+NET "debug<3>"  LOC = "AC16"  ;
+NET "debug<4>"  LOC = "AB16"  ;
+NET "debug<5>"  LOC = "AF19"  ;
+NET "debug<6>"  LOC = "AE19"  ;
+NET "debug<7>"  LOC = "V15"  ;
+NET "debug<8>"  LOC = "U15"  ;
+NET "debug<9>"  LOC = "AE17"  ;
+NET "debug<10>"  LOC = "AD17"  ;
+NET "debug<11>"  LOC = "V14"  ;
+NET "debug<12>"  LOC = "W15"  ;
+NET "debug<13>"  LOC = "AC15"  ;
+NET "debug<14>"  LOC = "AD14"  ;
+NET "debug<15>"  LOC = "AC14"  ;
+NET "debug<16>"  LOC = "AC11"  ;
+NET "debug<17>"  LOC = "AB12"  ;
+NET "debug<18>"  LOC = "AC12"  ;
+NET "debug<19>"  LOC = "V13"  ;
+NET "debug<20>"  LOC = "W13"  ;
+NET "debug<21>"  LOC = "AE8"  ;
+NET "debug<22>"  LOC = "AF8"  ;
+NET "debug<23>"  LOC = "V12"  ;
+NET "debug<24>"  LOC = "W12"  ;
+NET "debug<25>"  LOC = "AB9"  ;
+NET "debug<26>"  LOC = "AC9"  ;
+NET "debug<27>"  LOC = "AC8"  ;
+NET "debug<28>"  LOC = "AB7"  ;
+NET "debug<29>"  LOC = "V11"  ;
+NET "debug<30>"  LOC = "U11"  ;
+NET "debug<31>"  LOC = "Y10"  ;
+
+## UARTS
+NET "TXD<3>"  LOC = "AD20"  ;
+NET "TXD<2>"  LOC = "AC20"  ;
+NET "TXD<1>"  LOC = "AD19"  ;
+NET "RXD<3>"  LOC = "AF17"  ;
+NET "RXD<2>"  LOC = "AF15"  ;
+NET "RXD<1>"  LOC = "AD12"  ;
+
+## AD9510
+NET "clk_status"  LOC = "AD22"  ;
+NET "CLK_FUNC"  LOC = "AC21"  ;
+NET "clk_sel<0>"  LOC = "AE21"  ;
+NET "clk_sel<1>"  LOC = "AD21"  ;
+NET "clk_en<1>"  LOC = "AA17"  ;
+NET "clk_en<0>"  LOC = "Y17"  ;
+
+## I2C
+NET "SDA"  LOC = "V16"  ;
+NET "SCL"  LOC = "U16"  ;
+
+## Timing
+NET "PPS_IN"  LOC = "AB6"  ;
+NET "PPS2_IN"  LOC = "AA20"  ;
+
+## SPI
+NET "SEN_CLK"  LOC = "AA18"  ;
+NET "MOSI_CLK"  LOC = "W17"  ;
+NET "SCLK_CLK"  LOC = "V17"  ;
+NET "MISO_CLK"  LOC = "AC10"  ;
+
+NET "SEN_DAC"  LOC = "AE7"  ;
+NET "SCLK_DAC"  LOC = "AF5"  ;
+NET "MOSI_DAC"  LOC = "AE6"  ;
+NET "MISO_DAC"  LOC = "Y3"  ;
+
+NET "SCLK_ADC"  LOC = "B1"  ;
+NET "MOSI_ADC"  LOC = "J8"  ;
+NET "SEN_ADC"  LOC = "J9"  ;
+
+NET "MOSI_TX_ADC"  LOC = "V10"  ;
+NET "SEN_TX_ADC"  LOC = "W10"  ;
+NET "SCLK_TX_ADC"  LOC = "AC6"  ;
+NET "MISO_TX_ADC"  LOC = "G1"  ;
+
+NET "MOSI_TX_DAC"  LOC = "AD6"  ;
+NET "SEN_TX_DAC"  LOC = "AE4"  ;
+NET "SCLK_TX_DAC"  LOC = "AF4"  ;
+
+NET "SCLK_TX_DB"  LOC = "AE3"  ;
+NET "MOSI_TX_DB"  LOC = "AF3"  ;
+NET "SEN_TX_DB"  LOC = "W9"  ;
+NET "MISO_TX_DB"  LOC = "AA5"  ;
+
+NET "MOSI_RX_ADC"  LOC = "E3"  ;
+NET "SCLK_RX_ADC"  LOC = "F4"  ;
+NET "SEN_RX_ADC"  LOC = "D3"  ;
+NET "MISO_RX_ADC"  LOC = "C1"  ;
+
+NET "SCLK_RX_DAC"  LOC = "E4"  ;
+NET "SEN_RX_DAC"  LOC = "K9"  ;
+NET "MOSI_RX_DAC"  LOC = "K8"  ;
+
+NET "SCLK_RX_DB"  LOC = "G6"  ;
+NET "MOSI_RX_DB"  LOC = "H7"  ;
+NET "SEN_RX_DB"  LOC = "B2"  ;
+NET "MISO_RX_DB"  LOC = "H4"  ;
+
+## ETH PHY
+NET "CLK_TO_MAC"  LOC = "P26"  ;
+
+NET "GMII_TXD<7>"  LOC = "G21"  ;
+NET "GMII_TXD<6>"  LOC = "C26"  ;
+NET "GMII_TXD<5>"  LOC = "C25"  ;
+NET "GMII_TXD<4>"  LOC = "J21"  ;
+NET "GMII_TXD<3>"  LOC = "H21"  ;
+NET "GMII_TXD<2>"  LOC = "D25"  ;
+NET "GMII_TXD<1>"  LOC = "D24"  ;
+NET "GMII_TXD<0>"  LOC = "E26"  ;
+NET "GMII_TX_EN"  LOC = "D26"  ;
+NET "GMII_TX_ER"  LOC = "J19"  ;
+NET "GMII_GTX_CLK"  LOC = "J20"  ;
+NET "GMII_TX_CLK"  LOC = "P25"  ;
+
+NET "GMII_RX_CLK"  LOC = "P21"  ;
+NET "GMII_RXD<7>"  LOC = "G22"  ;
+NET "GMII_RXD<6>"  LOC = "K19"  ;
+NET "GMII_RXD<5>"  LOC = "K18"  ;
+NET "GMII_RXD<4>"  LOC = "E24"  ;
+NET "GMII_RXD<3>"  LOC = "F23"  ;
+NET "GMII_RXD<2>"  LOC = "L18"  ;
+NET "GMII_RXD<1>"  LOC = "L17"  ;
+NET "GMII_RXD<0>"  LOC = "F25"  ;
+NET "GMII_RX_DV"  LOC = "F24"  ;
+NET "GMII_RX_ER"  LOC = "L20"  ;
+NET "GMII_CRS"  LOC = "K20"  ;
+NET "GMII_COL"  LOC = "G23"  ;
+
+NET "PHY_INTn"  LOC = "L22"  ;
+NET "MDIO"  LOC = "K21"  ;
+NET "MDC"  LOC = "J23"  ;
+NET "PHY_RESETn"  LOC = "J22"  ;
+NET "ETH_LED"  LOC = "H20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+
+## MIMO Interface
+NET "exp_time_out_p"  LOC = "Y14"  ;
+NET "exp_time_out_n"  LOC = "AA14"  ;
+NET "exp_time_in_p"  LOC = "N18"  ;
+NET "exp_time_in_n"  LOC = "N17"  ;
+NET "exp_user_out_p"  LOC = "AF14"  ;
+NET "exp_user_out_n"  LOC = "AE14"  ;
+NET "exp_user_in_p"  LOC = "L24"  ;
+NET "exp_user_in_n"  LOC = "M23"  ;
+
+## SERDES
+NET "ser_enable"  LOC = "R20"  ;
+NET "ser_prbsen"  LOC = "U23"  ;
+NET "ser_loopen"  LOC = "R19"  ;
+NET "ser_rx_en"  LOC = "Y21"  ;
+NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
+NET "ser_t<15>"  LOC = "V23"  ;
+NET "ser_t<14>"  LOC = "U22"  ;
+NET "ser_t<13>"  LOC = "V24"  ;
+NET "ser_t<12>"  LOC = "V25"  ;
+NET "ser_t<11>"  LOC = "W23"  ;
+NET "ser_t<10>"  LOC = "V22"  ;
+NET "ser_t<9>"  LOC = "T18"  ;
+NET "ser_t<8>"  LOC = "T17"  ;
+NET "ser_t<7>"  LOC = "Y24"  ;
+NET "ser_t<6>"  LOC = "Y25"  ;
+NET "ser_t<5>"  LOC = "U21"  ;
+NET "ser_t<4>"  LOC = "T20"  ;
+NET "ser_t<3>"  LOC = "Y22"  ;
+NET "ser_t<2>"  LOC = "Y23"  ;
+NET "ser_t<1>"  LOC = "U19"  ;
+NET "ser_t<0>"  LOC = "U18"  ;
+NET "ser_tkmsb"  LOC = "AA24"  ;
+NET "ser_tklsb"  LOC = "AA25"  ;
+NET "ser_rx_clk"  LOC = "P18"  ;
+NET "ser_r<15>"  LOC = "V21"  ;
+NET "ser_r<14>"  LOC = "U20"  ;
+NET "ser_r<13>"  LOC = "AA22"  ;
+NET "ser_r<12>"  LOC = "AA23"  ;
+NET "ser_r<11>"  LOC = "V18"  ;
+NET "ser_r<10>"  LOC = "V19"  ;
+NET "ser_r<9>"  LOC = "AB23"  ;
+NET "ser_r<8>"  LOC = "AC26"  ;
+NET "ser_r<7>"  LOC = "AB26"  ;
+NET "ser_r<6>"  LOC = "AD26"  ;
+NET "ser_r<5>"  LOC = "AC25"  ;
+NET "ser_r<4>"  LOC = "W20"  ;
+NET "ser_r<3>"  LOC = "W21"  ;
+NET "ser_r<2>"  LOC = "AC23"  ;
+NET "ser_r<1>"  LOC = "AC24"  ;
+NET "ser_r<0>"  LOC = "AE26"  ;
+NET "ser_rkmsb"  LOC = "AD25"  ;
+NET "ser_rklsb"  LOC = "Y20"  ;
+
+## SRAM
+NET "RAM_D<35>"  LOC = "K16"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<34>"  LOC = "D20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<33>"  LOC = "C20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<32>"  LOC = "E21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<31>"  LOC = "D21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<30>"  LOC = "C21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<29>"  LOC = "B21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<28>"  LOC = "H17"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<27>"  LOC = "G17"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<26>"  LOC = "B23"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<25>"  LOC = "A22"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<24>"  LOC = "D23"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<23>"  LOC = "C23"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<22>"  LOC = "D22"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<21>"  LOC = "C22"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<20>"  LOC = "F19"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<19>"  LOC = "G20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<18>"  LOC = "F20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<17>"  LOC = "F7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<16>"  LOC = "E7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<15>"  LOC = "G9"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<14>"  LOC = "H9"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<13>"  LOC = "G10"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<12>"  LOC = "H10"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<11>"  LOC = "A4"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<10>"  LOC = "B4"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<9>"  LOC = "C5"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<8>"  LOC = "D6"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<7>"  LOC = "J11"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<6>"  LOC = "K11"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<5>"  LOC = "B7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<4>"  LOC = "C7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<3>"  LOC = "B6"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<2>"  LOC = "C6"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<1>"  LOC = "C8"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<0>"  LOC = "D8"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<0>"  LOC = "C11"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<1>"  LOC = "E12"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<2>"  LOC = "F12"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<3>"  LOC = "D13"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<4>"  LOC = "C12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<5>"  LOC = "A12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<6>"  LOC = "B12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<7>"  LOC = "E14"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<8>"  LOC = "F14"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<9>"  LOC = "B15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<10>"  LOC = "A15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<11>"  LOC = "D16"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<12>"  LOC = "C15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<13>"  LOC = "D17"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<14>"  LOC = "C16"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<15>"  LOC = "F15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<16>"  LOC = "C17"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<17>"  LOC = "B17"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<18>"  LOC = "B18"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<19>"  LOC = "A18"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<20>"  LOC = "D18"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<3>"  LOC = "D9"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<2>"  LOC = "A9"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<1>"  LOC = "B9"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<0>"  LOC = "G12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_ZZ"  LOC = "J12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_LDn"  LOC = "H12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_OEn"  LOC = "C10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_WEn"  LOC = "D10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_CENn"  LOC = "B10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_CLK"  LOC = "A10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+
+## SPI Flash
+NET "flash_miso"  LOC = "AF24"  ;
+NET "flash_clk"  LOC = "AE24"  ;
+NET "flash_mosi"  LOC = "AB15"  ;
+NET "flash_cs"  LOC = "AA7"  ;
+
+## MISC FPGA, unused for now
+#NET "PROG_B"  LOC = "A2"  ;
+#NET "PUDC_B"  LOC = "G8"  ;
+#NET "DONE"  LOC = "AB21"  ;
+#NET "INIT_B"  LOC = "AA15"  ;
+
+
+#NET "unnamed_net19"  LOC = "AE9"  ;    # VS1
+#NET "unnamed_net18"  LOC = "AF9"  ;    # VS0
+#NET "unnamed_net17"  LOC = "AA12"  ;   # VS2
+#NET "unnamed_net16"  LOC = "Y7"  ;     # M2
+#NET "unnamed_net15"  LOC = "AC4"  ;    # M1
+#NET "unnamed_net14"  LOC = "AD4"  ;    # M0
+#NET "unnamed_net13"  LOC = "D4"  ;     # TMS
+#NET "unnamed_net12"  LOC = "E23"  ;    # TDO
+#NET "unnamed_net11"  LOC = "G7"  ;     # TDI
+#NET "unnamed_net10"  LOC = "A25"  ;    # TCK
+#NET "unnamed_net20"  LOC = "V20"  ;    # SUSPEND
+
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
+
+#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
+
+
diff --git a/fpga/usrp2/top/N2x0/u2plus.v b/fpga/usrp2/top/N2x0/u2plus.v
new file mode 100644
index 000000000..be1f355d2
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/u2plus.v
@@ -0,0 +1,473 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+`timescale 1ns / 1ps
+//`define LVDS 1
+//`define DCM_FOR_RAMCLK
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2plus
+  (
+   input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   
+   // ADC
+   input ADC_clkout_p, input ADC_clkout_n,
+   input ADCA_12_p, input ADCA_12_n,
+   input ADCA_10_p, input ADCA_10_n,
+   input ADCA_8_p, input ADCA_8_n,
+   input ADCA_6_p, input ADCA_6_n,
+   input ADCA_4_p, input ADCA_4_n,
+   input ADCA_2_p, input ADCA_2_n,
+   input ADCA_0_p, input ADCA_0_n,
+   input ADCB_12_p, input ADCB_12_n,
+   input ADCB_10_p, input ADCB_10_n,
+   input ADCB_8_p, input ADCB_8_n,
+   input ADCB_6_p, input ADCB_6_n,
+   input ADCB_4_p, input ADCB_4_n,
+   input ADCB_2_p, input ADCB_2_n,
+   input ADCB_0_p, input ADCB_0_n,
+   
+   // DAC
+   output reg [15:0] DACA,
+   output reg [15:0] DACB,
+   input DAC_LOCK,     // unused for now
+   
+   // DB IO Pins
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // Misc, debug
+   output [5:1] leds,  // LED4 is shared w/INIT_B
+   input FPGA_RESET,
+   output [1:0] debug_clk,
+   output [31:0] debug,
+   output [3:1] TXD, input [3:1] RXD, // UARTs
+   //input [3:0] dipsw,  // Forgot DIP Switches...
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input CLK_FUNC,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   inout SCL, inout SDA,   // I2C
+
+   // PPS
+   input PPS_IN, input PPS2_IN,
+
+   // SPI
+   output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK,
+   output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC,
+   output SEN_ADC, output SCLK_ADC, output MOSI_ADC,
+   output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,
+   output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC,
+   output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC,
+   output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,
+   output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC,
+   output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC,
+
+   // GigE PHY
+   input CLK_TO_MAC,
+
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   input GMII_RX_CLK,
+   input [7:0] GMII_RXD,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+   input GMII_COL,
+   input GMII_CRS,
+
+   input PHY_INTn,   // open drain
+   inout MDIO,
+   output MDC,
+   output PHY_RESETn,
+   output ETH_LED,
+   
+//   input POR,
+   
+   // Expansion
+   input exp_time_in_p, input exp_time_in_n, // Diff
+   output exp_time_out_p, output exp_time_out_n, // Diff 
+   input exp_user_in_p, input exp_user_in_n, // Diff
+   output exp_user_out_p, output exp_user_out_n, // Diff 
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+
+   // SRAM
+   inout [35:0] RAM_D,
+   output [20:0] RAM_A,
+   output [3:0] RAM_BWn,
+   output RAM_ZZ,
+   output RAM_LDn,
+   output RAM_OEn,
+   output RAM_WEn,
+   output RAM_CENn,
+   output RAM_CLK,
+   
+   // SPI Flash
+   output flash_cs,
+   output flash_clk,
+   output flash_mosi,
+   input flash_miso
+   );
+
+   wire  CLK_TO_MAC_int, CLK_TO_MAC_int2;
+   IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC));
+   BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int));
+      
+   // FPGA-specific pins connections
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD  = "LVDS_25";
+
+   wire 	exp_user_in;
+   IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n));
+   defparam 	exp_user_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_user_out;
+   OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out));
+   defparam 	exp_user_out_pin.IOSTANDARD  = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge clk_fpga)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+
+   // ADC A is inverted on the schematic to facilitate a clean layout
+   //  We account for that here by inverting it
+`ifdef LVDS
+   wire [13:0] 	adc_a, adc_a_inv, adc_b;
+   capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds
+     (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), 
+      .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p},
+	     {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), 
+      .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n},
+	     {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), 
+      .out({adc_a_inv,adc_b}));
+   assign adc_a = ~adc_a_inv;
+`else
+   reg [13:0] 	adc_a, adc_b, adc_a_pre, adc_b_pre;
+   always @(posedge dsp_clk)
+     begin
+	adc_a_pre <= {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n,
+		   ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n };
+	adc_b_pre <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n,
+		   ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n };
+	adc_a <= ~adc_a_pre; //Note: A must be inverted, but not B
+	adc_b <= adc_b_pre;
+     end
+`endif // !`ifdef LVDS
+   
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_fpga), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(), 
+                 .CLK180(), 
+                 .CLK270(clk270_100), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz.
+   BUFG  clk270_100_buf_i1 (.I(clk270_100), 
+			    .O(clk270_100_buf));
+   OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
+			.C0(clk270_100_buf),
+			.C1(~clk270_100_buf),
+			.CE(1'b1),
+			.D0(1'b1),
+			.D1(1'b0),
+			.R(1'b0),
+			.S(1'b0));
+  
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [5:0] leds_int;
+   assign     {ETH_LED,leds} = {6'b011111 ^ leds_int};  // drive low to turn on leds
+   
+   // SPI
+   wire       miso, mosi, sclk;
+
+   assign 	{SCLK_CLK,MOSI_CLK} 	   = ~SEN_CLK ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_DAC,MOSI_DAC} 	   = ~SEN_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_ADC,MOSI_ADC} 	   = ~SEN_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DB,MOSI_TX_DB}    = ~SEN_TX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DAC,MOSI_TX_DAC}  = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_ADC,MOSI_TX_ADC}  = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DB,MOSI_RX_DB}    = ~SEN_RX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DAC,MOSI_RX_DAC}  = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_ADC,MOSI_RX_ADC}  = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0;
+   
+   assign 	miso 			   = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) |
+					     (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) |
+					     (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC);
+   
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+   
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+
+
+   //
+   // Instantiate IO for Bidirectional bus to SRAM
+   //
+   wire [35:0] RAM_D_pi;
+   wire [35:0] RAM_D_po;
+   wire        RAM_D_poe;
+   
+   genvar      i;
+   
+   generate  
+      for (i=0;i<36;i=i+1)
+        begin : gen_RAM_D_IO
+
+	   IOBUF #(
+		   .DRIVE(12),
+		   .IOSTANDARD("LVCMOS25"),
+		   .SLEW("FAST")
+		   )
+	     RAM_D_i (
+		      .O(RAM_D_pi[i]),
+		      .I(RAM_D_po[i]),
+		      .IO(RAM_D[i]),
+		      .T(RAM_D_poe)
+		      );
+	end // block: gen_RAM_D_IO
+   endgenerate
+
+   
+   
+   wire [15:0] dac_a_int, dac_b_int;
+   // DAC A and B are swapped in schematic to facilitate clean layout
+   // DAC A is also inverted in schematic to facilitate clean layout
+   always @(negedge dsp_clk) DACA <= ~dac_b_int;
+   always @(negedge dsp_clk) DACB <= dac_a_int;
+
+   wire 	pps;
+   assign pps = PPS_IN ^ PPS2_IN;
+   
+   u2plus_core u2p_c(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(CLK_TO_MAC_int2),
+		     .pps_in		(pps),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_time_in	(exp_time_in),
+		     .exp_time_out	(exp_time_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(1'b0),
+		     .adc_on_a		(),
+		     .adc_oe_a		(),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(1'b0),
+		     .adc_on_b		(),
+		     .adc_oe_b		(),
+		     .dac_a		(dac_a_int[15:0]),
+		     .dac_b		(dac_b_int[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(SEN_CLK),
+		     .sen_dac		(SEN_DAC),
+		     .sen_adc           (SEN_ADC),
+		     .sen_tx_db		(SEN_TX_DB),
+		     .sen_tx_adc	(SEN_TX_ADC),
+		     .sen_tx_dac	(SEN_TX_DAC),
+		     .sen_rx_db		(SEN_RX_DB),
+		     .sen_rx_adc	(SEN_RX_ADC),
+		     .sen_rx_dac	(SEN_RX_DAC),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D_po          (RAM_D_po),
+		     .RAM_D_pi          (RAM_D_pi),
+		     .RAM_D_poe         (RAM_D_poe),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (TXD[3:1]),
+		     .uart_rx_i         ({1'b1,RXD[3:1]}),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2),
+		     .button            (FPGA_RESET),
+		     .spiflash_cs       (flash_cs),
+		     .spiflash_clk      (flash_clk),
+		     .spiflash_miso     (flash_miso),
+		     .spiflash_mosi     (flash_mosi)
+		     );
+
+   // Drive low so that RAM does not sleep.
+   assign RAM_ZZ = 0;
+   // Byte Writes are qualified by the global write enable
+   // Always do 36bit operations to extram.
+   assign RAM_BWn = 4'b0000;
+   
+endmodule // u2plus
diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v
new file mode 100644
index 000000000..703e157cc
--- /dev/null
+++ b/fpga/usrp2/top/N2x0/u2plus_core.v
@@ -0,0 +1,772 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2plus_core
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output [7:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_time_in,
+   output exp_time_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   input por,
+   output config_success,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_on_a,
+   output adc_oe_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_on_b,
+   output adc_oe_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_adc,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // External RAM
+   input [35:0] RAM_D_pi,
+   output [35:0] RAM_D_po,
+   output RAM_D_poe,
+   output [20:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // Debug stuff
+   output [3:0] uart_tx_o, 
+   input [3:0] uart_rx_i,
+   output [3:0] uart_baud_o,
+   input sim_mode,
+   input [3:0] clock_divider,
+   input button,
+   
+   output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi
+   );
+
+   localparam SR_MISC     =   0;   // 7 regs
+   localparam SR_USER_REGS =  8;   // 2
+   localparam SR_TIME64   =  10;   // 6
+   localparam SR_BUF_POOL =  16;   // 4
+   localparam SR_SPI_CORE  = 20;   // 3
+   localparam SR_RX_FRONT =  24;   // 5
+   localparam SR_RX_CTRL0 =  32;   // 9
+   localparam SR_RX_DSP0  =  48;   // 7
+   localparam SR_RX_CTRL1 =  80;   // 9
+   localparam SR_RX_DSP1  =  96;   // 7
+
+   localparam SR_TX_FRONT = 128;   // ?
+   localparam SR_TX_CTRL  = 144;   // 6
+   localparam SR_TX_DSP   = 160;   // 5
+
+   localparam SR_GPIO     = 184;   // 5   
+   localparam SR_UDP_SM   = 192;   // 64
+   
+   // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
+   // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
+   // localparam DSP_TX_FIFOSIZE = 9;  unused -- DSPTX uses extram fifo
+   localparam DSP_RX_FIFOSIZE = 10;
+   localparam DSP_TX_FIFOSIZE = 10;
+   localparam ETH_TX_FIFOSIZE = 9;
+   localparam ETH_RX_FIFOSIZE = 11;
+   localparam SERDES_TX_FIFOSIZE = 9;
+   localparam SERDES_RX_FIFOSIZE = 9;  // RX currently doesn't use a fifo?
+
+   wire [7:0]  set_addr, set_addr_dsp, set_addr_user;
+   wire [31:0] set_data, set_data_dsp, set_data_user;
+   wire        set_stb, set_stb_dsp, set_stb_user;
+
+   reg 		wb_rst; 
+   wire 	dsp_rst = wb_rst;
+   
+   wire [31:0] 	status;
+   wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
+   wire 	proc_int, overrun0, overrun1, underrun;
+   wire [3:0] 	uart_tx_int, uart_rx_int;
+
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+
+   wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2;
+
+   wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire 	ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+	
+   wire 	serdes_link_up, good_sync;
+   wire 	epoch;
+   wire [31:0] 	irq;
+   wire [63:0] 	vita_time, vita_time_pps;
+   
+   wire 	 run_rx0, run_rx1, run_tx;
+   reg 		 run_rx0_d1, run_rx1_d1;
+   
+   // ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   localparam 	dw = 32;  // Data bus width
+   localparam 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   localparam	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+   
+   wire [dw-1:0] m0_dat_o, m0_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+   wire 	 m0_err, m0_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we;
+   
+   wb_1master #(.decode_w(8),
+		.s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000),  // Main RAM (0-16K)
+		.s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000),  // Packet Router (16-20K)
+ 		.s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100),  // SPI
+		.s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100),  // I2C
+		.s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100),  // Unused
+		.s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100),  // Readback
+		.s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000),  // Ethernet MAC
+		.s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000),  // Settings Bus (only uses 1K)
+		.s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100),  // PIC
+		.s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100),  // Unused
+		.sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100),  // UART
+		.sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100),  // Unused
+		.sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000),  // Unused
+		.sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000),  // ICAP
+		.se_addr(8'b1011_0000),.se_mask(8'b1111_0000),  // SPI Flash
+		.sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000),  // 48K-64K, Boot RAM
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+      .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
+
+   assign s2_ack = 0;
+   assign s4_ack = 0;
+   assign s9_ack = 0;
+   assign sb_ack = 0;
+   assign sc_ack = 0;
+   
+   // ////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+
+   reg 		 cpu_bldr_ctrl_state;
+   localparam CPU_BLDR_CTRL_WAIT = 0;
+   localparam CPU_BLDR_CTRL_DONE = 1;
+   
+   wire 	 bldr_done;
+   wire 	 por_rst;
+   wire [aw-1:0] cpu_adr;
+
+   // Swap boot ram and main ram when in bootloader mode
+   assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr :
+		   cpu_adr ^ 16'hC000;
+   
+   system_control sysctrl 
+     (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) );
+   
+   always @(posedge wb_clk)
+     if(por_rst) begin
+        cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT;
+        wb_rst <= 1'b1;
+     end
+     else begin
+        case(cpu_bldr_ctrl_state)
+	  
+          CPU_BLDR_CTRL_WAIT: begin
+             wb_rst <= 1'b0;
+             if (bldr_done == 1'b1) begin //set by the bootloader
+                cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE;
+                wb_rst <= 1'b1;
+             end
+          end
+	  
+          CPU_BLDR_CTRL_DONE: begin //stay here forever
+             wb_rst <= 1'b0;
+          end
+	  
+        endcase //cpu_bldr_ctrl_state
+     end
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Processor
+
+   assign 	 bus_error = m0_err | m0_rty;
+
+   wire [63:0] zpu_status;
+   zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw))
+     zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst),
+	   // Data Wishbone bus to system bus fabric
+	   .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr),
+	   .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .zpu_status(zpu_status), .interrupt(proc_int & 1'b0));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone
+   // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone
+   // I-port connects directly to processor
+
+   bootram bootram(.clk(wb_clk), .reset(wb_rst),
+		   .if_adr(14'b0), .if_data(),
+		   .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i),
+		   .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel));
+
+////blinkenlights v0.1
+//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000;
+//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001;
+
+`include "bootloader.rmi"
+
+   ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384))
+   sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),	     
+	   .if_adr(14'b0), .if_data(),
+	   .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+	   .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool, slave #1
+   wire 	 rd0_ready_i, rd0_ready_o;
+   wire 	 rd1_ready_i, rd1_ready_o;
+   wire 	 rd2_ready_i, rd2_ready_o;
+   wire 	 rd3_ready_i, rd3_ready_o;
+   wire [35:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_ready_i, wr0_ready_o;
+   wire 	 wr1_ready_i, wr1_ready_o;
+   wire 	 wr2_ready_i, wr2_ready_o;
+   wire 	 wr3_ready_i, wr3_ready_o;
+   wire [35:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+
+   wire [35:0] sfc_wr_data, sfc_rd_data;
+   wire sfc_wr_ready, sfc_rd_ready;
+   wire sfc_wr_valid, sfc_rd_valid;
+
+   wire [35:0] 	 tx_err_data;
+   wire 	 tx_err_src_rdy, tx_err_dst_rdy;
+
+   wire [31:0] router_debug;
+
+   packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
+
+      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0),
+
+      .status(status), .sys_int_o(buffer_int), .debug(router_debug),
+
+      .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
+      .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),
+      .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),
+      .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+      .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy),
+      .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid),   .ctl_inp_ready(sfc_wr_ready),
+
+      .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
+      .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+      .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready),
+      .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
+      );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI -- Slave #2
+    wire [31:0] spi_debug;
+    wire [31:0] spi_readback;
+    wire spi_ready;
+    simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(9)) shared_spi(
+        .clock(dsp_clk), .reset(dsp_rst),
+        .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+        .readback(spi_readback), .ready(spi_ready),
+        .sen({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+        .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug)
+    );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_i[31:8] = 24'd0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs
+
+   wire [31:0] gpio_readback;
+   
+   gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) 
+   gpio_atr(.clk(dsp_clk),.reset(dsp_rst),
+	    .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+	    .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx),
+	    .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool Status -- Slave #5   
+   
+   //compatibility number -> increment when the fpga has been sufficiently altered
+   localparam compat_num = {16'd10, 16'd0}; //major, minor
+
+   wire [31:0] irq_readback = {18'b0, button, spi_ready, clk_status, serdes_link_up, 10'b0};
+
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
+
+      .word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+      .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
+      .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
+      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
+      .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
+      );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC  Slave #6
+
+   simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), 
+			  .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper
+     (.clk125(clk_to_mac),  .reset(wb_rst),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .sys_clk(dsp_clk),
+      .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+      .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
+      .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
+      .mdio(MDIO), .mdc(MDC),
+      .debug(debug_mac));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_dat_i = 32'd0;
+
+   wire set_stb_dsp0, set_stb_dsp1;
+   wire [31:0] set_data_dsp0, set_data_dsp1;
+   wire [7:0] set_addr_dsp0, set_addr_dsp1;
+
+   //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio
+   assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1;
+   assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0;
+   assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0;
+
+   settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock
+     (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
+      .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0),
+      .blocked(set_stb_dsp1));
+
+   user_settings #(.BASE(SR_USER_REGS)) user_settings
+     (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),
+      .set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_addr_user(set_addr_user),.set_data_user(set_data_user),
+      .set_stb_user(set_stb_user) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings + Readback Bus -- FIFO controlled
+
+    wire [31:0] sfc_debug;
+    wire sfc_clear;
+    settings_fifo_ctrl #(.PROT_DEST(3), .PROT_HDR(1)) sfc
+    (
+        .clock(dsp_clk), .reset(dsp_rst), .clear(sfc_clear),
+        .vita_time(vita_time), .perfs_ready(spi_ready),
+        .in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready),
+        .out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready),
+        .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1),
+        .word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+        .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
+        .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
+        .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
+        .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
+        .debug(sfc_debug)
+    );
+
+    setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_sfc
+     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear));
+
+   // Output control lines
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+   wire 	 phy_reset;
+   assign 	 PHY_RESETn = ~phy_reset;
+   
+   setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk
+     (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),.in(set_data),.out(clock_outs),.changed());
+
+   setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser
+     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(serdes_outs),.changed());
+
+   setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc
+     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(adc_outs),.changed());
+
+   setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy
+     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(phy_reset),.changed());
+
+   setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld
+     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(bldr_done),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
+   //  LEDS
+   //    register 8 determines whether leds are controlled by SW or not
+   //    1 = controlled by HW, 0 = by SW
+   //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+   
+   wire [7:0] 	 led_src, led_sw;
+   wire [7:0] 	 led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up & good_sync, 1'b0};
+   
+   setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led
+     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(led_sw),.changed());
+
+   setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src
+     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp), .in(set_data_dsp),.out(led_src),.changed());
+
+   assign 	 leds = (led_src & led_hw) | (~led_src & led_sw);
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+
+   assign irq= {{8'b0},
+		{uart_tx_int[3:0], uart_rx_int[3:0]},
+		{4'b0, clk_status, 3'b0},
+		{3'b0, PHY_INTn,i2c_int,spi_int,2'b00}};
+   
+   pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
+	   .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+	   .irq(irq) );
+ 	 
+   // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+      .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   // /////////////////////////////////////////////////////////////////////////
+   // ICAP for reprogramming the FPGA, Slave #13 (D)
+
+   s3a_icap_wb s3a_icap_wb
+     (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb),
+      .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI for Flash -- Slave #14 (E)
+   spi_top flash_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o),
+      .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb),
+      .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int),
+      .ss_pad_o(spiflash_cs),
+      .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // ADC Frontend
+   wire [23:0] 	 rx_fe_i, rx_fe_q;
+   
+   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
+      .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b),
+      .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX 0
+   wire [31:0] 	 sample_rx0;
+   wire 	 strobe_rx0, clear_rx0;
+
+   always @(posedge dsp_clk)
+     run_rx0_d1 <= run_rx0;
+   
+   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
+     (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
+      .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
+      .debug() );
+
+   vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(0)) vita_rx_chain0
+     (.clk(dsp_clk), .reset(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+      .vita_time(vita_time), .overrun(overrun0),
+      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
+      .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
+      .debug() );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX 1
+   wire [31:0] 	 sample_rx1;
+   wire 	 strobe_rx1, clear_rx1;
+
+   always @(posedge dsp_clk)
+     run_rx1_d1 <= run_rx1;
+   
+   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
+     (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
+      .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
+      .debug() );
+
+   vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(1)) vita_rx_chain1
+     (.clk(dsp_clk), .reset(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+      .vita_time(vita_time), .overrun(overrun1),
+      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
+      .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
+      .debug() );
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [35:0] 	 tx_data;
+   wire 	 tx_src_rdy, tx_dst_rdy;
+   wire [31:0] 	 debug_vt;
+   wire 	 clear_tx;
+
+   assign 	 RAM_A[20:18] = 3'b0;
+   
+   ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) 
+     ext_fifo_i1
+       (.int_clk(dsp_clk),
+	.ext_clk(dsp_clk),
+	.rst(dsp_rst | clear_tx),
+	.RAM_D_pi(RAM_D_pi),
+	.RAM_D_po(RAM_D_po),
+	.RAM_D_poe(RAM_D_poe),
+	.RAM_A(RAM_A[17:0]),
+	.RAM_WEn(RAM_WEn),
+	.RAM_CENn(RAM_CENn),
+	.RAM_LDn(RAM_LDn),
+	.RAM_OEn(RAM_OEn),
+	.RAM_CE1n(RAM_CE1n),
+	.datain(rd1_dat),
+	.src_rdy_i(rd1_ready_o),
+	.dst_rdy_o(rd1_ready_i),
+	.dataout(tx_data),
+	.src_rdy_o(tx_src_rdy),
+	.dst_rdy_i(tx_dst_rdy),
+	.debug(debug_extfifo),
+	.debug2(debug_extfifo2) );
+
+   wire [23:0] 	 tx_fe_i, tx_fe_q;
+   wire [31:0]   sample_tx;
+   wire strobe_tx;
+   
+   vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE),
+		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
+		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
+		   .DSP_NUMBER(0))
+   vita_tx_chain
+     (.clk(dsp_clk), .reset(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+      .vita_time(vita_time),
+      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
+      .sample(sample_tx), .strobe(strobe_tx),
+      .underrun(underrun), .run(run_tx), .clear_o(clear_tx),
+      .debug(debug_vt));
+
+   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
+     (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+      .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug() );
+
+   tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
+      .dac_a(dac_a), .dac_b(dac_b));
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+
+   serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   wire [31:0] 	 debug_sync;
+
+   time_64bit #(.BASE(SR_TIME64)) time_64bit
+     (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync));
+
+   // /////////////////////////////////////////////////////////////////////////////////////////
+   // Debug Pins
+  
+   assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac};
+   assign debug = 32'd0;
+   assign debug_gpio_0 = 32'd0;
+   assign debug_gpio_1 = 32'd0;
+   
+endmodule // u2_core